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    • 1. 发明申请
    • Managing Concurrent Serialized Interrupt Broadcast Commands In A Multi-Node, Symmetric Multiprocessing Computer
    • 在多节点对称多处理计算机中管理并发序列化中断广播命令
    • US20110320665A1
    • 2011-12-29
    • US12821752
    • 2010-06-23
    • Garrett M. DrapalaChristine C. JonesPak-Kin MakCraig R. Walters
    • Garrett M. DrapalaChristine C. JonesPak-Kin MakCraig R. Walters
    • G06F13/24
    • G06F13/24
    • Managing concurrent serialized interrupt broadcast commands in a multi-node, symmetric multiprocessing computer including receiving, by a communications adapter in a compute node, a plurality of serialized interrupt broadcast commands; receiving, by the communications adapter, a plurality of interrupt tags for the plurality of serialized interrupt broadcast commands, each interrupt tag including an identification of an interrupt service order for a serialized interrupt broadcast command; assigning, by the communications adapter, to each serialized interrupt broadcast command its interrupt tag; and if an interrupt tag assigned to a serialized interrupt broadcast command has an interrupt service order that matches a value of a current operation tag that identifies the next serialized interrupt broadcast command to be exposed to the one or more processors, exposing, by the communications adapter, the serialized interrupt broadcast command to the one or more processors on the compute node to be serviced.
    • 在多节点对称多处理计算机中管理并发的串行化中断广播命令,包括由计算节点中的通信适配器接收多个串行化的中断广播命令; 由通信适配器接收多个串行化中断广播命令的多个中断标签,每个中断标签包括用于串行化中断广播命令的中断服务命令的标识; 由通信适配器将每个序列化的中断广播命令分配给其中断标签; 并且如果分配给序列化中断广播命令的中断标签具有与当前操作标签的值相匹配的中断服务订单,该当前操作标签的值标识要暴露给所述一个或多个处理器的下一个串行化中断广播命令,则由通信适配器 将序列化的中断广播命令发送到要被服务的计算节点上的一个或多个处理器。
    • 6. 发明授权
    • Main memory operations in a symmetric multiprocessing computer
    • 对称多处理计算机中的主存储器操作
    • US09558119B2
    • 2017-01-31
    • US12821540
    • 2010-06-23
    • Garrett M. DrapalaPak-Kin MakArthur J. O'Neill, Jr.Craig R. Walters
    • Garrett M. DrapalaPak-Kin MakArthur J. O'Neill, Jr.Craig R. Walters
    • G06F12/08
    • G06F12/0828G06F12/0831
    • Main memory operation in a symmetric multiprocessing computer, the computer comprising one or more processors operatively coupled through a cache controller to at least one cache of main memory, the main memory shared among the processors, the computer further comprising input/output (‘I/O’) resources, including receiving, in the cache controller from an issuing resource, a memory instruction for a memory address, the memory instruction requiring writing data to main memory; locking by the cache controller the memory address against further memory operations for the memory address; advising the issuing resource of completion of the memory instruction before the memory instruction completes in main memory; issuing by the cache controller the memory instruction to main memory; and unlocking the memory address only after completion of the memory instruction in main memory.
    • 在对称多处理计算机中的主存储器操作,所述计算机包括通过高速缓存控制器操作地耦合到主存储器的至少一个高速缓存的一个或多个处理器,所述主存储器在所述处理器之间共享,所述计算机还包括输入/​​输出(“I / O')资源,包括从发行资源在高速缓存控制器中接收存储器地址的存储器指令,需要向主存储器写入数据的存储器指令; 由缓存控制器锁定存储器地址,以防止存储器地址的进一步存储器操作; 在存储器指令在主存储器中完成之前建议完成存储器指令的发布资源; 由缓存控制器发出存储器指令给主存储器; 并且仅在主存储器中的存储器指令完成之后解锁存储器地址。