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1. 发明授权

US08990507B2 Storing data in a system memory for a subsequent cache flush 有权
公开(公告)号：US08990507B2
公开(公告)日：2015-03-24
申请号：US13495383
申请日：2012-06-13
申请人： Michael A. Blake , Pak-Kin Mak , Timothy C. Bronson , Hieu T. Huynh , Kenneth D. Klapproth , Vesselina K. Papazova
发明人： Michael A. Blake , Pak-Kin Mak , Timothy C. Bronson , Hieu T. Huynh , Kenneth D. Klapproth , Vesselina K. Papazova
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0895 , G06F12/0804 , G06F12/0817 , G06F12/0891 , G06F12/128
摘要： Embodiments relate to storing data to a system memory. An aspect includes accessing successive entries of a cache directory having a plurality of directory entries by a stepper engine, where access to the cache directory is given a lower priority than other cache operations. It is determined that a specific directory entry in the cache directory has a change line state that indicates it is modified. A store operation is performed to send a copy of the specific corresponding cache entry to the system memory as part of a cache management function. The specific directory entry is updated to indicate that the change line state is unmodified.

2. 发明申请

US20110320700A1 Concurrent Refresh In Cache Memory 失效
标题翻译：缓存中并发刷新
公开(公告)号：US20110320700A1
公开(公告)日：2011-12-29
申请号：US12822364
申请日：2010-06-24
申请人： Timothy C. Bronson , Hieu T. Huynh , Charlie C. Hwang , Kenneth D. Klapproth
发明人： Timothy C. Bronson , Hieu T. Huynh , Charlie C. Hwang , Kenneth D. Klapproth
IPC分类号： G06F12/06
CPC分类号： G06F12/0846 , G06F12/0893
摘要： Concurrent refresh in a cache memory includes calculating a refresh time interval at a centralized refresh controller, the centralized refresh controller being common to all cache memory banks of the cache memory, transmitting a starting time of the refresh time interval to a bank controller, the bank controller being local to, and associated with, only one cache memory bank of the cache memory, sampling a continuous refresh status indicative of a number of refreshes necessary to maintain data within the cache memory bank associated with the bank controller, requesting a gap in a processing pipeline of the cache memory to facilitate the number of refreshes necessary, receiving a refresh grant in response to the requesting, and transmitting an encoded refresh command to the bank controller, the encoded refresh command indicating a number of refresh operations granted to the cache memory bank associated with the bank controller.
摘要翻译：高速缓冲存储器中的并发刷新包括计算集中式刷新控制器的刷新时间间隔，集中式刷新控制器对于高速缓存存储器的所有高速缓存存储体共同，将刷新时间间隔的开始时间发送到银行控制器，银行控制器本身并且仅与高速缓冲存储器的一个高速缓冲存储器组相关联，并且对与表示控制器相关联的高速缓存存储器中的数据进行维护所需的刷新次数的连续刷新状态进行采样，请求在处理高速缓冲存储器的流水线以便于所需的刷新次数，响应于请求接收刷新许可，并向编组控制器发送编码的刷新命令，编码的刷新命令指示授予高速缓冲存储器的刷新操作的次数与银行控制人有关的银行。

3. 发明授权

US06968415B2 Opaque memory region for I/O adapter transparent bridge 有权
标题翻译：不透明内存区域用于I / O适配器透明桥
公开(公告)号：US06968415B2
公开(公告)日：2005-11-22
申请号：US10113299
申请日：2002-03-29
申请人： Timothy C. Bronson , Stefan P. Jackowski , John M. Sheplock , Phillip G. Williams
发明人： Timothy C. Bronson , Stefan P. Jackowski , John M. Sheplock , Phillip G. Williams
IPC分类号： G06F13/36 , G06F13/40
CPC分类号： G06F13/4059
摘要： An opaque memory region for a bridge of an I/O adapter. The opaque memory region is inaccessible to memory transactions which traverse the bridge either from a primary bus to secondary bus or secondary bus to primary bus. As a result, memory transactions which target the opaque memory region are ignored by the bridge, allowing for the same address to exist on both sides of the bridge with different data stored in each. The implementation of the opaque memory region provides a means to complete memory transactions within I/O adapter subsystem memory, hence, relieving host computer system memory resources. In addition, a number of I/O adapters can be used in a host computer system where the host and all the I/O devices use some of the same memory addresses.
摘要翻译：用于I / O适配器的桥的不透明的存储器区域。不透明的存储器区域无法通过从主总线到次总线或辅助总线到主总线的桥接器的存储器事务。因此，桥接器忽略了针对不透明存储器区域的内存事务，允许在每个存储不同数据的网桥两侧存在相同的地址。不透明存储器区域的实现提供了在I / O适配器子系统存储器内完成存储器事务的手段，因此减轻了主机计算机系统存储器资源。此外，主机和所有I / O设备使用一些相同的内存地址的主机系统中可以使用多个I / O适配器。

4. 发明授权

US06442634B2 System and method for interrupt command queuing and ordering 有权
标题翻译：用于中断命令排队和排序的系统和方法
公开(公告)号：US06442634B2
公开(公告)日：2002-08-27
申请号：US09860309
申请日：2001-05-18
申请人： Timothy C. Bronson , Wai Ling Lee , Vincent P. Zeyak, Jr.
发明人： Timothy C. Bronson , Wai Ling Lee , Vincent P. Zeyak, Jr.
IPC分类号： G06F1300
CPC分类号： G06F13/4027
摘要： An input/output bus bridge and command queuing system includes an external interrupt router for receiving interrupt commands from bus unit controllers (BUCs) and responds with end of interrupt (EOI), interrupt return (INR) and interrupt reissue (IRR) commands. The interrupt router includes a first command queue for ordering EOI commands and a second command queue for ordering INR and IRR commands. A first in first out (FIFO) command queue orders bus memory mapped input output (MMIO) commands. The EOI commands are directed from the first command queue to the input of the FIFO command queue. The EOI commands and the MMIO commands are directed from the command queue to an input output bus and the INR and IRR commands are directed from the second command queue to the input output bus. In this way, strict ordering of EOI commands relative to MMIO accesses is maintained while simultaneously allowing INR and IRR commands to bypass enqueued MMIO accesses.
摘要翻译：输入/输出总线桥接器和命令排队系统包括外部中断路由器，用于从总线单元控制器（BUC）接收中断命令，并响应中断结束（EOI），中断返回（INR）和中断重发（IRR）命令。中断路由器包括用于排序EOI命令的第一命令队列和用于排序INR和IRR命令的第二命令队列。先进先出（FIFO）命令队列命令总线内存映射输入输出（MMIO）命令。 EOI命令从第一个命令队列指向FIFO命令队列的输入。 EOI命令和MMIO命令从命令队列引导到输入输出总线，INR和IRR命令从第二个命令队列引导到输入输出总线。以这种方式，维护相对于MMIO访问的EOI命令的严格排序，同时允许INR和IRR命令绕过入队的MMIO访问。

5. 发明授权

US08918587B2 Multilevel cache hierarchy for finding a cache line on a remote node 有权
标题翻译：用于在远程节点上查找缓存行的多级缓存层次结构
公开(公告)号：US08918587B2
公开(公告)日：2014-12-23
申请号：US13495373
申请日：2012-06-13
申请人： Timothy C. Bronson , Garrett M. Drapala , Michael A. Blake , Craig R. Walters , Pak-Kin Mak
发明人： Timothy C. Bronson , Garrett M. Drapala , Michael A. Blake , Craig R. Walters , Pak-Kin Mak
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0811 , G06F12/0817 , G06F12/0884 , G06F12/123
摘要： Embodiments relate to accessing a cache line on a multi-level cache system having a system memory. Based on a request for exclusive ownership of a specific cache line at the local node, requests are concurrently sent to the system memory and remote nodes of the plurality of nodes for the specific cache line by the local node. The specific cache line is found in a specific remote node. The specific remote node is one of the remote nodes. The specific cache line is removed from the specific remote node for exclusive ownership by another node. Based on the specified node having the specified cache line in ghost state, any subsequent fetch request is initiated for the specific cache line from the specific node encounters the ghost state. When the ghost state is encountered, the subsequent fetch request is directed only to nodes of the plurality of nodes.
摘要翻译：实施例涉及在具有系统存储器的多级缓存系统上访问高速缓存行。基于本地节点对特定高速缓存线的独占所有权的请求，请求被本地节点同时发送到用于特定高速缓存行的多个节点的系统内存和远程节点。在特定的远程节点中找到特定的高速缓存行。特定的远程节点是远程节点之一。从特定的远程节点中删除特定的高速缓存行以供另一个节点独占所有。基于具有指定缓存行在幽灵状态的指定节点，任何后续的提取请求将针对具体的缓存行启动，特定的缓存行遇到幽灵状态。当遇到鬼状态时，后续的提取请求仅被引导到多个节点的节点。

6. 发明授权

US08458405B2 Cache bank modeling with variable access and busy times 失效
标题翻译：缓存库建模与可变访问和繁忙时间
公开(公告)号：US08458405B2
公开(公告)日：2013-06-04
申请号：US12821891
申请日：2010-06-23
申请人： Timothy C. Bronson , Garrett M. Drapala , Hieu T. Huynh , Kenneth D. Klapproth
发明人： Timothy C. Bronson , Garrett M. Drapala , Hieu T. Huynh , Kenneth D. Klapproth
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0895
摘要： Various embodiments of the present invention manage access to a cache memory. In one embodiment, a set of cache bank availability vectors are generated based on a current set of cache access requests currently operating on a set of cache banks and at least a variable busy time of a cache memory includes the set of cache banks. The set of cache bank availability vectors indicate an availability of the set of cache banks. A set of cache access requests for accessing a set of given cache banks within the set of cache banks is received. At least one cache access request in the set of cache access requests is selected to access a given cache bank based on the a cache bank availability vectors associated with the given cache bank and the set of access request parameters associated with the at least one cache access that has been selected.
摘要翻译：本发明的各种实施例管理对高速缓冲存储器的访问。在一个实施例中，基于当前在一组高速缓存组上操作的当前高速缓存访问请求集合来生成一组高速缓存存储库可用性向量，并且至少高速缓冲存储器的可变繁忙时间包括该组缓存存储体。该组缓存库可用性向量指示该组缓存存储体的可用性。接收用于访问该组缓存组内的一组给定高速缓存存储体的一组缓存访问请求。选择该组高速缓存访问请求中的至少一个高速缓存访问请求以基于与给定高速缓存组相关联的高速缓存存储体可用性向量和与该至少一个高速缓存访问相关联的一组访问请求参数访问给定高速缓存组已被选中。

7. 发明授权

US08291157B2 Concurrent refresh in cache memory 失效
标题翻译：高速缓存中同时刷新
公开(公告)号：US08291157B2
公开(公告)日：2012-10-16
申请号：US12822364
申请日：2010-06-24
申请人： Timothy C. Bronson , Hieu T. Huynh , Charlie C. Hwang , Kenneth D. Klapproth
发明人： Timothy C. Bronson , Hieu T. Huynh , Charlie C. Hwang , Kenneth D. Klapproth
IPC分类号： G06F12/00
CPC分类号： G06F12/0846 , G06F12/0893
摘要： Concurrent refresh in a cache memory includes calculating a refresh time interval at a centralized refresh controller, the centralized refresh controller being common to all cache memory banks of the cache memory, transmitting a starting time of the refresh time interval to a bank controller, the bank controller being local to, and associated with, only one cache memory bank of the cache memory, sampling a continuous refresh status indicative of a number of refreshes necessary to maintain data within the cache memory bank associated with the bank controller, requesting a gap in a processing pipeline of the cache memory to facilitate the number of refreshes necessary, receiving a refresh grant in response to the requesting, and transmitting an encoded refresh command to the bank controller, the encoded refresh command indicating a number of refresh operations granted to the cache memory bank associated with the bank controller.
摘要翻译：高速缓冲存储器中的并发刷新包括计算集中式刷新控制器的刷新时间间隔，集中式刷新控制器对于高速缓存存储器的所有高速缓存存储体共同，将刷新时间间隔的开始时间发送到银行控制器，银行控制器本身并且仅与高速缓冲存储器的一个高速缓冲存储器组相关联，并且对与表示控制器相关联的高速缓存存储器中的数据进行维护所需的刷新次数的连续刷新状态进行采样，请求在处理高速缓冲存储器的流水线以便于所需的刷新次数，响应于请求接收刷新许可，并向编组控制器发送编码的刷新命令，编码的刷新命令指示授予高速缓冲存储器的刷新操作的次数与银行控制人有关的银行。

8. 发明授权

US08244972B2 Optimizing EDRAM refresh rates in a high performance cache architecture 失效
标题翻译：在高性能缓存架构中优化EDRAM刷新率
公开(公告)号：US08244972B2
公开(公告)日：2012-08-14
申请号：US12822830
申请日：2010-06-24
申请人： Timothy C. Bronson , Michael Fee , Arthur J. O'Neill, Jr. , Scott B. Swaney
发明人： Timothy C. Bronson , Michael Fee , Arthur J. O'Neill, Jr. , Scott B. Swaney
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0855
摘要： Controlling refresh request transmission rates in a cache comprising: a refresh requestor configured to transmit a refresh request to a cache memory at a first refresh rate, the first refresh rate comprising an interval, the interval comprising receiving a plurality of first signals, the first refresh rate corresponding to a maximum refresh rate, and a refresh counter operatively coupled to the refresh requestor and configured to reset in response to receiving a second signal, increment in response to receiving each of a plurality of refresh requests from the refresh requestor, and reset and transmit a current count to the refresh requestor in response to receiving a third signal, wherein the refresh requestor is configured to transmit a refresh request at a second refresh rate, in response to receiving the current count from the refresh counter and determining that the current count is greater than a refresh threshold.
摘要翻译：控制缓存中的刷新请求传输速率包括：刷新请求器，被配置为以第一刷新率向高速缓存存储器发送刷新请求，所述第一刷新率包括间隔，所述间隔包括接收多个第一信号，所述第一刷新速率对应于最大刷新率;以及刷新计数器，可操作地耦合到所述刷新请求器，并且被配置为响应于接收到第二信号而复位，响应于接收到来自所述刷新请求者的多个刷新请求中的每一个，响应于接收到第三信号将当前计数发送到刷新请求者，其中响应于从刷新计数器接收当前计数并确定当前计数，刷新请求器被配置为以第二刷新率发送刷新请求大于刷新阈值。

9. 发明申请

US20110320729A1 CACHE BANK MODELING WITH VARIABLE ACCESS AND BUSY TIMES 失效
标题翻译：具有可变访问和繁忙时间的高速缓存库建模
公开(公告)号：US20110320729A1
公开(公告)日：2011-12-29
申请号：US12821891
申请日：2010-06-23
申请人： TIMOTHY C. BRONSON , Garrett M. Drapala , Hieu T. Huynh , Kenneth D. Klapproth
发明人： TIMOTHY C. BRONSON , Garrett M. Drapala , Hieu T. Huynh , Kenneth D. Klapproth
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0895
摘要： Various embodiments of the present invention manage access to a cache memory. In one embodiment, a set of cache bank availability vectors are generated based on a current set of cache access requests currently operating on a set of cache banks and at least a variable busy time of a cache memory includes the set of cache banks. The set of cache bank availability vectors indicate an availability of the set of cache banks. A set of cache access requests for accessing a set of given cache banks within the set of cache banks is received. At least one cache access request in the set of cache access requests is selected to access a given cache bank based on the a cache bank availability vectors associated with the given cache bank and the set of access request parameters associated with the at least one cache access that has been selected.
摘要翻译：本发明的各种实施例管理对高速缓冲存储器的访问。在一个实施例中，基于当前在一组高速缓存组上操作的当前高速缓存访问请求集合来生成一组高速缓存存储库可用性向量，并且至少高速缓存存储器的可变繁忙时间包括该组高速缓冲存储器组。该组缓存库可用性向量指示该组缓存存储体的可用性。接收用于访问该组缓存组内的一组给定高速缓存存储体的一组缓存访问请求。选择该组高速缓存访问请求中的至少一个高速缓存访问请求以基于与给定高速缓存组相关联的高速缓存存储体可用性向量和与该至少一个高速缓存访问相关联的一组访问请求参数访问给定高速缓存组已被选中。

10. 发明授权

US06985990B2 System and method for implementing private devices on a secondary peripheral component interface 有权
公开(公告)号：US06985990B2
公开(公告)日：2006-01-10
申请号：US10114020
申请日：2002-03-29
申请人： Timothy C. Bronson , John M. Sheplock , Phillip G. Williams
发明人： Timothy C. Bronson , John M. Sheplock , Phillip G. Williams
IPC分类号： G06F13/36
CPC分类号： G06F13/4027
摘要： Private devices are implemented on the secondary interface of PCI bridge by re-routing the activation of device select signals (IDSEL) during the address phase of a Type 0 configuration operation on the secondary bus in response to a Type 1 configuration operation on its primary bus. Under control of a mask register and device select reroute circuit, if a configuration command on the primary interface attempts to activate the IDSEL line associated with one of the private, or reroute, devices on the secondary interface, a different IDSEL is activated to select a monitoring device on the secondary interface.

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