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1. 发明授权

US6151655A Computer system deadlock request resolution using timed pulses 失效
标题翻译：使用定时脉冲的计算机系统死锁请求分辨率
公开(公告)号：US6151655A
公开(公告)日：2000-11-21
申请号：US70432
申请日：1998-04-30
申请人： Christine Comins Jones , Pak-kin Mak , Michael A. Blake , Michael Fee , Gary Eugene Strait
发明人： Christine Comins Jones , Pak-kin Mak , Michael A. Blake , Michael Fee , Gary Eugene Strait
IPC分类号： G06F15/177 , G06F9/46 , G06F9/52 , G06F12/00
CPC分类号： G06F9/524
摘要： Disclosed is a hardware mechanism for detecting and avoiding potential deadlocks among requestors in a multiprocessor system, consisting of a plurality of CP's and I/O adapters connected to one or more shared storage controllers (SC's). Requests to each storage controller originate from external sources such as the CP's, the I/O adapters, and the other SC, as well as from internal sources, such as the hardware facilities used to process fetches and stores between the SC and main memory. All requests must be granted priority before beginning to execute, using a ranked priority order scheme. Specific sequences of requests may cause deadlocks, either due to high-priority requests using priority cycles and locking out low-priority requests, or as a result of requests of any priority level busying resources needed for the completion of other requests. The deadlock resolution mechanism described here monitors the length of time a request has been valid in the storage controller without completing, by checking the request register valid bits and utilizing a timed pulse, which is a subset of the pulse used to detect hangs within the SC. If the valid bit for a request register is on, and two timed pulses are received, an internal hang detect latch is set. If the valid bit is reset at any time, the detection logic and the internal hang detect latch are reset. When the internal hang detect latch is set, requests in progress are allowed to complete, and new requests are held in an inactive state, until the request which detected the internal hang is able to complete.
摘要翻译：公开了一种用于检测和避免多处理器系统中的请求者之间潜在的死锁的硬件机制，其由连接到一个或多个共享存储控制器（SC）的多个CP和I / O适配器组成。对每个存储控制器的请求源自诸如CP，I / O适配器和其他SC的外部源，以及来自内部源（例如用于处理SC和主存储器之间的获取和存储的硬件设施）。所有请求必须在开始执行之前被赋予优先级，使用排名优先顺序方案。特定的请求序列可能会由于高优先权请求使用优先级周期和锁定低优先级请求而导致死锁，或者由于完成其他请求所需的任何优先级级别的资源请求而产生死锁。这里描述的死锁解析机制通过检查请求寄存器有效位并利用定时脉冲来监视存储控制器中的请求已经有效的时间长度，并且使用定时脉冲，定时脉冲是用于检测SC内的挂起的脉冲的子集。如果请求寄存器的有效位为开，并且接收到两个定时脉冲，则设置内部挂起检测锁存器。如果有效位在任何时候被复位，则检测逻辑和内部挂起检测锁存器被复位。当设置内部挂起检测锁存器时，允许正在进行的请求完成，并且新的请求保持在非活动状态，直到检测到内部挂起的请求能够完成为止。

2. 发明授权

US6073182A Method of resolving deadlocks between competing requests in a multiprocessor using global hang pulse logic 失效
标题翻译：使用全局挂起脉冲逻辑解决多处理器中竞争请求之间的死锁的方法
公开(公告)号：US6073182A
公开(公告)日：2000-06-06
申请号：US70664
申请日：1998-04-30
申请人： Christine Comins Jones , Pak-kin Mak , Michael A. Blake , Michael Fee , Gary Eugene Strait
发明人： Christine Comins Jones , Pak-kin Mak , Michael A. Blake , Michael Fee , Gary Eugene Strait
IPC分类号： G06F13/16 , G06F15/16 , G06F15/173
CPC分类号： G06F13/1663
摘要： A method using a global hang pulse logic mechanism detects and resolves deadlocks among requesters to the storage controller of a symmetric multiprocessor system in which multiple central processors and I/O adapters are connected to one or more shared storage controllers. Deadlocks may occur in such a system due to specific sequences of requests, either because high priority requests use priority cycles and lock out low priority requests, or because requests of any priority level make resources needed for the completion of other requests too busy. The mechanism logic monitors the length of time a request has been valid in the storage controller without completing, by checking the request register valid bits, and by utilizing a timed pulse which is a subset of the pulse used to detect hangs within the storage controller. If the valid bit is reset at any time detection logic and an internal hang detect latch is set, Logic which allows requests in progress to complete, and holds new requests in an inactive state is activated when the internal hang latch is set and remains active until the request which detected the internal hang is able to complete, thus resetting the internal hang detect latch.
摘要翻译：使用全局挂起脉冲逻辑机制的方法检测并解决请求者之间的死锁到其中多个中央处理器和I / O适配器连接到一个或多个共享存储控制器的对称多处理器系统的存储控制器。由于高优先级请求使用优先级周期并锁定低优先级请求，或者由于任何优先级的请求使得完成其他请求太繁忙所需的资源，因此在这种系统中可能会由于特定的请求序列而在这样的系统中发生死锁。机制逻辑监视存储控制器中的请求已经有效的时间长度，而不需要通过检查请求寄存器有效位以及利用作为用于检测存储控制器内的挂起的脉冲的子集的定时脉冲来完成。如果有效位在任何时候被复位，则检测逻辑和内部挂起检测锁存器被置位，当内部挂起锁存器被设置并且保持有效时，激活允许正在进行中的请求完成并保持处于非活动状态的新请求的逻辑，直到检测到内部挂起的请求能够完成，从而重置内部挂起检测锁存器。

3. 发明授权

US06516393B1 Dynamic serialization of memory access in a multi-processor system 失效
标题翻译：在多处理器系统中的存储器访问的动态序列化
公开(公告)号：US06516393B1
公开(公告)日：2003-02-04
申请号：US09676185
申请日：2000-09-29
申请人： Michael Fee , Pak-kin Mak
发明人： Michael Fee , Pak-kin Mak
IPC分类号： G06F1200
CPC分类号： G06F12/084 , G06F12/0828 , G06F13/1663
摘要： A method for resolving address contention and prioritization of access to resources within a shared memory system includes dynamically creating ordered lists of requests for each contested resource. A new request is added to the lists only after a conflict is recognized. Since the resource conflict does not always exist, there is no impact to a request for an uncontested resources.
摘要翻译：一种用于解决在共享存储器系统内访问资源的地址竞争和优先级排列的方法包括动态地创建每个有争议的资源的请求的有序列表。只有在确认冲突之后，才会将新请求添加到列表中。由于资源冲突并不总是存在，因此对无争议资源的请求没有任何影响。

4. 发明授权

US06219758B1 False exception for cancelled delayed requests 失效
标题翻译：取消延迟请求的假异常
公开(公告)号：US06219758B1
公开(公告)日：2001-04-17
申请号：US09047579
申请日：1998-03-25
申请人： Jennifer Almoradie Navarro , Barry Watson Krumm , Chung-Lung Kevin Shum , Pak-kin Mak , Michael Fee
发明人： Jennifer Almoradie Navarro , Barry Watson Krumm , Chung-Lung Kevin Shum , Pak-kin Mak , Michael Fee
IPC分类号： G06F1200
CPC分类号： G06F12/1054
摘要： A central processor uses virtual addresses to access data via cache logic including a DAT and ART, and the cache logic accesses data in the hierarchical storage subsystem using absolute addresses to access data, a part of the first level of the cache memory includes a translator for virtual or real addresses to absolute addresses. When requests are sent for a data fetch and the requested data are not resident in the first level of cache the request for data is delayed and may be forwarded to a lower level of said hierarchical memory, and a delayed request may result in cancellation of any process during a delayed request that has the ability to send back an exception. A delayed request may be rescinded if the central processor has reached an interruptible stage in its pipeline logic at which point, a false exception is forced clearing all I the wait states while the central processor ignores the false exception. Forcing of an exception occurs during dynamic address translation (DAT) or during access register translation (ART). A request for data signal to the storage subsystem cancellation is settable by the first hierarchical level of cache logic. A false exception signal to the first level cache is settable by the storage subsystem logic.
摘要翻译：中央处理器使用虚拟地址通过包括DAT和ART的高速缓存逻辑来访问数据，并且高速缓存逻辑使用绝对地址访问分层存储子系统中的数据来访问数据，高速缓冲存储器的第一级的一部分包括用于虚拟或实际地址到绝对地址。当请求被发送用于数据提取并且所请求的数据不驻留在高速缓存的第一级时，数据请求被延迟并且可以被转发到所述分层存储器的较低级别，并且延迟的请求可能导致任何在具有发回异常的能力的延迟请求过程中。如果中央处理器在其流水线逻辑中达到可中断阶段，则可能会撤销延迟请求，此时在中央处理器忽略错误异常时，强制清除所有I等待状态的错误异常。动态地址转换（DAT）或访问寄存器转换（ART）期间发生异常的强制。对存储子系统取消的数据信号的请求可以由高速缓存逻辑的第一层级设置。存储子系统逻辑可以设置到第一级高速缓存的错误异常信号。

5. 发明申请

US20130339808A1 BITLINE DELETION 失效
公开(公告)号：US20130339808A1
公开(公告)日：2013-12-19
申请号：US13523633
申请日：2012-06-14
申请人： Ekaterina M. Ambroladze , Michael A. Blake , Michael Fee , Hieu T. Huynh , Patrick J. Meaney , Arthur J. O'Neill
发明人： Ekaterina M. Ambroladze , Michael A. Blake , Michael Fee , Hieu T. Huynh , Patrick J. Meaney , Arthur J. O'Neill
IPC分类号： G06F11/20
CPC分类号： G06F11/1064 , G06F11/073 , G06F11/076 , G06F11/08 , G11C2029/1204
摘要： Embodiments relate to a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line and recording a second address of the second error. Embodiments also include comparing the first and second bitline address, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching the first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to a third bitline address and deleting a location corresponding to the third cache line from available cache locations based on the activated bitline delete mode and the third bitline address matching the second bitline address.
摘要翻译：实施例涉及一种方法，包括当读取第一高速缓存行时检测第一错误，记录第一错误的第一地址，在读取第二高速缓存行时检测第二错误并记录第二错误的第二地址。实施例还包括比较第一和第二位线地址，比较第一和第二字线地址，基于匹配的第一和第二位线地址激活位线删除模式，并且不匹配第一和第二字线地址，在读取第三位线时检测第三错误记录第三错误的第三位线地址，将第二位线地址与第三位线地址进行比较，并且基于激活的位线删除模式和第三位线地址匹配从可用高速缓存位置删除与第三高速缓存行相对应的位置第二个位线地址。

6. 发明授权

US08788891B2 Bitline deletion 失效
标题翻译：位线删除
公开(公告)号：US08788891B2
公开(公告)日：2014-07-22
申请号：US13523633
申请日：2012-06-14
申请人： Ekaterina M. Ambroladze , Michael A. Blake , Michael Fee , Hieu T. Huynh , Patrick J. Meaney , Arthur J. O'Neill
发明人： Ekaterina M. Ambroladze , Michael A. Blake , Michael Fee , Hieu T. Huynh , Patrick J. Meaney , Arthur J. O'Neill
IPC分类号： G06F11/00 , G11C29/00 , G06F11/10 , G11C29/12
CPC分类号： G06F11/1064 , G06F11/073 , G06F11/076 , G06F11/08 , G11C2029/1204
摘要： Embodiments relate to a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line and recording a second address of the second error. Embodiments also include comparing the first and second bitline address, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching the first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to a third bitline address and deleting a location corresponding to the third cache line from available cache locations based on the activated bitline delete mode and the third bitline address matching the second bitline address.
摘要翻译：实施例涉及一种方法，包括当读取第一高速缓存行时检测第一错误，记录第一错误的第一地址，在读取第二高速缓存行时检测第二错误并记录第二错误的第二地址。实施例还包括比较第一和第二位线地址，比较第一和第二字线地址，基于匹配的第一和第二位线地址激活位线删除模式，并且不匹配第一和第二字线地址，在读取第三位线时检测第三错误记录第三错误的第三位线地址，将第二位线地址与第三位线地址进行比较，并且基于激活的位线删除模式和第三位线地址匹配从可用高速缓存位置删除与第三高速缓存行相对应的位置第二个位线地址。

7. 发明授权

US08539190B2 Preemptive in-pipeline store compare resolution 有权
标题翻译：抢先管道存储比较分辨率
公开(公告)号：US08539190B2
公开(公告)日：2013-09-17
申请号：US13459598
申请日：2012-04-30
申请人： Deanna Postles Dunn Berger , Michael Fee , Robert J. Sonnelitter
发明人： Deanna Postles Dunn Berger , Michael Fee , Robert J. Sonnelitter
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3834
摘要： A computer-implemented method that includes receiving a plurality of stores in a store queue, via a processor, comparing a fetch request against the store queue to search for a target store having a same memory address as the fetch request, determining whether the target store is ahead of the fetch request in a same pipeline, and processing the fetch request when it is determined that the target store is ahead of the fetch request.
摘要翻译：一种计算机实现的方法，其包括经由处理器在存储队列中接收多个存储，将获取请求与所述存储队列进行比较，以搜索具有与所述提取请求相同的存储器地址的目标存储器，确定所述目标存储在同一流水线中的提取请求之前，并且当确定目标存储位于提取请求之前时处理提取请求。

8. 发明授权

US08392621B2 Managing dataflow in a temporary memory 失效
标题翻译：在临时内存中管理数据流
公开(公告)号：US08392621B2
公开(公告)日：2013-03-05
申请号：US12820589
申请日：2010-06-22
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
IPC分类号： G06F3/00
CPC分类号： G06F11/0751 , G06F11/0724 , G06F11/073 , G06F12/0897 , Y02D10/13
摘要： A method of managing a temporary memory includes: receiving a request to transfer data from a source location to a destination location, the data transfer request associated with an operation to be performed, the operation selected from an input into an intermediate temporary memory and an output; checking a two-state indicator associated with the temporary memory, the two-state indicator having a first state indicating that an immediately preceding operation on the temporary memory was an input to the temporary memory and a second state indicating that the immediately preceding operation was an output from the temporary memory; and performing the operation responsive to one of: the operation being an input operation and the two-state indicator being in the second state, indicating that the immediately preceding operation was an output; and the operation being an output operation and the two-state indicator being in the first state, indicating that the immediately preceding operation was an input.
摘要翻译：管理临时存储器的方法包括：接收从源位置传送数据到目的地位置的请求，与要执行的操作相关联的数据传输请求，从输入中选择的中间临时存储器和输出 ; 检查与临时存储器相关联的两状态指示符，两状态指示符具有指示临时存储器上的紧接在前的操作是临时存储器的输入的第一状态，以及指示紧接在前的操作是第二状态的第二状态从临时存储器输出; 并且响应于以下操作中的一个执行操作：作为输入操作的操作和处于第二状态的两状态指示器，指示紧接在前的操作是输出; 操作是输出操作，两状态指示灯处于第一状态，表示紧接在前的操作是输入。

9. 发明授权

US08250243B2 Diagnostic data collection and storage put-away station in a multiprocessor system 失效
标题翻译：多处理器系统中的诊断数据采集和存储放置站
公开(公告)号：US08250243B2
公开(公告)日：2012-08-21
申请号：US12822704
申请日：2010-06-24
申请人： Deanna Postles Dunn Berger , Ekaterina M. Ambroladze , Michael Fee , Christine C. Jones
发明人： Deanna Postles Dunn Berger , Ekaterina M. Ambroladze , Michael Fee , Christine C. Jones
IPC分类号： G06F3/00
CPC分类号： G06F11/0778 , G06F11/0724 , G06F11/3636 , G06F11/3648 , G06F11/366
摘要： A computer-implemented method for collecting diagnostic data within a multiprocessor system that includes capturing diagnostic data via a plurality of collection points disposed at a source location within the multiprocessor system, routing the captured diagnostic data to a data collection station at the source location, providing a plurality of buffers within the data collection station, and temporarily storing the captured diagnostic data on at least one of the plurality of buffers, and transferring the captured diagnostic data to a target storage location on a same chip as the source location or another storage location on a same node.
摘要翻译：一种用于在多处理器系统内收集诊断数据的计算机实现的方法，其包括经由多处理器系统中的源位置处的多个收集点捕获诊断数据，将所捕获的诊断数据路由到源位置处的数据采集站，数据收集站内的多个缓冲器，并且将所捕获的诊断数据临时存储在多个缓冲器中的至少一个缓冲器上，并将捕获的诊断数据传送到与源位置或另一个存储位置相同的芯片上的目标存储位置在同一个节点上。

10. 发明授权

US08244972B2 Optimizing EDRAM refresh rates in a high performance cache architecture 失效
标题翻译：在高性能缓存架构中优化EDRAM刷新率
公开(公告)号：US08244972B2
公开(公告)日：2012-08-14
申请号：US12822830
申请日：2010-06-24
申请人： Timothy C. Bronson , Michael Fee , Arthur J. O'Neill, Jr. , Scott B. Swaney
发明人： Timothy C. Bronson , Michael Fee , Arthur J. O'Neill, Jr. , Scott B. Swaney
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0855
摘要： Controlling refresh request transmission rates in a cache comprising: a refresh requestor configured to transmit a refresh request to a cache memory at a first refresh rate, the first refresh rate comprising an interval, the interval comprising receiving a plurality of first signals, the first refresh rate corresponding to a maximum refresh rate, and a refresh counter operatively coupled to the refresh requestor and configured to reset in response to receiving a second signal, increment in response to receiving each of a plurality of refresh requests from the refresh requestor, and reset and transmit a current count to the refresh requestor in response to receiving a third signal, wherein the refresh requestor is configured to transmit a refresh request at a second refresh rate, in response to receiving the current count from the refresh counter and determining that the current count is greater than a refresh threshold.
摘要翻译：控制缓存中的刷新请求传输速率包括：刷新请求器，被配置为以第一刷新率向高速缓存存储器发送刷新请求，所述第一刷新率包括间隔，所述间隔包括接收多个第一信号，所述第一刷新速率对应于最大刷新率;以及刷新计数器，可操作地耦合到所述刷新请求器，并且被配置为响应于接收到第二信号而复位，响应于接收到来自所述刷新请求者的多个刷新请求中的每一个，响应于接收到第三信号将当前计数发送到刷新请求者，其中响应于从刷新计数器接收当前计数并确定当前计数，刷新请求器被配置为以第二刷新率发送刷新请求大于刷新阈值。

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