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1. 发明授权

US08392621B2 Managing dataflow in a temporary memory 失效
标题翻译：在临时内存中管理数据流
公开(公告)号：US08392621B2
公开(公告)日：2013-03-05
申请号：US12820589
申请日：2010-06-22
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
IPC分类号： G06F3/00
CPC分类号： G06F11/0751 , G06F11/0724 , G06F11/073 , G06F12/0897 , Y02D10/13
摘要： A method of managing a temporary memory includes: receiving a request to transfer data from a source location to a destination location, the data transfer request associated with an operation to be performed, the operation selected from an input into an intermediate temporary memory and an output; checking a two-state indicator associated with the temporary memory, the two-state indicator having a first state indicating that an immediately preceding operation on the temporary memory was an input to the temporary memory and a second state indicating that the immediately preceding operation was an output from the temporary memory; and performing the operation responsive to one of: the operation being an input operation and the two-state indicator being in the second state, indicating that the immediately preceding operation was an output; and the operation being an output operation and the two-state indicator being in the first state, indicating that the immediately preceding operation was an input.
摘要翻译：管理临时存储器的方法包括：接收从源位置传送数据到目的地位置的请求，与要执行的操作相关联的数据传输请求，从输入中选择的中间临时存储器和输出 ; 检查与临时存储器相关联的两状态指示符，两状态指示符具有指示临时存储器上的紧接在前的操作是临时存储器的输入的第一状态，以及指示紧接在前的操作是第二状态的第二状态从临时存储器输出; 并且响应于以下操作中的一个执行操作：作为输入操作的操作和处于第二状态的两状态指示器，指示紧接在前的操作是输出; 操作是输出操作，两状态指示灯处于第一状态，表示紧接在前的操作是输入。

2. 发明授权

US08244972B2 Optimizing EDRAM refresh rates in a high performance cache architecture 失效
标题翻译：在高性能缓存架构中优化EDRAM刷新率
公开(公告)号：US08244972B2
公开(公告)日：2012-08-14
申请号：US12822830
申请日：2010-06-24
申请人： Timothy C. Bronson , Michael Fee , Arthur J. O'Neill, Jr. , Scott B. Swaney
发明人： Timothy C. Bronson , Michael Fee , Arthur J. O'Neill, Jr. , Scott B. Swaney
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0855
摘要： Controlling refresh request transmission rates in a cache comprising: a refresh requestor configured to transmit a refresh request to a cache memory at a first refresh rate, the first refresh rate comprising an interval, the interval comprising receiving a plurality of first signals, the first refresh rate corresponding to a maximum refresh rate, and a refresh counter operatively coupled to the refresh requestor and configured to reset in response to receiving a second signal, increment in response to receiving each of a plurality of refresh requests from the refresh requestor, and reset and transmit a current count to the refresh requestor in response to receiving a third signal, wherein the refresh requestor is configured to transmit a refresh request at a second refresh rate, in response to receiving the current count from the refresh counter and determining that the current count is greater than a refresh threshold.
摘要翻译：控制缓存中的刷新请求传输速率包括：刷新请求器，被配置为以第一刷新率向高速缓存存储器发送刷新请求，所述第一刷新率包括间隔，所述间隔包括接收多个第一信号，所述第一刷新速率对应于最大刷新率;以及刷新计数器，可操作地耦合到所述刷新请求器，并且被配置为响应于接收到第二信号而复位，响应于接收到来自所述刷新请求者的多个刷新请求中的每一个，响应于接收到第三信号将当前计数发送到刷新请求者，其中响应于从刷新计数器接收当前计数并确定当前计数，刷新请求器被配置为以第二刷新率发送刷新请求大于刷新阈值。

3. 发明申请

US20110320919A1 HIGH PERFORMANCE CACHE DIRECTORY ERROR CORRECTION CODE 失效
标题翻译：高性能缓存目录错误修正代码
公开(公告)号：US20110320919A1
公开(公告)日：2011-12-29
申请号：US12822889
申请日：2010-06-24
申请人： Ekaterina M. Ambroladze , Patrick J. Meaney , Arthur J. O'Neill, JR.
发明人： Ekaterina M. Ambroladze , Patrick J. Meaney , Arthur J. O'Neill, JR.
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： G06F11/1064 , H03M13/19
摘要： Defining a set of correctable error and uncorrectable error syndrome code points, generating an error correction code (ECC) syndrome decode, regarding the uncorrectable error syndrome code points as “don't cares” and logically minimizing the ECC syndrome decode for the determination of the correctable error syndrome code points based on the regarding of the uncorrectable error syndrome code points as the “don't cares” whereby output data can be ignored for the uncorrectable error syndrome code points.
摘要翻译：定义一组可纠正的错误和不可校正的错误校正码代码点，产生纠错码（ECC）校正码解码，关于不可校正的错误校正码码点为“不关心”，并在逻辑上最小化ECC校验码解码以确定基于关于不可校正误差校验码码点的可校正误差校验码码点作为“不关心”，由此对于不可校正的误码校验码码点可以忽略输出数据。

4. 发明申请

US20110320721A1 DYNAMIC TRAILING EDGE LATENCY ABSORPTION FOR FETCH DATA FORWARDED FROM A SHARED DATA/CONTROL INTERFACE 失效
标题翻译：动态跟踪边缘对从数据/控制界面转发的数据进行数据采集
公开(公告)号：US20110320721A1
公开(公告)日：2011-12-29
申请号：US12822884
申请日：2010-06-24
申请人： Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, JR. , Robert J. Sonnelitter, III
发明人： Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, JR. , Robert J. Sonnelitter, III
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0888 , G06F12/0897 , G06F2212/1024
摘要： A computer-implemented method for managing data transfer in a multi-level memory hierarchy that includes receiving a fetch request for allocation of data in a higher level memory, determining whether a data bus between the higher level memory and a lower level memory is available, bypassing an intervening memory between the higher level memory and the lower level memory when it is determined that the data bus is available, and transferring the requested data directly from the higher level memory to the lower level memory.
摘要翻译：一种用于管理多级存储器层级中的数据传输的计算机实现的方法，包括：接收用于在较高级存储器中分配数据的提取请求，确定所述较高级存储器和较低级存储器之间的数据总线是否可用，当确定数据总线可用时，绕过高级存储器和较低级存储器之间的中间存储器，并将所请求的数据直接从较高级存储器传送到下级存储器。

5. 发明申请

US20090210629A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR SELECTIVELY PURGING CACHE ENTRIES 审中-公开
标题翻译：方法，系统和计算机程序产品，用于选择高速缓存进入
公开(公告)号：US20090210629A1
公开(公告)日：2009-08-20
申请号：US12032058
申请日：2008-02-15
申请人： Michael A. Blake , Christine C. Jones , Pak-kin Mak , Arthur J. O'Neill, JR.
发明人： Michael A. Blake , Christine C. Jones , Pak-kin Mak , Arthur J. O'Neill, JR.
IPC分类号： G06F12/08
CPC分类号： G06F12/0817
摘要： A method, system and computer program product for selectively purging entries in a cache of a computer system. The method includes determining a starting storage address and a length of the storage address range to be purged, determining preset values for a congruence class and a compartment of a cache directory, accessing the cache directory based on the preset value of the congruence class, and selecting an entry in the cache directory based on the preset value of the compartment, determining validity of the entry accessed by examining an ownership tag of the entry, comparing a line address of the entry with the starting storage address and a sum of the starting storage address and the length of the storage address range, and selectively purging the entry based on the comparison result.
摘要翻译：一种用于选择性地清除计算机系统的高速缓存中的条目的方法，系统和计算机程序产品。该方法包括确定要清除的存储地址范围的起始存储地址和长度，确定高速缓存目录的同余类和隔间的预设值，基于同余类的预设值访问高速缓存目录;以及基于所述隔室的所述预设值来选择所述缓存目录中的条目，通过检查所述条目的所有权标签来确定所访问的条目的有效性，将所述条目的行地址与所述起始存储地址进行比较，以及所述起始存储器地址和存储地址范围的长度，并且基于比较结果选择性地清除条目。

6. 发明授权

US09104581B2 eDRAM refresh in a high performance cache architecture 有权
标题翻译： eDRAM在高性能缓存架构中刷新
公开(公告)号：US09104581B2
公开(公告)日：2015-08-11
申请号：US12822245
申请日：2010-06-24
申请人： Michael Fee , Arthur J. O'Neill, Jr. , Robert J. Sonnelitter, III
发明人： Michael Fee , Arthur J. O'Neill, Jr. , Robert J. Sonnelitter, III
IPC分类号： G06F13/14 , G06F12/02 , G06F12/08 , G06F13/16 , G11C11/406
CPC分类号： G06F12/0893 , G06F13/14 , G06F13/16 , G06F13/1605 , G06F13/1636 , G11C11/406 , G11C11/40603 , G11C11/40618 , G11C2207/104
摘要： A memory refresh requestor, a memory request interpreter, a cache memory, and a cache controller on a single chip. The cache controller configured to receive a memory access request, the memory access request for a memory address range in the cache memory, detect that the cache memory located at the memory address range is available, and send the memory access request to the memory request interpreter when the memory address range is available. The memory request interpreter configured to receive the memory access request from the cache controller, determine if the memory access request is a request to refresh a contents of the memory address range, and refresh data in the memory address range when the memory access request is a request to refresh memory.
摘要翻译：在单个芯片上的存储器刷新请求器，存储器请求解释器，高速缓存存储器和高速缓存控制器。缓存控制器被配置为接收存储器访问请求，对高速缓冲存储器中的存储器地址范围的存储器访问请求，检测位于存储器地址范围的高速缓存存储器可用，并将存储器访问请求发送到存储器请求解释器当存储器地址范围可用时。存储器请求解释器被配置为从高速缓存控制器接收存储器访问请求，确定存储器访问请求是否是刷新存储器地址范围的内容的请求，以及当存储器访问请求是存储器访问请求时刷新存储器地址范围中的数据请求刷新内存。

7. 发明授权

US08671267B2 Monitoring processing time in a shared pipeline 失效
标题翻译：在共享管道中监视处理时间
公开(公告)号：US08671267B2
公开(公告)日：2014-03-11
申请号：US12822359
申请日：2010-06-24
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
IPC分类号： G06F9/30 , G06F9/40 , G06F13/00 , G06F3/00
CPC分类号： G06F9/3867 , G06F11/3419 , G06F11/3466 , G06F2201/88
摘要： A pipelined processing device includes: a device controller configured to receive a request to perform an operation; a plurality of subcontrollers configured to receive at least one instruction associated with the operation, each of the plurality of subcontrollers including a counter configured to generate an active time value indicating at least a portion of a time taken to process the at least one instruction; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor configured to receive the active time value; and a shared pipeline storage area configured to store the active time value for each of the plurality of subcontrollers.
摘要翻译：流水线处理装置包括：设备控制器，被配置为接收执行操作的请求; 多个子控制器被配置为接收与所述操作相关联的至少一个指令，所述多个子控制器中的每一个包括配置成生成指示处理所述至少一个指令所花费的时间的至少一部分的活动时间值的计数器; 流水线处理器，被配置为接收和处理所述至少一个指令，所述流水线处理器被配置为接收所述活动时间值; 以及共享流水线存储区域，被配置为存储多个子控制器中的每一个的活动时间值。

8. 发明授权

US08522076B2 Error detection and recovery in a shared pipeline 失效
标题翻译：共享管道中的错误检测和恢复
公开(公告)号：US08522076B2
公开(公告)日：2013-08-27
申请号：US12821871
申请日：2010-06-23
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
IPC分类号： G06F11/00
CPC分类号： G06F11/0751 , G06F11/0724 , G06F11/0793
摘要： A pipelined processing device includes: a processor configured to receive a request to perform an operation; a plurality of processing controllers configured to receive at least one instruction associated with the operation, each of the plurality of processing controllers including a memory to store at least one instruction therein; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor including shared error detection logic configured to detect a parity error in the at least one instruction as the at least one instruction is processed in a pipeline and generate an error signal; and a pipeline bus connected to each of the plurality of processing controllers and configured to communicate the error signal from the error detection logic.
摘要翻译：流水线处理装置包括：被配置为接收执行操作的请求的处理器; 多个处理控制器，被配置为接收与所述操作相关联的至少一个指令，所述多个处理控制器中的每个处理控制器包括用于在其中存储至少一个指令的存储器; 流水线处理器，被配置为接收和处理所述至少一个指令，所述流水线处理器包括被配置为在流水线中处理所述至少一个指令时检测所述至少一个指令中的奇偶校验错误的共享错误检测逻辑，并且生成错误信号 ; 以及连接到所述多个处理控制器中的每个处理控制器并被配置为传送来自所述错误检测逻辑的所述错误信号的流水线总线。

9. 发明申请

US20110320779A1 PERFORMANCE MONITORING IN A SHARED PIPELINE 失效
标题翻译：分布式管道中的性能监测
公开(公告)号：US20110320779A1
公开(公告)日：2011-12-29
申请号：US12822359
申请日：2010-06-24
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Arthur J. O'Neill, JR. , Diana L. Orf , Robert J. Sonnelitter, III
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Arthur J. O'Neill, JR. , Diana L. Orf , Robert J. Sonnelitter, III
IPC分类号： G06F9/30
CPC分类号： G06F9/3867 , G06F11/3419 , G06F11/3466 , G06F2201/88
摘要： A pipelined processing device includes: a device controller configured to receive a request to perform an operation; a plurality of subcontrollers configured to receive at least one instruction associated with the operation, each of the plurality of subcontrollers including a counter configured to generate an active time value indicating at least a portion of a time taken to process the at least one instruction; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor configured to receive the active time value; and a shared pipeline storage area configured to store the active time value for each of the plurality of subcontrollers.
摘要翻译：流水线处理装置包括：设备控制器，被配置为接收执行操作的请求; 多个子控制器被配置为接收与所述操作相关联的至少一个指令，所述多个子控制器中的每一个包括配置成生成指示处理所述至少一个指令所花费的时间的至少一部分的活动时间值的计数器; 流水线处理器，被配置为接收和处理所述至少一个指令，所述流水线处理器被配置为接收所述活动时间值; 以及共享流水线存储区域，被配置为存储多个子控制器中的每一个的活动时间值。

10. 发明申请

US20110320737A1 Main Memory Operations In A Symmetric Multiprocessing Computer 有权
标题翻译：对称多处理计算机中的主内存操作
公开(公告)号：US20110320737A1
公开(公告)日：2011-12-29
申请号：US12821540
申请日：2010-06-23
申请人： Garrett M. Drapala , Pak-Kin Mak , Arthur J. O'Neill, JR. , Craig R. Walters
发明人： Garrett M. Drapala , Pak-Kin Mak , Arthur J. O'Neill, JR. , Craig R. Walters
IPC分类号： G06F12/08 , G06F12/14 , G06F12/00
CPC分类号： G06F12/0828 , G06F12/0831
摘要： Main memory operation in a symmetric multiprocessing computer, the computer comprising one or more processors operatively coupled through a cache controller to at least one cache of main memory, the main memory shared among the processors, the computer further comprising input/output (‘I/O’) resources, including receiving, in the cache controller from an issuing resource, a memory instruction for a memory address, the memory instruction requiring writing data to main memory; locking by the cache controller the memory address against further memory operations for the memory address; advising the issuing resource of completion of the memory instruction before the memory instruction completes in main memory; issuing by the cache controller the memory instruction to main memory; and unlocking the memory address only after completion of the memory instruction in main memory.
摘要翻译：在对称多处理计算机中的主存储器操作，所述计算机包括通过高速缓存控制器操作地耦合到主存储器的至少一个高速缓存的一个或多个处理器，所述主存储器在所述处理器之间共享，所述计算机还包括输入/输出（“I / O'）资源，包括在缓存控制器中从发布资源接收存储器地址的存储器指令，需要向主存储器写入数据的存储器指令; 由缓存控制器锁定存储器地址，以防止存储器地址的进一步存储器操作; 在存储器指令在主存储器中完成之前建议完成存储器指令的发布资源; 由缓存控制器发出存储器指令给主存储器; 并且仅在主存储器中的存储器指令完成之后解锁存储器地址。

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