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1. 发明申请

US20110320755A1 TRACKING DYNAMIC MEMORY REALLOCATION USING A SINGLE STORAGE ADDRESS CONFIGURATION TABLE 失效
标题翻译：使用单个存储地址配置表跟踪动态内存重新安装
公开(公告)号：US20110320755A1
公开(公告)日：2011-12-29
申请号：US12821986
申请日：2010-06-23
申请人： Michael A. Blake , Pak-kin Mak , Michael F. Fee , Mark S. Farrell
发明人： Michael A. Blake , Pak-kin Mak , Michael F. Fee , Mark S. Farrell
IPC分类号： G06F12/06
CPC分类号： G06F12/0292
摘要： Tracking dynamic memory de-allocation using a single configuration table having a first register and a second register includes setting the first register as an active register, initiating a de-allocation of desired storage increments from a memory partition, setting the storage increments in the second register as invalid, purging all caches associated with the single configuration table, setting the second register as the active register and the first register as an inactive register, setting the desired storage increments in the first register as invalid, switching the active register from the second register to the first register to complete memory de-allocation using the single configuration table.
摘要翻译：使用具有第一寄存器和第二寄存器的单个配置表来跟踪动态存储器去分配包括将第一寄存器设置为活动寄存器，启动从存储器分区的期望存储增量的去分配，在第二寄存器中设置存储增量注册为无效，清除与单个配置表相关联的所有高速缓存，将第二个寄存器设置为活动寄存器，将第一个寄存器设置为非活动寄存器，将第一个寄存器中的所需存储增量设置为无效，将活动寄存器从第二个注册到第一个寄存器，使用单个配置表完成内存取消分配。

2. 发明授权

US08645642B2 Tracking dynamic memory reallocation using a single storage address configuration table 失效
标题翻译：使用单个存储地址配置表跟踪动态内存重新分配
公开(公告)号：US08645642B2
公开(公告)日：2014-02-04
申请号：US12821986
申请日：2010-06-23
申请人： Michael A. Blake , Pak-kin Mak , Michael F. Fee , Mark S. Farrell
发明人： Michael A. Blake , Pak-kin Mak , Michael F. Fee , Mark S. Farrell
IPC分类号： G06F12/00
CPC分类号： G06F12/0292
摘要： Tracking dynamic memory de-allocation using a single configuration table having a first register and a second register includes setting the first register as an active register, initiating a de-allocation of desired storage increments from a memory partition, setting the storage increments in the second register as invalid, purging all caches associated with the single configuration table, setting the second register as the active register and the first register as an inactive register, setting the desired storage increments in the first register as invalid, switching the active register from the second register to the first register to complete memory de-allocation using the single configuration table.
摘要翻译：使用具有第一寄存器和第二寄存器的单个配置表来跟踪动态存储器去分配包括将第一寄存器设置为活动寄存器，启动从存储器分区的期望存储增量的去分配，在第二寄存器中设置存储增量注册为无效，清除与单个配置表相关联的所有高速缓存，将第二个寄存器设置为活动寄存器，将第一个寄存器设置为非活动寄存器，将第一个寄存器中的所需存储增量设置为无效，将活动寄存器从第二个注册到第一个寄存器，使用单个配置表完成内存取消分配。

3. 发明授权

US08250305B2 Method, system and computer program product for data buffers partitioned from a cache array 有权
标题翻译：从缓存阵列分区的数据缓冲区的方法，系统和计算机程序产品
公开(公告)号：US08250305B2
公开(公告)日：2012-08-21
申请号：US12051244
申请日：2008-03-19
申请人： Gary E. Strait , Deanna P. Dunn , Michael F. Fee , Pak-kin Mak , Robert J. Sonnelitter, III
发明人： Gary E. Strait , Deanna P. Dunn , Michael F. Fee , Pak-kin Mak , Robert J. Sonnelitter, III
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/126 , G06F2212/2515
摘要： Systems, methods and computer program products for data buffers partitioned from a cache array. An exemplary embodiment includes a method in a processor and for providing data buffers partitioned from a cache array, the method including clearing cache directories associated with the processor to an initial state, obtaining a selected directory state from a control register preloaded by the service processor, in response to the control register including the desired cache state, sending load commands with an address and data, loading cache lines and cache line directory entries into the cache and storing the specified data in the corresponding cache line.
摘要翻译：从缓存阵列分区的数据缓冲区的系统，方法和计算机程序产品。示例性实施例包括处理器中的方法并且用于提供从高速缓存阵列分区的数据缓冲器，该方法包括将与处理器相关联的高速缓存目录清除到初始状态，从由服务处理器预加载的控制寄存器获得所选择的目录状态，响应于包括所需缓存状态的控制寄存器，发送具有地址和数据的加载命令，将高速缓存行和高速缓存行目录条目加载到高速缓存中并将指定的数据存储在相应的高速缓存行中。

4. 发明授权

US08180970B2 Least recently used (LRU) compartment capture in a cache memory system 有权
标题翻译：在缓存存储器系统中最近使用的（LRU）隔离区
公开(公告)号：US08180970B2
公开(公告)日：2012-05-15
申请号：US12035906
申请日：2008-02-22
申请人： Arthur J. O'Neill, Jr. , Michael F. Fee , Pak-kin Mak
发明人： Arthur J. O'Neill, Jr. , Michael F. Fee , Pak-kin Mak
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/123 , G06F12/0859
摘要： A two pipe pass method for least recently used (LRU) compartment capture in a multiprocessor system. The method includes receiving a fetch request via a requesting processor and accessing a cache directory based on the received fetch request, performing a first pipe pass by determining whether a fetch hit or a fetch miss has occurred in the cache directory, and determining an LRU compartment associated with a specified congruence class of the cache directory based on the fetch request received, when it is determined that a fetch miss has occurred, and performing a second pipe pass by using the LRU compartment determined and the specified congruence class to access the cache directory and to select an LRU address to be cast out of the cache directory.
摘要翻译：在多处理器系统中用于最近最少使用（LRU）隔室捕获的两个管道通过方法。该方法包括：通过请求处理器接收提取请求，并基于接收的提取请求访问高速缓存目录;通过确定高速缓存目录中是否发生了提取命中或提取丢失，执行第一管道通路，以及确定LRU隔间当确定已经发生提取未命中时，基于所接收的获取请求与缓存目录的指定同余类相关联，并且通过使用确定的LRU隔离区和指定的一致等级来访问高速缓存目录来执行第二管道传递并选择要从缓存目录中抛出的LRU地址。

5. 发明申请

US20090240891A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DATA BUFFERS PARTITIONED FROM A CACHE ARRAY 有权
标题翻译：方法，系统和计算机程序产品用于从缓存区域分配的数据缓冲区
公开(公告)号：US20090240891A1
公开(公告)日：2009-09-24
申请号：US12051244
申请日：2008-03-19
申请人： Gary E. Strait , Deanna P. Dunn , Michael F. Fee , Pak-kin Mak , Robert J. Sonnelitter, III
发明人： Gary E. Strait , Deanna P. Dunn , Michael F. Fee , Pak-kin Mak , Robert J. Sonnelitter, III
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F2212/2515
摘要： Systems, methods and computer program products for data buffers partitioned from a cache array. An exemplary embodiment includes a method in a processor and for providing data buffers partitioned from a cache array, the method including clearing cache directories associated with the processor to an initial state, obtaining a selected directory state from a control register preloaded by the service processor, in response to the control register including the desired cache state, sending load commands with an address and data, loading cache lines and cache line directory entries into the cache and storing the specified data in the corresponding cache line.
摘要翻译：从缓存阵列分区的数据缓冲区的系统，方法和计算机程序产品。示例性实施例包括处理器中的方法并且用于提供从高速缓存阵列分区的数据缓冲器，该方法包括将与处理器相关联的高速缓存目录清除到初始状态，从由服务处理器预加载的控制寄存器获得所选择的目录状态，响应于包括所需缓存状态的控制寄存器，发送具有地址和数据的加载命令，将高速缓存行和高速缓存行目录条目加载到高速缓存中并将指定的数据存储在相应的高速缓存行中。

6. 发明授权

US07779189B2 Method, system, and computer program product for pipeline arbitration 失效
标题翻译：管道仲裁的方法，系统和计算机程序产品
公开(公告)号：US07779189B2
公开(公告)日：2010-08-17
申请号：US12035249
申请日：2008-02-21
申请人： Deanna P. Dunn , Garrett M. Drapala , Michael F. Fee , Pak-kin Mak , Craig R. Walters
发明人： Deanna P. Dunn , Garrett M. Drapala , Michael F. Fee , Pak-kin Mak , Craig R. Walters
IPC分类号： G06F13/36 , G06F12/00 , G06F13/00 , H03M13/00
CPC分类号： G06F13/36
摘要： A method for pipeline arbitration including receiving a first request for a shared chip interface from a first pipeline, determining whether a response bus of the shared chip interface is needed by the first request, and if it is determined that the response bus is not needed by the first request, concluding that the first request needs just an address bus of the shared chip interface, arbitrating the first request with a second request for the shared chip interface received from a second pipeline for access to the address bus, sending the first request to the address bus if the first request wins the arbitration over the second request, and rejecting the first request if the second request wins the arbitration over the first request. A corresponding system and computer program product.
摘要翻译：一种用于流水线仲裁的方法，包括从第一流水线接收对共享芯片接口的第一请求，确定第一请求是否需要共享芯片接口的响应总线，以及如果确定不需要响应总线第一请求，认为第一请求仅需要共享芯片接口的地址总线，对从第二管道接收的用于访问地址总线的共享芯片接口的第二请求仲裁第一请求，将第一请求发送到所述地址总线如果所述第一请求通过所述第二请求获胜所述仲裁，并且如果所述第二请求通过所述第一请求获胜仲裁，则拒绝所述第一请求。相应的系统和计算机程序产品。

7. 发明申请

US20090216933A1 METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR PIPELINE ARBITRATION 失效
标题翻译：用于管道仲裁的方法，系统和计算机程序产品
公开(公告)号：US20090216933A1
公开(公告)日：2009-08-27
申请号：US12035249
申请日：2008-02-21
申请人： Deanna P. Dunn , Garrett M. Drapala , Michael F. Fee , Pak-kin Mak , Craig R. Walters
发明人： Deanna P. Dunn , Garrett M. Drapala , Michael F. Fee , Pak-kin Mak , Craig R. Walters
IPC分类号： G06F13/36
CPC分类号： G06F13/36
摘要： A method for pipeline arbitration including receiving a first request for a shared chip interface from a first pipeline, determining whether a response bus of the shared chip interface is needed by the first request, and if it is determined that the response bus is not needed by the first request, concluding that the first request needs just an address bus of the shared chip interface, arbitrating the first request with a second request for the shared chip interface received from a second pipeline for access to the address bus, sending the first request to the address bus if the first request wins the arbitration over the second request, and rejecting the first request if the second request wins the arbitration over the first request. A corresponding system and computer program product.
摘要翻译：一种用于流水线仲裁的方法，包括从第一流水线接收对共享芯片接口的第一请求，确定第一请求是否需要共享芯片接口的响应总线，以及如果确定不需要响应总线第一请求，认为第一请求仅需要共享芯片接口的地址总线，对从第二管道接收的用于访问地址总线的共享芯片接口的第二请求仲裁第一请求，将第一请求发送到所述地址总线如果所述第一请求通过所述第二请求获胜所述仲裁，并且如果所述第二请求通过所述第一请求获胜仲裁，则拒绝所述第一请求。相应的系统和计算机程序产品。

8. 发明申请

US20090216955A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR LRU COMPARTMENT CAPTURE 有权
标题翻译：方法，系统和计算机程序产品用于LRU间隔捕获
公开(公告)号：US20090216955A1
公开(公告)日：2009-08-27
申请号：US12035906
申请日：2008-02-22
申请人： Arthur J. O'Neill, JR. , Michael F. Fee , Pak-kin Mak
发明人： Arthur J. O'Neill, JR. , Michael F. Fee , Pak-kin Mak
IPC分类号： G06F12/00
CPC分类号： G06F12/123 , G06F12/0859
摘要： A two pipe pass method for least recently used (LRU) compartment capture in a multiprocessor system. The method includes receiving a fetch request via a requesting processor and accessing a cache directory based on the received fetch request, performing a first pipe pass by determining whether a fetch hit or a fetch miss has occurred in the cache directory, and determining an LRU compartment associated with a specified congruence class of the cache directory based on the fetch request received, when it is determined that a fetch miss has occurred, and performing a second pipe pass by using the LRU compartment determined and the specified congruence class to access the cache directory and to select an LRU address to be cast out of the cache directory.
摘要翻译：在多处理器系统中用于最近最少使用（LRU）隔室捕获的两个管道通过方法。该方法包括：通过请求处理器接收提取请求，并基于接收的提取请求访问高速缓存目录;通过确定高速缓存目录中是否发生了提取命中或提取丢失，执行第一管道通路，以及确定LRU隔间当确定已经发生提取未命中时，基于所接收的获取请求与缓存目录的指定同余类相关联，并且通过使用确定的LRU隔离区和指定的一致等级来访问高速缓存目录来执行第二管道传递并选择要从缓存目录中抛出的LRU地址。

9. 发明授权

US06988173B2 Bus protocol for a switchless distributed shared memory computer system 失效
标题翻译：总线协议用于无交换分布式共享内存计算机系统
公开(公告)号：US06988173B2
公开(公告)日：2006-01-17
申请号：US10435878
申请日：2003-05-12
申请人： Michael A. Blake , Steven M. German , Pak-kin Mak , Adrian E. Seigler , Gary A. Van Huben
发明人： Michael A. Blake , Steven M. German , Pak-kin Mak , Adrian E. Seigler , Gary A. Van Huben
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A bus protocol is disclosed for a symmetric multiprocessing computer system consisting of a plurality of nodes, each of which contains a multitude of processors, I/O devices, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. The bus protocol is used to exchange snoop requests and addresses, data, coherency information and operational status between nodes in a manner that allows partial coherency results to be passed in parallel with a snoop request and address as an operation is forwarded along each ring. Each node combines it's own coherency results with the partial coherency results it received prior to forwarding the snoop request, address and updated partial coherency results to the next node on the ring. The protocol allows each node in the system to see the final coherency results without requiring the requesting node to broadcast these results to all the other nodes in the system. The bus protocol also allows data to be returned on one of the two rings, with the ring selection determined by the relative placement of the source and destination nodes on each ring, in order to control latency and data bus utilization.
摘要翻译：公开了一种用于由多个节点组成的对称多处理计算机系统的总线协议，每个节点包含多个处理器，I / O设备，主存储器和包括具有顶级高速缓存的集成交换机的系统控制器。节点通过双同心环拓扑互连。总线协议用于以一种允许部分一致性结果与窥探请求和地址并行传送的方式来交换窥探请求和地址，数据，相关性信息和节点之间的操作状态，因为操作沿着每个环转发。每个节点将其自身的一致性结果与在将窥探请求转发之前接收的部分一致性结果相结合，将地址和更新的部分一致性结果合并到环上的下一个节点。该协议允许系统中的每个节点查看最终的一致性结果，而不需要请求节点将这些结果广播到系统中的所有其他节点。总线协议还允许在两个振铃中的一个上返回数据，其中环选择由每个振铃上的源节点和目的节点的相对位置确定，以便控制等待时间和数据总线的利用。

10. 发明授权

US6151655A Computer system deadlock request resolution using timed pulses 失效
标题翻译：使用定时脉冲的计算机系统死锁请求分辨率
公开(公告)号：US6151655A
公开(公告)日：2000-11-21
申请号：US70432
申请日：1998-04-30
申请人： Christine Comins Jones , Pak-kin Mak , Michael A. Blake , Michael Fee , Gary Eugene Strait
发明人： Christine Comins Jones , Pak-kin Mak , Michael A. Blake , Michael Fee , Gary Eugene Strait
IPC分类号： G06F15/177 , G06F9/46 , G06F9/52 , G06F12/00
CPC分类号： G06F9/524
摘要： Disclosed is a hardware mechanism for detecting and avoiding potential deadlocks among requestors in a multiprocessor system, consisting of a plurality of CP's and I/O adapters connected to one or more shared storage controllers (SC's). Requests to each storage controller originate from external sources such as the CP's, the I/O adapters, and the other SC, as well as from internal sources, such as the hardware facilities used to process fetches and stores between the SC and main memory. All requests must be granted priority before beginning to execute, using a ranked priority order scheme. Specific sequences of requests may cause deadlocks, either due to high-priority requests using priority cycles and locking out low-priority requests, or as a result of requests of any priority level busying resources needed for the completion of other requests. The deadlock resolution mechanism described here monitors the length of time a request has been valid in the storage controller without completing, by checking the request register valid bits and utilizing a timed pulse, which is a subset of the pulse used to detect hangs within the SC. If the valid bit for a request register is on, and two timed pulses are received, an internal hang detect latch is set. If the valid bit is reset at any time, the detection logic and the internal hang detect latch are reset. When the internal hang detect latch is set, requests in progress are allowed to complete, and new requests are held in an inactive state, until the request which detected the internal hang is able to complete.
摘要翻译：公开了一种用于检测和避免多处理器系统中的请求者之间潜在的死锁的硬件机制，其由连接到一个或多个共享存储控制器（SC）的多个CP和I / O适配器组成。对每个存储控制器的请求源自诸如CP，I / O适配器和其他SC的外部源，以及来自内部源（例如用于处理SC和主存储器之间的获取和存储的硬件设施）。所有请求必须在开始执行之前被赋予优先级，使用排名优先顺序方案。特定的请求序列可能会由于高优先权请求使用优先级周期和锁定低优先级请求而导致死锁，或者由于完成其他请求所需的任何优先级级别的资源请求而产生死锁。这里描述的死锁解析机制通过检查请求寄存器有效位并利用定时脉冲来监视存储控制器中的请求已经有效的时间长度，并且使用定时脉冲，定时脉冲是用于检测SC内的挂起的脉冲的子集。如果请求寄存器的有效位为开，并且接收到两个定时脉冲，则设置内部挂起检测锁存器。如果有效位在任何时候被复位，则检测逻辑和内部挂起检测锁存器被复位。当设置内部挂起检测锁存器时，允许正在进行的请求完成，并且新的请求保持在非活动状态，直到检测到内部挂起的请求能够完成为止。

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