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1. 发明授权

US09104583B2 On demand allocation of cache buffer slots 有权
标题翻译：缓存缓存槽的按需分配
公开(公告)号：US09104583B2
公开(公告)日：2015-08-11
申请号：US12822398
申请日：2010-06-24
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Diana Lynn Orf
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Diana Lynn Orf
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F12/0871
摘要： Dynamic allocation of cache buffer slots includes receiving a request to perform an operation that requires a storage buffer slot, the storage buffer slot residing in a level of storage. The dynamic allocation of cache buffer slots also includes determining availability of the storage buffer slot for the cache index as specified by the request. Upon determining the storage buffer slot is not available, the dynamic allocation of cache buffer slots includes evicting data stored in the storage buffer slot, and reserving the storage buffer slot for data associated with the request.
摘要翻译：高速缓存缓存槽的动态分配包括接收执行需要存储缓冲器时隙的操作的请求，存储缓冲槽位于存储级别。高速缓存缓存槽的动态分配还包括确定请求指定的高速缓存索引的存储缓冲区的可用性。在确定存储缓冲器时隙不可用时，高速缓存缓冲器时隙的动态分配包括驱逐存储在存储缓冲器时隙中的数据，并且为与请求相关联的数据保留存储缓冲器时隙。

2. 发明授权

US09104581B2 eDRAM refresh in a high performance cache architecture 有权
标题翻译： eDRAM在高性能缓存架构中刷新
公开(公告)号：US09104581B2
公开(公告)日：2015-08-11
申请号：US12822245
申请日：2010-06-24
申请人： Michael Fee , Arthur J. O'Neill, Jr. , Robert J. Sonnelitter, III
发明人： Michael Fee , Arthur J. O'Neill, Jr. , Robert J. Sonnelitter, III
IPC分类号： G06F13/14 , G06F12/02 , G06F12/08 , G06F13/16 , G11C11/406
CPC分类号： G06F12/0893 , G06F13/14 , G06F13/16 , G06F13/1605 , G06F13/1636 , G11C11/406 , G11C11/40603 , G11C11/40618 , G11C2207/104
摘要： A memory refresh requestor, a memory request interpreter, a cache memory, and a cache controller on a single chip. The cache controller configured to receive a memory access request, the memory access request for a memory address range in the cache memory, detect that the cache memory located at the memory address range is available, and send the memory access request to the memory request interpreter when the memory address range is available. The memory request interpreter configured to receive the memory access request from the cache controller, determine if the memory access request is a request to refresh a contents of the memory address range, and refresh data in the memory address range when the memory access request is a request to refresh memory.
摘要翻译：在单个芯片上的存储器刷新请求器，存储器请求解释器，高速缓存存储器和高速缓存控制器。缓存控制器被配置为接收存储器访问请求，对高速缓冲存储器中的存储器地址范围的存储器访问请求，检测位于存储器地址范围的高速缓存存储器可用，并将存储器访问请求发送到存储器请求解释器当存储器地址范围可用时。存储器请求解释器被配置为从高速缓存控制器接收存储器访问请求，确定存储器访问请求是否是刷新存储器地址范围的内容的请求，以及当存储器访问请求是存储器访问请求时刷新存储器地址范围中的数据请求刷新内存。

3. 发明授权

US08671267B2 Monitoring processing time in a shared pipeline 失效
标题翻译：在共享管道中监视处理时间
公开(公告)号：US08671267B2
公开(公告)日：2014-03-11
申请号：US12822359
申请日：2010-06-24
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
IPC分类号： G06F9/30 , G06F9/40 , G06F13/00 , G06F3/00
CPC分类号： G06F9/3867 , G06F11/3419 , G06F11/3466 , G06F2201/88
摘要： A pipelined processing device includes: a device controller configured to receive a request to perform an operation; a plurality of subcontrollers configured to receive at least one instruction associated with the operation, each of the plurality of subcontrollers including a counter configured to generate an active time value indicating at least a portion of a time taken to process the at least one instruction; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor configured to receive the active time value; and a shared pipeline storage area configured to store the active time value for each of the plurality of subcontrollers.
摘要翻译：流水线处理装置包括：设备控制器，被配置为接收执行操作的请求; 多个子控制器被配置为接收与所述操作相关联的至少一个指令，所述多个子控制器中的每一个包括配置成生成指示处理所述至少一个指令所花费的时间的至少一部分的活动时间值的计数器; 流水线处理器，被配置为接收和处理所述至少一个指令，所述流水线处理器被配置为接收所述活动时间值; 以及共享流水线存储区域，被配置为存储多个子控制器中的每一个的活动时间值。

4. 发明申请

US20130339808A1 BITLINE DELETION 失效
公开(公告)号：US20130339808A1
公开(公告)日：2013-12-19
申请号：US13523633
申请日：2012-06-14
申请人： Ekaterina M. Ambroladze , Michael A. Blake , Michael Fee , Hieu T. Huynh , Patrick J. Meaney , Arthur J. O'Neill
发明人： Ekaterina M. Ambroladze , Michael A. Blake , Michael Fee , Hieu T. Huynh , Patrick J. Meaney , Arthur J. O'Neill
IPC分类号： G06F11/20
CPC分类号： G06F11/1064 , G06F11/073 , G06F11/076 , G06F11/08 , G11C2029/1204
摘要： Embodiments relate to a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line and recording a second address of the second error. Embodiments also include comparing the first and second bitline address, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching the first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to a third bitline address and deleting a location corresponding to the third cache line from available cache locations based on the activated bitline delete mode and the third bitline address matching the second bitline address.
摘要翻译：实施例涉及一种方法，包括当读取第一高速缓存行时检测第一错误，记录第一错误的第一地址，在读取第二高速缓存行时检测第二错误并记录第二错误的第二地址。实施例还包括比较第一和第二位线地址，比较第一和第二字线地址，基于匹配的第一和第二位线地址激活位线删除模式，并且不匹配第一和第二字线地址，在读取第三位线时检测第三错误记录第三错误的第三位线地址，将第二位线地址与第三位线地址进行比较，并且基于激活的位线删除模式和第三位线地址匹配从可用高速缓存位置删除与第三高速缓存行相对应的位置第二个位线地址。

5. 发明授权

US08522076B2 Error detection and recovery in a shared pipeline 失效
标题翻译：共享管道中的错误检测和恢复
公开(公告)号：US08522076B2
公开(公告)日：2013-08-27
申请号：US12821871
申请日：2010-06-23
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
IPC分类号： G06F11/00
CPC分类号： G06F11/0751 , G06F11/0724 , G06F11/0793
摘要： A pipelined processing device includes: a processor configured to receive a request to perform an operation; a plurality of processing controllers configured to receive at least one instruction associated with the operation, each of the plurality of processing controllers including a memory to store at least one instruction therein; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor including shared error detection logic configured to detect a parity error in the at least one instruction as the at least one instruction is processed in a pipeline and generate an error signal; and a pipeline bus connected to each of the plurality of processing controllers and configured to communicate the error signal from the error detection logic.
摘要翻译：流水线处理装置包括：被配置为接收执行操作的请求的处理器; 多个处理控制器，被配置为接收与所述操作相关联的至少一个指令，所述多个处理控制器中的每个处理控制器包括用于在其中存储至少一个指令的存储器; 流水线处理器，被配置为接收和处理所述至少一个指令，所述流水线处理器包括被配置为在流水线中处理所述至少一个指令时检测所述至少一个指令中的奇偶校验错误的共享错误检测逻辑，并且生成错误信号 ; 以及连接到所述多个处理控制器中的每个处理控制器并被配置为传送来自所述错误检测逻辑的所述错误信号的流水线总线。

6. 发明授权

US08468536B2 Multiple level linked LRU priority 失效
标题翻译：多级链接LRU优先级
公开(公告)号：US08468536B2
公开(公告)日：2013-06-18
申请号：US12822514
申请日：2010-06-24
申请人： Deanna Postles Dunn Berger , Ekaterina M. Ambroladze , Michael Fee , Diana Lynn Orf
发明人： Deanna Postles Dunn Berger , Ekaterina M. Ambroladze , Michael Fee , Diana Lynn Orf
IPC分类号： G06F9/46 , G06F13/00 , G06F13/38
CPC分类号： G06F13/14
摘要： A method that includes providing LRU selection logic which controllably pass requests for access to computer system resources to a shared resource via a first level and a second level, determining whether a request in a request group is active, presenting the request to LRU selection logic at the first level, when it is determined that the request is active, determining whether the request is a LRU request of the request group at the first level, forwarding the request to the second level when it is determined that the request is the LRU request of the request group, comparing the request to an LRU request from each of the request groups at the second level to determine whether the request is a LRU request of the plurality of request groups, and selecting the LRU request of the plurality of request groups to access the shared resource.
摘要翻译：一种方法，其包括提供LRU选择逻辑，所述LRU选择逻辑可控制地将经由第一级别和第二级别访问计算机系统资源的请求传递给共享资源，确定请求组中的请求是否是活动的，向LRU选择逻辑呈现请求所述第一级当确定所述请求是活动时，确定所述请求是否是所述第一级请求组的LRU请求，当确定所述请求是所述请求的LRU请求时将所述请求转发到所述第二级别所述请求组将所述请求与来自所述第二级别的每个请求组的LRU请求进行比较，以确定所述请求是否是所述多个请求组的LRU请求，以及选择所述多个请求组的所述LRU请求以访问共享资源。

7. 发明授权

US08407442B2 Preemptive in-pipeline store compare resolution 失效
标题翻译：抢先管道存储比较分辨率
公开(公告)号：US08407442B2
公开(公告)日：2013-03-26
申请号：US12822734
申请日：2010-06-24
申请人： Deanna Postles Dunn Berger , Michael Fee , Robert J. Sonnelitter, III
发明人： Deanna Postles Dunn Berger , Michael Fee , Robert J. Sonnelitter, III
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3834
摘要： A computer-program product that includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving a plurality of stores in a store queue, via a processor, comparing a fetch request against the store queue to search for a target store having a same memory address as the fetch request, determining whether the target store is ahead of the fetch request in a same pipeline, and processing the fetch request when it is determined that the target store is ahead of the fetch request.
摘要翻译：一种计算机程序产品，其包括可由处理电路读取的有形存储介质，并且存储由处理电路执行以执行方法的指令。该方法包括经由处理器在存储队列中接收多个存储，将获取请求与存储队列进行比较，以搜索具有与获取请求相同的存储器地址的目标存储，确定目标存储是否在在同一流水线中提取请求，并且当确定目标存储在提取请求之前时处理该提取请求。

8. 发明申请

US20120215995A1 PREEMPTIVE IN-PIPELINE STORE COMPARE RESOLUTION 有权
标题翻译：预期的管道存储比较分辨率
公开(公告)号：US20120215995A1
公开(公告)日：2012-08-23
申请号：US13459598
申请日：2012-04-30
申请人： Deanna Postles Dunn Berger , Michael Fee , Robert J. Sonnelitter, III
发明人： Deanna Postles Dunn Berger , Michael Fee , Robert J. Sonnelitter, III
IPC分类号： G06F12/00
CPC分类号： G06F9/3834
摘要： A computer-implemented method that includes receiving a plurality of stores in a store queue, via a processor, comparing a fetch request against the store queue to search for a target store having a same memory address as the fetch request, determining whether the target store is ahead of the fetch request in a same pipeline, and processing the fetch request when it is determined that the target store is ahead of the fetch request.
摘要翻译：一种计算机实现的方法，其包括经由处理器在存储队列中接收多个存储，将获取请求与所述存储队列进行比较，以搜索具有与所述提取请求相同的存储器地址的目标存储器，确定所述目标存储在同一流水线中的提取请求之前，并且当确定目标存储位于提取请求之前时处理提取请求。

9. 发明申请

US20110320779A1 PERFORMANCE MONITORING IN A SHARED PIPELINE 失效
标题翻译：分布式管道中的性能监测
公开(公告)号：US20110320779A1
公开(公告)日：2011-12-29
申请号：US12822359
申请日：2010-06-24
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Arthur J. O'Neill, JR. , Diana L. Orf , Robert J. Sonnelitter, III
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Arthur J. O'Neill, JR. , Diana L. Orf , Robert J. Sonnelitter, III
IPC分类号： G06F9/30
CPC分类号： G06F9/3867 , G06F11/3419 , G06F11/3466 , G06F2201/88
摘要： A pipelined processing device includes: a device controller configured to receive a request to perform an operation; a plurality of subcontrollers configured to receive at least one instruction associated with the operation, each of the plurality of subcontrollers including a counter configured to generate an active time value indicating at least a portion of a time taken to process the at least one instruction; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor configured to receive the active time value; and a shared pipeline storage area configured to store the active time value for each of the plurality of subcontrollers.
摘要翻译：流水线处理装置包括：设备控制器，被配置为接收执行操作的请求; 多个子控制器被配置为接收与所述操作相关联的至少一个指令，所述多个子控制器中的每一个包括配置成生成指示处理所述至少一个指令所花费的时间的至少一部分的活动时间值的计数器; 流水线处理器，被配置为接收和处理所述至少一个指令，所述流水线处理器被配置为接收所述活动时间值; 以及共享流水线存储区域，被配置为存储多个子控制器中的每一个的活动时间值。

10. 发明申请

US20070300095A1 Double Data Rate Chaining for Synchronous DDR Interfaces 失效
标题翻译：双数据速率链接同步DDR接口
公开(公告)号：US20070300095A1
公开(公告)日：2007-12-27
申请号：US11426651
申请日：2006-06-27
申请人： Michael Fee , Patrick J. Meaney , Christopher J. Berry , Jonathan Y. Chen , Alan P. Wagstaff
发明人： Michael Fee , Patrick J. Meaney , Christopher J. Berry , Jonathan Y. Chen , Alan P. Wagstaff
IPC分类号： G06F1/12
CPC分类号： G06F13/4217
摘要： A system and method in which the receiving chip separately latches each half of the data received from the double data rate bus. Each half is launched as soon as it is available; one on the normal chip cycle time and the other is launched from a Master (L1) latch a half cycle into the normal chip cycle time. The first launched half of the data proceeds through the chip along its standard design chip path to be captured by the chips driving interface latch and launched again after one cycle of latency on the chip. The second half of the data proceeds through the chip one half cycle behind the first half, and is latched a half clock cycle later part way through the path into a Slave (L2) latch. On the next edge of the local clock, the data then continues from the L2 latch to the driving double data rate interface. This allows a half cycle set up time for the second half of the data so that it can be launched again, maintaining a one-cycle time on the chip.
摘要翻译：一种系统和方法，其中接收芯片分别锁存从双数据速率总线接收的数据的每一半。每一半都可以立即启动; 一个在正常的芯片周期时间，另一个从主（L1）锁存器半个周期启动到正常的芯片周期时间。首先推出的一半数据通过芯片沿其标准设计芯片路径进行，由芯片驱动接口锁存器捕获，并在芯片上的一个延迟周期后再次启动。数据的后半部分通过芯片在上半部分后半个周期进行，并且稍后通过进入从（L2）锁存器的路径被锁存半个时钟周期。在本地时钟的下一个边缘，数据然后从L2锁存器继续到驱动双数据速率接口。这允许半周期的半周期设置时间，以便可以再次启动，在芯片上保持一个周期的时间。

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