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21. 发明授权

US06913960B2 Fin-based double poly dynamic threshold CMOS FET with spacer gate and method of fabrication 失效
标题翻译：基于鳍的双重多晶硅动态阈值CMOS FET与间隔栅极和制造方法
公开(公告)号：US06913960B2
公开(公告)日：2005-07-05
申请号：US10843029
申请日：2004-05-11
申请人： Andres Bryant , K. Paul Muller , Edward J. Nowak
发明人： Andres Bryant , K. Paul Muller , Edward J. Nowak
IPC分类号： H01L21/28 , H01L21/336 , H01L21/84 , H01L27/12 , H01L29/423 , H01L29/78 , H01L29/786 , H01L21/8238
CPC分类号： H01L29/785 , H01L21/2815 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66795 , H01L29/783
摘要： The present invention provides a dynamic threshold (DT) CMOS FET and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a DT CMOS FET with a short, low resistance connection between the gate and the body and with low body-source/drain capacitance. The low body-source/drain capacitance is achieved using a thin, fin-type body. The low resistance connection between the gate and the body contact is achieved by having the gate and body contact aligned on opposite long sides of the fin with a bridge over the top of the narrow fin electrically connecting the gate and body.
摘要翻译：本发明提供一种动态阈值（DT）CMOS FET及其形成方法，其导致改进的器件性能和密度。本发明的优选实施例提供一种DT CMOS FET，其在栅极和主体之间具有短的低电阻连接，并且具有低的体源/漏极电容。低体积/漏极电容使用薄的翅片型体实现。栅极和体接触之间的低电阻连接是通过使栅极和主体接触在翅片的相对的长边上对准来实现的，桥与电极连接门和主体的窄鳍的顶部之间形成一个桥。

22. 发明授权

US06657261B2 Ground-plane device with back oxide topography 有权
公开(公告)号：US06657261B2
公开(公告)日：2003-12-02
申请号：US09757317
申请日：2001-01-09
申请人： Fariborz Assaderaghi , Tze-chiang Chen , K. Paul Muller , Edward J. Nowak , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Fariborz Assaderaghi , Tze-chiang Chen , K. Paul Muller , Edward J. Nowak , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L29/78603
摘要： A ground-plane SOI device including at least a gate region that is formed on a top Si-containing layer of a SOI wafer, said top Si-containing layer being formed on a non-planar buried oxide layer, wherein said non-planar buried oxide layer has a thickness beneath the gate region that is thinner than corresponding oxide layers that are formed in regions not beneath said gate region as well as a method of fabricating the same are provided.

23. 发明授权

US06541317B2 Polysilicon doped transistor 失效
公开(公告)号：US06541317B2
公开(公告)日：2003-04-01
申请号：US09848466
申请日：2001-05-03
申请人： K. Paul Muller , Dominic J. Schepis , Ghavam G. Shahidi
发明人： K. Paul Muller , Dominic J. Schepis , Ghavam G. Shahidi
IPC分类号： H01L2100
CPC分类号： H01L29/66553 , H01L21/2257 , H01L21/7624 , H01L29/41766 , H01L29/665 , H01L29/66507 , H01L29/66545 , H01L29/66621
摘要： Steep concentration gradients are achieved in semiconductor device of small sizes by using implanted polycrystalline material such as polysilicon as a solid diffusion source. Rapid diffusion of impurities along grain boundaries relative to diffusion rates in monocrystalline materials provides a substantially constant impurity concentration at the interface between polycrystalline material and monocrystalline material. Steepness of the impurity concentration gradient is thus effectively scaled as transistor size is decreased to counter increased short channel and other deleterious effects.

24. 发明授权

US06521949B2 SOI transistor with polysilicon seed 有权
标题翻译：具有多晶硅种子的SOI晶体管
公开(公告)号：US06521949B2
公开(公告)日：2003-02-18
申请号：US09848508
申请日：2001-05-03
申请人： Fariborz Assaderaghi , Tze-Chiang Chen , K. Paul Muller , Edward J. Nowak , Ghavam G. Shahidi
发明人： Fariborz Assaderaghi , Tze-Chiang Chen , K. Paul Muller , Edward J. Nowak , Ghavam G. Shahidi
IPC分类号： H01L2701
CPC分类号： H01L29/66757 , H01L29/66772 , H01L29/78618 , H01L29/78651 , H01L29/78675
摘要： Short channel effects are effectively suppressed by steep impurity concentration gradients which can be placed with improved accuracy of location and geometry while relaxing process tolerances by implanting impurities in a polysilicon seed adjacent a conduction channel of a transistor and diffusing impurities therefrom into the conduction channel. The polysilicon seed also allows the epitaxial growth of polysilicon source/drain contacts therefrom having a configuration which minimizes current density and path length therein while providing further mechanical advantages.
摘要翻译：通过陡峭的杂质浓度梯度有效地抑制了短沟道效应，其可以通过在邻近晶体管的导电沟道的多晶硅种子中注入杂质并将杂质从其扩散到导通通道中而使放置过程公差的同时提高了位置和几何形状的精度而放置。多晶硅种子还允许其中的多晶硅源极/漏极接触器的外延生长具有最小化其中的电流密度和路径长度的结构，同时提供进一步的机械优点。

25. 发明授权

US6124141A Non-destructive method and device for measuring the depth of a buried interface 失效
标题翻译：用于测量埋入界面深度的非破坏性方法和装置
公开(公告)号：US6124141A
公开(公告)日：2000-09-26
申请号：US4074
申请日：1998-01-07
申请人： K. Paul Muller , Venkatachalam C. Jaiprakash
发明人： K. Paul Muller , Venkatachalam C. Jaiprakash
IPC分类号： G01B11/02 , G01R31/265 , H01L21/334 , H01L21/66 , G01R31/26
CPC分类号： H01L29/66181 , G01R31/2656 , H01L22/12
摘要： The depth at which the top surface of a buried interface is located is non-destructively determined by FTIR.
摘要翻译：掩埋界面顶表面的深度由FTIR非破坏性决定。

26. 发明授权

US08909383B2 Proactive cooling of chips using workload information and controls 有权
标题翻译：使用工作负载信息和控制来主动冷却芯片
公开(公告)号：US08909383B2
公开(公告)日：2014-12-09
申请号：US13334903
申请日：2011-12-22
申请人： Scott J. Hadderman , Daniel J. Kearney , Wei Huang , K. Paul Muller , William J. Rooney , Guillermo J. Silva , Malcolm S. Ware , Emmanuel Yashchin , Peter B. Yocom
发明人： Scott J. Hadderman , Daniel J. Kearney , Wei Huang , K. Paul Muller , William J. Rooney , Guillermo J. Silva , Malcolm S. Ware , Emmanuel Yashchin , Peter B. Yocom
IPC分类号： G05D23/00 , G01K7/00 , H01L35/00 , H01L37/00 , H03K3/42 , H03K17/78
CPC分类号： G05D23/1919 , G06F1/206 , Y02D10/16
摘要： A method to reduce large temperature over/undershoot in a computer system. Using workload data, the method proactively modifies controls of mechanical cooling system to anticipate power and take appropriate actions to maintain temperature. Workload control modifies workload and scheduling to reduce power transients and subsequent temperature deviations. In addition, workload control allows more even distribution of temp across chips, allowing for even wear and reduction of small/ripple/noise temp oscillations. A system and program product for carrying out the method are also provided.
摘要翻译：一种减少计算机系统中温度过高/欠冲击的方法。使用工作负载数据，该方法主动修改机械冷却系统的控制以预测功率并采取适当的措施来保持温度。工作负载控制可以修改工作负载和调度，以减少电力瞬变和随后的温度偏差。此外，工作负载控制可以更均匀地分配芯片间的温度，从而可以均匀磨损和减少小/纹波/噪声温度振荡。还提供了一种用于执行该方法的系统和程序产品。

27. 发明申请

US20130166095A1 Proactive Cooling Of Chips Using Workload Information and Controls 有权
标题翻译：使用工作负载信息和控件主动冷却芯片
公开(公告)号：US20130166095A1
公开(公告)日：2013-06-27
申请号：US13334903
申请日：2011-12-22
申请人： Scott J. Hadderman , Daniel J. Kearney , Wei Huang , K. Paul Muller , William J. Rooney , Guillermo J. Silva , Malcolm S. Ware , Emmanuel Yashchin , Peter B. Yocom
发明人： Scott J. Hadderman , Daniel J. Kearney , Wei Huang , K. Paul Muller , William J. Rooney , Guillermo J. Silva , Malcolm S. Ware , Emmanuel Yashchin , Peter B. Yocom
IPC分类号： G05D23/19
CPC分类号： G05D23/1919 , G06F1/206 , Y02D10/16
摘要： A method to reduce large temperature over/undershoot in a computer system. Using workload data, the method proactively modifies controls of mechanical cooling system to anticipate power and take appropriate actions to maintain temperature. Workload control modifies workload and scheduling to reduce power transients and subsequent temperature deviations. In addition, workload control allows more even distribution of temp across chips, allowing for even wear and reduction of small/ripple/noise temp oscillations. A system and program product for carrying out the method are also provided.
摘要翻译：一种减少计算机系统中温度过高/欠冲击的方法。使用工作负载数据，该方法主动修改机械冷却系统的控制以预测功率并采取适当的措施来保持温度。工作负载控制可以修改工作负载和调度，以减少电力瞬变和随后的温度偏差。此外，工作负载控制可以更均匀地分配芯片间的温度，从而可以均匀磨损和减少小/纹波/噪声温度振荡。还提供了一种用于执行该方法的系统和程序产品。

28. 发明授权

US08102033B2 Reduced soft error rate through metal fill and placement 有权
标题翻译：通过金属填充和放置降低软错误率
公开(公告)号：US08102033B2
公开(公告)日：2012-01-24
申请号：US12473435
申请日：2009-05-28
申请人： K. Paul Muller , Alicia Wang
发明人： K. Paul Muller , Alicia Wang
IPC分类号： H01L23/556
CPC分类号： H01L23/556 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： A method for reducing single event upsets in an integrated circuit includes the step of providing a plurality of levels within the integrated circuit, wherein the plurality of levels within the integrated circuit are in a stacked arrangement. The method also includes the step of providing a plurality of metal fill patterns within each of the plurality of levels within the integrated circuit. The method further includes the step of placing the plurality of metal fill patterns within at least one of the plurality of levels in a pattern such that a line of sight towards an active silicon layer does not exist within the stacked arrangement of the plurality of levels, thereby increasingly absorbing ionizing radiation particles, and thereby reducing single event upsets in the integrated circuit.
摘要翻译：一种用于减少集成电路中的单事件扰乱的方法包括在集成电路内提供多个电平的步骤，其中集成电路内的多个电平处于堆叠布置。该方法还包括在集成电路内的多个电平的每一个内提供多个金属填充图案的步骤。该方法还包括将多个金属填充图案放置在多个层中的至少一个层中的图案的步骤，使得朝向有源硅层的视线不存在于多个层次的堆叠布置中，从而越来越多地吸收电离辐射颗粒，从而减少集成电路中的单个事件的不适。

29. 发明申请

US20110102042A1 APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES 有权
标题翻译：用于在SOI CMOS器件中硬化栅极的装置和方法
公开(公告)号：US20110102042A1
公开(公告)日：2011-05-05
申请号：US12987106
申请日：2011-01-08
申请人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
发明人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
IPC分类号： H03K3/00
CPC分类号： H03K3/356156 , H03K3/0375
摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.
摘要翻译：确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。该电路是锁存器，晶体管是SOI CMOS FET。晶体管也是SOI晶体管。串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

30. 发明授权

US07645650B2 Double gated transistor and method of fabrication 有权
标题翻译：双门控晶体管和制造方法
公开(公告)号：US07645650B2
公开(公告)日：2010-01-12
申请号：US11774663
申请日：2007-07-09
申请人： Andres Bryant , Meikei Ieong , K. Paul Muller , Edward J. Nowak , David M. Fried , Jed Rankin
发明人： Andres Bryant , Meikei Ieong , K. Paul Muller , Edward J. Nowak , David M. Fried , Jed Rankin
IPC分类号： H01L21/84
CPC分类号： H01L29/4908 , H01L21/823842 , H01L27/092 , H01L29/66795 , H01L29/785
摘要： A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The first and second body edges of the semiconductor substrate define a transistor body. A second gate structure of a second fermi level is provided adjacent the second body edge. A substantially uniform dopant concentration density is formed throughout the transistor body.
摘要翻译：一种形成晶体管的方法。提供半导体衬底。图案化半导体衬底以提供第一本体边缘。在第一身体边缘附近提供第一费米能级的第一门结构。图案化半导体衬底以提供第二本体边缘。半导体衬底的第一和第二主体边缘限定晶体管体。在第二身体边缘附近设置第二费米能级的第二门结构。在整个晶体管本体中形成基本均匀的掺杂剂浓度密度。

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