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1. 发明授权

US06960806B2 Double gated vertical transistor with different first and second gate materials 失效
标题翻译：双门控垂直晶体管，具有不同的第一和第二栅极材料
公开(公告)号：US06960806B2
公开(公告)日：2005-11-01
申请号：US09886823
申请日：2001-06-21
申请人： Andres Bryant , Meikei Ieong , K. Paul Muller , Edward J. Nowak , David M. Fried , Jed Rankin
发明人： Andres Bryant , Meikei Ieong , K. Paul Muller , Edward J. Nowak , David M. Fried , Jed Rankin
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/78 , H01L29/786 , H01L29/76
CPC分类号： H01L29/4908 , H01L21/823842 , H01L27/092 , H01L29/66795 , H01L29/785
摘要： Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and −0.5V for pFETs.
摘要翻译：因此，本发明提供一种双门控晶体管及其形成方法，其导致改进的器件性能和密度。本发明的优选实施例提供了具有不对称栅极掺杂的双门控晶体管，其中双栅极中的一个被简并掺杂为n型，另一个为简并p型。通过掺杂栅极n型和另一种p型，所得器件的阈值电压得到改善。特别地，通过不对称地掺杂两个栅极，所得到的晶体管可以通过适当掺杂的体，在允许低电压CMOS操作的范围内具有阈值电压。例如，可以产生对于nFET具有在0V和0.5V之间的阈值电压并且对于pFET而言在0和-0.5V之间的晶体管。

2. 发明授权

US07645650B2 Double gated transistor and method of fabrication 有权
标题翻译：双门控晶体管和制造方法
公开(公告)号：US07645650B2
公开(公告)日：2010-01-12
申请号：US11774663
申请日：2007-07-09
申请人： Andres Bryant , Meikei Ieong , K. Paul Muller , Edward J. Nowak , David M. Fried , Jed Rankin
发明人： Andres Bryant , Meikei Ieong , K. Paul Muller , Edward J. Nowak , David M. Fried , Jed Rankin
IPC分类号： H01L21/84
CPC分类号： H01L29/4908 , H01L21/823842 , H01L27/092 , H01L29/66795 , H01L29/785
摘要： A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The first and second body edges of the semiconductor substrate define a transistor body. A second gate structure of a second fermi level is provided adjacent the second body edge. A substantially uniform dopant concentration density is formed throughout the transistor body.
摘要翻译：一种形成晶体管的方法。提供半导体衬底。图案化半导体衬底以提供第一本体边缘。在第一身体边缘附近提供第一费米能级的第一门结构。图案化半导体衬底以提供第二本体边缘。半导体衬底的第一和第二主体边缘限定晶体管体。在第二身体边缘附近设置第二费米能级的第二门结构。在整个晶体管本体中形成基本均匀的掺杂剂浓度密度。

3. 发明授权

US07288445B2 Double gated transistor and method of fabrication 有权
标题翻译：双门控晶体管及其制造方法
公开(公告)号：US07288445B2
公开(公告)日：2007-10-30
申请号：US11125063
申请日：2005-05-09
申请人： Andres Bryant , Meikei Ieong , K. Paul Muller , Edward J. Nowak , David M. Fried , Jed Rankin
发明人： Andres Bryant , Meikei Ieong , K. Paul Muller , Edward J. Nowak , David M. Fried , Jed Rankin
IPC分类号： H01L21/84
CPC分类号： H01L29/4908 , H01L21/823842 , H01L27/092 , H01L29/66795 , H01L29/785
摘要： Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and −0.5V for pFETs.
摘要翻译：因此，本发明提供一种双门控晶体管及其形成方法，其导致改进的器件性能和密度。本发明的优选实施例提供了具有不对称栅极掺杂的双门控晶体管，其中双栅极中的一个被简并掺杂为n型，另一个为简并p型。通过掺杂栅极n型和另一种p型，所得器件的阈值电压得到改善。特别地，通过不对称地掺杂两个栅极，所得到的晶体管可以通过适当掺杂的体，在允许低电压CMOS操作的范围内具有阈值电压。例如，可以产生对于nFET具有在0V和0.5V之间的阈值电压并且对于pFET而言在0和-0.5V之间的晶体管。

4. 发明授权

US06967351B2 Finfet SRAM cell using low mobility plane for cell stability and method for forming 有权
标题翻译： Finfet SRAM单元使用低迁移率平面进行电池稳定性和形成方法
公开(公告)号：US06967351B2
公开(公告)日：2005-11-22
申请号：US10011351
申请日：2001-12-04
申请人： David M. Fried , Randy W. Mann , K. Paul Muller , Edward J. Nowak
发明人： David M. Fried , Randy W. Mann , K. Paul Muller , Edward J. Nowak
IPC分类号： H01L21/8244 , H01L21/84 , H01L27/12 , H01L29/04
CPC分类号： H01L27/11 , H01L21/84 , H01L27/1203 , H01L29/785 , Y10S257/903
摘要： The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The present invention forms relatively low gain FinFET transistors in a low carrier mobility plane and relatively high gain FinFET transistors in a high carrier mobility plane. Thus formed, the FinFETs formed in the high mobility plane have a relatively higher gain than the FinFETs formed in the low mobility plane. The embodiments are of particular application to the design and fabrication of a Static Random Access Memory (SRAM) cell. In this application, the bodies of the n-type FinFETs used as transfer devices are formed along the {110} plane. The bodies of the n-type FinFETs and p-type FinFETs used as the storage latch are formed along the {100}. Thus formed, the transfer devices will have a gain approximately half that of the n-type storage latch devices, facilitating proper SRAM operation.
摘要翻译：本发明提供了一种用于形成它的器件设计和方法，其导致Fin场效应晶体管具有不同的增益而不会不利地影响器件密度。本发明在低载流子迁移率平面中形成相对较低的增益FinFET晶体管，并在高载流子迁移率平面内形成相对较高的增益FinFET晶体管。如此形成的，在高迁移率平面中形成的FinFET具有比在低迁移率平面中形成的FinFET更高的增益。这些实施例特别适用于静态随机存取存储器（SRAM）单元的设计和制造。在这种应用中，用作转移装置的n型FinFET的主体沿{110}平面形成。用作存储锁存器的n型FinFET和p型FinFET的主体沿{100}形成。如此形成的，传送装置的增益大约是n型存储锁存装置的增益的一半，有利于适当的SRAM操作。

5. 发明授权

US07087477B2 FinFET SRAM cell using low mobility plane for cell stability and method for forming 失效
标题翻译： FinFET SRAM单元使用低迁移率平面进行电池稳定性和成型方法
公开(公告)号：US07087477B2
公开(公告)日：2006-08-08
申请号：US10987532
申请日：2004-11-12
申请人： David M. Fried , Randy W. Mann , K. Paul Muller , Edward J. Nowak
发明人： David M. Fried , Randy W. Mann , K. Paul Muller , Edward J. Nowak
IPC分类号： H01L21/8238
CPC分类号： H01L27/11 , H01L21/84 , H01L27/1203 , H01L29/785 , Y10S257/903
摘要： The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The present invention forms relatively low gain FinFET transistors in a low carrier mobility plane and relatively high gain FinFET transistors in a high carrier mobility plane. Thus formed, the FinFETs formed in the high mobility plane have a relatively higher gain than the FinFETs formed in the low mobility plane. The embodiments are of particular application to the design and fabrication of a Static Random Access Memory (SRAM) cell. In this application, the bodies of the n-type FinFETs used as transfer devices are formed along the {110} plane. The bodies of the n-type FinFETs and p-type FinFETs used as the storage latch are formed along the {100}. Thus formed, the transfer devices will have a gain approximately half that of the n-type storage latch devices, facilitating proper SRAM operation.
摘要翻译：本发明提供了一种用于形成它的器件设计和方法，其导致Fin场效应晶体管具有不同的增益而不会不利地影响器件密度。本发明在低载流子迁移率平面中形成相对较低的增益FinFET晶体管，并在高载流子迁移率平面内形成相对较高的增益FinFET晶体管。如此形成的，在高迁移率平面中形成的FinFET具有比在低迁移率平面中形成的FinFET更高的增益。这些实施例特别适用于静态随机存取存储器（SRAM）单元的设计和制造。在这种应用中，用作转移装置的n型FinFET的主体沿{110}平面形成。用作存储锁存器的n型FinFET和p型FinFET的主体沿{100}形成。如此形成的，传送装置的增益大约是n型存储锁存装置的增益的一半，有利于适当的SRAM操作。

6. 发明授权

US06913960B2 Fin-based double poly dynamic threshold CMOS FET with spacer gate and method of fabrication 失效
标题翻译：基于鳍的双重多晶硅动态阈值CMOS FET与间隔栅极和制造方法
公开(公告)号：US06913960B2
公开(公告)日：2005-07-05
申请号：US10843029
申请日：2004-05-11
申请人： Andres Bryant , K. Paul Muller , Edward J. Nowak
发明人： Andres Bryant , K. Paul Muller , Edward J. Nowak
IPC分类号： H01L21/28 , H01L21/336 , H01L21/84 , H01L27/12 , H01L29/423 , H01L29/78 , H01L29/786 , H01L21/8238
CPC分类号： H01L29/785 , H01L21/2815 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66795 , H01L29/783
摘要： The present invention provides a dynamic threshold (DT) CMOS FET and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a DT CMOS FET with a short, low resistance connection between the gate and the body and with low body-source/drain capacitance. The low body-source/drain capacitance is achieved using a thin, fin-type body. The low resistance connection between the gate and the body contact is achieved by having the gate and body contact aligned on opposite long sides of the fin with a bridge over the top of the narrow fin electrically connecting the gate and body.
摘要翻译：本发明提供一种动态阈值（DT）CMOS FET及其形成方法，其导致改进的器件性能和密度。本发明的优选实施例提供一种DT CMOS FET，其在栅极和主体之间具有短的低电阻连接，并且具有低的体源/漏极电容。低体积/漏极电容使用薄的翅片型体实现。栅极和体接触之间的低电阻连接是通过使栅极和主体接触在翅片的相对的长边上对准来实现的，桥与电极连接门和主体的窄鳍的顶部之间形成一个桥。

7. 发明授权

US06774437B2 Fin-based double poly dynamic threshold CMOS FET with spacer gate and method of fabrication 有权
标题翻译：基于鳍的双重多晶硅动态阈值CMOS FET与间隔栅极和制造方法
公开(公告)号：US06774437B2
公开(公告)日：2004-08-10
申请号：US09683486
申请日：2002-01-07
申请人： Andres Bryant , K. Paul Muller , Edward J. Nowak
发明人： Andres Bryant , K. Paul Muller , Edward J. Nowak
IPC分类号： H01L2704
CPC分类号： H01L29/785 , H01L21/2815 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66795 , H01L29/783
摘要： The present invention provides a dynamic threshold (DT) CMOS FET and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a DT CMOS FET with a short, low resistance connection between the gate and the body and with low body-to-source/drain capacitance. The low body-to-source/drain capacitance is achieved using a thin, fin-type body. The low resistance connection between the gate and the body contact is achieved by having the gate and body contact aligned on opposite long sides of the fin with a bridge over the top of the narrow fin electrically connecting the gate and body.
摘要翻译：本发明提供一种动态阈值（DT）CMOS FET及其形成方法，其导致改进的器件性能和密度。本发明的优选实施例提供了一种DT CMOS FET，其在栅极和主体之间具有短的低电阻连接，并且具有低的体/源极/漏极电容。使用薄的鳍式体实现了较低的体源对漏极电容。栅极和体接触之间的低电阻连接是通过使栅极和主体接触在翅片的相对的长边上对准来实现的，桥与电极连接门和主体的窄鳍的顶部之间形成桥。

8. 发明授权

US06657261B2 Ground-plane device with back oxide topography 有权
公开(公告)号：US06657261B2
公开(公告)日：2003-12-02
申请号：US09757317
申请日：2001-01-09
申请人： Fariborz Assaderaghi , Tze-chiang Chen , K. Paul Muller , Edward J. Nowak , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Fariborz Assaderaghi , Tze-chiang Chen , K. Paul Muller , Edward J. Nowak , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L29/78603
摘要： A ground-plane SOI device including at least a gate region that is formed on a top Si-containing layer of a SOI wafer, said top Si-containing layer being formed on a non-planar buried oxide layer, wherein said non-planar buried oxide layer has a thickness beneath the gate region that is thinner than corresponding oxide layers that are formed in regions not beneath said gate region as well as a method of fabricating the same are provided.

9. 发明授权

US06521949B2 SOI transistor with polysilicon seed 有权
标题翻译：具有多晶硅种子的SOI晶体管
公开(公告)号：US06521949B2
公开(公告)日：2003-02-18
申请号：US09848508
申请日：2001-05-03
申请人： Fariborz Assaderaghi , Tze-Chiang Chen , K. Paul Muller , Edward J. Nowak , Ghavam G. Shahidi
发明人： Fariborz Assaderaghi , Tze-Chiang Chen , K. Paul Muller , Edward J. Nowak , Ghavam G. Shahidi
IPC分类号： H01L2701
CPC分类号： H01L29/66757 , H01L29/66772 , H01L29/78618 , H01L29/78651 , H01L29/78675
摘要： Short channel effects are effectively suppressed by steep impurity concentration gradients which can be placed with improved accuracy of location and geometry while relaxing process tolerances by implanting impurities in a polysilicon seed adjacent a conduction channel of a transistor and diffusing impurities therefrom into the conduction channel. The polysilicon seed also allows the epitaxial growth of polysilicon source/drain contacts therefrom having a configuration which minimizes current density and path length therein while providing further mechanical advantages.
摘要翻译：通过陡峭的杂质浓度梯度有效地抑制了短沟道效应，其可以通过在邻近晶体管的导电沟道的多晶硅种子中注入杂质并将杂质从其扩散到导通通道中而使放置过程公差的同时提高了位置和几何形状的精度而放置。多晶硅种子还允许其中的多晶硅源极/漏极接触器的外延生长具有最小化其中的电流密度和路径长度的结构，同时提供进一步的机械优点。

10. 发明授权

US08513972B2 Soft error resilient FPGA 失效
公开(公告)号：US08513972B2
公开(公告)日：2013-08-20
申请号：US13352900
申请日：2012-01-18
申请人： Luiz C. Alves , William J. Clarke , K. Paul Muller , Robert B. Tremaine
发明人： Luiz C. Alves , William J. Clarke , K. Paul Muller , Robert B. Tremaine
IPC分类号： H03K19/003
CPC分类号： H03K19/00315 , H03K19/17764
摘要： A field programmable gate array (FPGA) includes configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having an SER resilience greater than an SER resilience of the non-hardened portion.

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