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1. 发明授权

US08909383B2 Proactive cooling of chips using workload information and controls 有权
标题翻译：使用工作负载信息和控制来主动冷却芯片
公开(公告)号：US08909383B2
公开(公告)日：2014-12-09
申请号：US13334903
申请日：2011-12-22
申请人： Scott J. Hadderman , Daniel J. Kearney , Wei Huang , K. Paul Muller , William J. Rooney , Guillermo J. Silva , Malcolm S. Ware , Emmanuel Yashchin , Peter B. Yocom
发明人： Scott J. Hadderman , Daniel J. Kearney , Wei Huang , K. Paul Muller , William J. Rooney , Guillermo J. Silva , Malcolm S. Ware , Emmanuel Yashchin , Peter B. Yocom
IPC分类号： G05D23/00 , G01K7/00 , H01L35/00 , H01L37/00 , H03K3/42 , H03K17/78
CPC分类号： G05D23/1919 , G06F1/206 , Y02D10/16
摘要： A method to reduce large temperature over/undershoot in a computer system. Using workload data, the method proactively modifies controls of mechanical cooling system to anticipate power and take appropriate actions to maintain temperature. Workload control modifies workload and scheduling to reduce power transients and subsequent temperature deviations. In addition, workload control allows more even distribution of temp across chips, allowing for even wear and reduction of small/ripple/noise temp oscillations. A system and program product for carrying out the method are also provided.
摘要翻译：一种减少计算机系统中温度过高/欠冲击的方法。使用工作负载数据，该方法主动修改机械冷却系统的控制以预测功率并采取适当的措施来保持温度。工作负载控制可以修改工作负载和调度，以减少电力瞬变和随后的温度偏差。此外，工作负载控制可以更均匀地分配芯片间的温度，从而可以均匀磨损和减少小/纹波/噪声温度振荡。还提供了一种用于执行该方法的系统和程序产品。

2. 发明申请

US20130166095A1 Proactive Cooling Of Chips Using Workload Information and Controls 有权
标题翻译：使用工作负载信息和控件主动冷却芯片
公开(公告)号：US20130166095A1
公开(公告)日：2013-06-27
申请号：US13334903
申请日：2011-12-22
申请人： Scott J. Hadderman , Daniel J. Kearney , Wei Huang , K. Paul Muller , William J. Rooney , Guillermo J. Silva , Malcolm S. Ware , Emmanuel Yashchin , Peter B. Yocom
发明人： Scott J. Hadderman , Daniel J. Kearney , Wei Huang , K. Paul Muller , William J. Rooney , Guillermo J. Silva , Malcolm S. Ware , Emmanuel Yashchin , Peter B. Yocom
IPC分类号： G05D23/19
CPC分类号： G05D23/1919 , G06F1/206 , Y02D10/16
摘要： A method to reduce large temperature over/undershoot in a computer system. Using workload data, the method proactively modifies controls of mechanical cooling system to anticipate power and take appropriate actions to maintain temperature. Workload control modifies workload and scheduling to reduce power transients and subsequent temperature deviations. In addition, workload control allows more even distribution of temp across chips, allowing for even wear and reduction of small/ripple/noise temp oscillations. A system and program product for carrying out the method are also provided.
摘要翻译：一种减少计算机系统中温度过高/欠冲击的方法。使用工作负载数据，该方法主动修改机械冷却系统的控制以预测功率并采取适当的措施来保持温度。工作负载控制可以修改工作负载和调度，以减少电力瞬变和随后的温度偏差。此外，工作负载控制可以更均匀地分配芯片间的温度，从而可以均匀磨损和减少小/纹波/噪声温度振荡。还提供了一种用于执行该方法的系统和程序产品。

3. 发明授权

US08102033B2 Reduced soft error rate through metal fill and placement 有权
标题翻译：通过金属填充和放置降低软错误率
公开(公告)号：US08102033B2
公开(公告)日：2012-01-24
申请号：US12473435
申请日：2009-05-28
申请人： K. Paul Muller , Alicia Wang
发明人： K. Paul Muller , Alicia Wang
IPC分类号： H01L23/556
CPC分类号： H01L23/556 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： A method for reducing single event upsets in an integrated circuit includes the step of providing a plurality of levels within the integrated circuit, wherein the plurality of levels within the integrated circuit are in a stacked arrangement. The method also includes the step of providing a plurality of metal fill patterns within each of the plurality of levels within the integrated circuit. The method further includes the step of placing the plurality of metal fill patterns within at least one of the plurality of levels in a pattern such that a line of sight towards an active silicon layer does not exist within the stacked arrangement of the plurality of levels, thereby increasingly absorbing ionizing radiation particles, and thereby reducing single event upsets in the integrated circuit.
摘要翻译：一种用于减少集成电路中的单事件扰乱的方法包括在集成电路内提供多个电平的步骤，其中集成电路内的多个电平处于堆叠布置。该方法还包括在集成电路内的多个电平的每一个内提供多个金属填充图案的步骤。该方法还包括将多个金属填充图案放置在多个层中的至少一个层中的图案的步骤，使得朝向有源硅层的视线不存在于多个层次的堆叠布置中，从而越来越多地吸收电离辐射颗粒，从而减少集成电路中的单个事件的不适。

4. 发明申请

US20110102042A1 APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES 有权
标题翻译：用于在SOI CMOS器件中硬化栅极的装置和方法
公开(公告)号：US20110102042A1
公开(公告)日：2011-05-05
申请号：US12987106
申请日：2011-01-08
申请人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
发明人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
IPC分类号： H03K3/00
CPC分类号： H03K3/356156 , H03K3/0375
摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.
摘要翻译：确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。该电路是锁存器，晶体管是SOI CMOS FET。晶体管也是SOI晶体管。串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

5. 发明授权

US07645650B2 Double gated transistor and method of fabrication 有权
标题翻译：双门控晶体管和制造方法
公开(公告)号：US07645650B2
公开(公告)日：2010-01-12
申请号：US11774663
申请日：2007-07-09
申请人： Andres Bryant , Meikei Ieong , K. Paul Muller , Edward J. Nowak , David M. Fried , Jed Rankin
发明人： Andres Bryant , Meikei Ieong , K. Paul Muller , Edward J. Nowak , David M. Fried , Jed Rankin
IPC分类号： H01L21/84
CPC分类号： H01L29/4908 , H01L21/823842 , H01L27/092 , H01L29/66795 , H01L29/785
摘要： A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The first and second body edges of the semiconductor substrate define a transistor body. A second gate structure of a second fermi level is provided adjacent the second body edge. A substantially uniform dopant concentration density is formed throughout the transistor body.
摘要翻译：一种形成晶体管的方法。提供半导体衬底。图案化半导体衬底以提供第一本体边缘。在第一身体边缘附近提供第一费米能级的第一门结构。图案化半导体衬底以提供第二本体边缘。半导体衬底的第一和第二主体边缘限定晶体管体。在第二身体边缘附近设置第二费米能级的第二门结构。在整个晶体管本体中形成基本均匀的掺杂剂浓度密度。

6. 发明申请

US20090134925A1 APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES 有权
标题翻译：用于在SOI CMOS器件中硬化栅极的装置和方法
公开(公告)号：US20090134925A1
公开(公告)日：2009-05-28
申请号：US11857596
申请日：2007-09-19
申请人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
发明人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
IPC分类号： H03K3/356 , H03K3/00
CPC分类号： H03K3/356156 , H03K3/0375
摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.
摘要翻译：确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。该电路是锁存器，晶体管是SOI CMOS FET。晶体管也是SOI晶体管。串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

7. 发明授权

US07491598B2 CMOS circuits including a passive element having a low end resistance 有权
标题翻译： CMOS电路包括具有低端电阻的无源元件
公开(公告)号：US07491598B2
公开(公告)日：2009-02-17
申请号：US11956993
申请日：2007-12-14
申请人： Christopher D. Sheraw , Alyssa C. Bonnoit , K. Paul Muller , Werner Rausch
发明人： Christopher D. Sheraw , Alyssa C. Bonnoit , K. Paul Muller , Werner Rausch
IPC分类号： H01L21/8238
CPC分类号： H01L27/0629 , H01L21/26506 , H01L28/20 , H01L28/40 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits, as well as methods for forming such CMOS circuits. More specifically, the present invention relates to CMOS circuits that contain passive elements, such as buried resistors, capacitors, diodes, inductors, attenuators, power dividers, and antennas, etc., which are characterized by an end contact resistance of less than 90 ohm-microns. Such a low end resistance can be achieved either by reducing the spacer widths of the passive elements to a range of from about 10 nm to about 30 nm, or by masking the passive elements during a pre-amorphization implantation step, so that the passive elements are essentially free of pre-amorphization implants.
摘要翻译：本发明涉及互补金属氧化物半导体（CMOS）电路以及用于形成这种CMOS电路的方法。更具体地说，本发明涉及包含诸如埋地电阻器，电容器，二极管，电感器，衰减器，功率分配器和天线等无源元件的CMOS电路，其特征在于端接触电阻小于90欧姆微量元素这样的低端电阻可以通过将无源元件的间隔物宽度减小到约10nm至约30nm的范围，或通过在预非晶化注入步骤期间掩蔽无源元件来实现，使得无源元件基本上没有前非晶化植入物。

8. 发明申请

US20080303070A1 PREVENTING CAVITATION IN HIGH ASPECT RATIO DIELECTRIC REGIONS OF SEMICONDUCTOR DEVICE 失效
标题翻译：在半导体器件的高比例电介质区域中防止蚀刻
公开(公告)号：US20080303070A1
公开(公告)日：2008-12-11
申请号：US12190777
申请日：2008-08-13
申请人： Paul D. Agnello , Rajeev Malik , K. Paul Muller
发明人： Paul D. Agnello , Rajeev Malik , K. Paul Muller
IPC分类号： H01L29/00
CPC分类号： H01L21/76832 , H01L21/76834 , H01L21/76837 , H01L21/823425 , H01L21/823468 , H01L21/823475
摘要： Methods for preventing cavitation in high aspect ratio dielectric regions in a semiconductor device, and the device so formed, are disclosed. The invention includes depositing a first dielectric in the high aspect ratio dielectric region between a pair of structures, and then removing the first dielectric to form a bearing surface adjacent each structure. The bearing surface prevents cavitation of the interlayer dielectric that subsequently fills the high aspect ratio region.
摘要翻译：公开了用于防止在半导体器件中的高纵横比介电区域中的空化的方法以及如此形成的器件。本发明包括在一对结构之间的高纵横比电介质区域中沉积第一电介质，然后移除第一电介质以形成邻近每个结构的支承表面。轴承表面防止随后填充高纵横比区域的层间电介质的空化。

9. 发明授权

US07459384B2 Preventing cavitation in high aspect ratio dielectric regions of semiconductor device 失效
标题翻译：防止半导体器件的高长宽比介电区域产生气蚀
公开(公告)号：US07459384B2
公开(公告)日：2008-12-02
申请号：US10710227
申请日：2004-06-28
申请人： Paul D. Agnello , Rajeev Malik , K. Paul Muller
发明人： Paul D. Agnello , Rajeev Malik , K. Paul Muller
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： H01L21/76832 , H01L21/76834 , H01L21/76837 , H01L21/823425 , H01L21/823468 , H01L21/823475
摘要： Methods for preventing cavitation in high aspect ratio dielectric regions in a semiconductor device, and the device so formed, are disclosed. The invention includes depositing a first dielectric in the high aspect ratio dielectric region between a pair of structures, and then removing the first dielectric to form a bearing surface adjacent each structure. The bearing surface prevents cavitation of the interlayer dielectric that subsequently fills the high aspect ratio region.
摘要翻译：公开了用于防止在半导体器件中的高纵横比介电区域中的空化的方法以及如此形成的器件。本发明包括在一对结构之间的高纵横比电介质区域中沉积第一电介质，然后移除第一电介质以形成邻近每个结构的支承表面。轴承表面防止随后填充高纵横比区域的层间电介质的空化。

10. 发明授权

US07288445B2 Double gated transistor and method of fabrication 有权
标题翻译：双门控晶体管及其制造方法
公开(公告)号：US07288445B2
公开(公告)日：2007-10-30
申请号：US11125063
申请日：2005-05-09
申请人： Andres Bryant , Meikei Ieong , K. Paul Muller , Edward J. Nowak , David M. Fried , Jed Rankin
发明人： Andres Bryant , Meikei Ieong , K. Paul Muller , Edward J. Nowak , David M. Fried , Jed Rankin
IPC分类号： H01L21/84
CPC分类号： H01L29/4908 , H01L21/823842 , H01L27/092 , H01L29/66795 , H01L29/785
摘要： Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and −0.5V for pFETs.
摘要翻译：因此，本发明提供一种双门控晶体管及其形成方法，其导致改进的器件性能和密度。本发明的优选实施例提供了具有不对称栅极掺杂的双门控晶体管，其中双栅极中的一个被简并掺杂为n型，另一个为简并p型。通过掺杂栅极n型和另一种p型，所得器件的阈值电压得到改善。特别地，通过不对称地掺杂两个栅极，所得到的晶体管可以通过适当掺杂的体，在允许低电压CMOS操作的范围内具有阈值电压。例如，可以产生对于nFET具有在0V和0.5V之间的阈值电压并且对于pFET而言在0和-0.5V之间的晶体管。

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