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1. 发明授权

US6094397A Method and apparatus for addressing multi-bank memory 失效
标题翻译：用于寻址多组存储器的方法和装置
公开(公告)号：US6094397A
公开(公告)日：2000-07-25
申请号：US246465
申请日：1999-02-09
申请人： Scott J. Hadderman , Daniel J. Kolor
发明人： Scott J. Hadderman , Daniel J. Kolor
IPC分类号： G11C8/12 , G11C8/00
CPC分类号： G11C8/12
摘要： A method and apparatus for addressing multi-bank memory. The method includes generating a first bank select and generating a first row address. The first row address is stored and presented as a second bank select during an activate portion of the memory cycle. During an access portion of the memory cycle, a first bank select is generated and the saved second bank select is retrieved from storage. The first bank select and retrieved second bank select identify a bank of memory. The apparatus includes a storage device for saving the second bank select. The second bank select may be stored based on the value of the first bank select.
摘要翻译：一种寻址多组存储器的方法和装置。该方法包括产生第一组选择并生成第一行地址。在存储器周期的激活部分期间，第一行地址被存储并呈现为第二存储体选择。在存储器周期的访问部分期间，产生第一存储区选择，并且从存储器检索保存的第二存储体选择。第一个银行选择和检索第二个银行选择识别一个记忆库。该装置包括用于保存第二存储体选择的存储装置。可以基于第一组选择的值来存储第二组选择。

2. 发明授权

US08909383B2 Proactive cooling of chips using workload information and controls 有权
标题翻译：使用工作负载信息和控制来主动冷却芯片
公开(公告)号：US08909383B2
公开(公告)日：2014-12-09
申请号：US13334903
申请日：2011-12-22
申请人： Scott J. Hadderman , Daniel J. Kearney , Wei Huang , K. Paul Muller , William J. Rooney , Guillermo J. Silva , Malcolm S. Ware , Emmanuel Yashchin , Peter B. Yocom
发明人： Scott J. Hadderman , Daniel J. Kearney , Wei Huang , K. Paul Muller , William J. Rooney , Guillermo J. Silva , Malcolm S. Ware , Emmanuel Yashchin , Peter B. Yocom
IPC分类号： G05D23/00 , G01K7/00 , H01L35/00 , H01L37/00 , H03K3/42 , H03K17/78
CPC分类号： G05D23/1919 , G06F1/206 , Y02D10/16
摘要： A method to reduce large temperature over/undershoot in a computer system. Using workload data, the method proactively modifies controls of mechanical cooling system to anticipate power and take appropriate actions to maintain temperature. Workload control modifies workload and scheduling to reduce power transients and subsequent temperature deviations. In addition, workload control allows more even distribution of temp across chips, allowing for even wear and reduction of small/ripple/noise temp oscillations. A system and program product for carrying out the method are also provided.
摘要翻译：一种减少计算机系统中温度过高/欠冲击的方法。使用工作负载数据，该方法主动修改机械冷却系统的控制以预测功率并采取适当的措施来保持温度。工作负载控制可以修改工作负载和调度，以减少电力瞬变和随后的温度偏差。此外，工作负载控制可以更均匀地分配芯片间的温度，从而可以均匀磨损和减少小/纹波/噪声温度振荡。还提供了一种用于执行该方法的系统和程序产品。

3. 发明申请

US20130166095A1 Proactive Cooling Of Chips Using Workload Information and Controls 有权
标题翻译：使用工作负载信息和控件主动冷却芯片
公开(公告)号：US20130166095A1
公开(公告)日：2013-06-27
申请号：US13334903
申请日：2011-12-22
申请人： Scott J. Hadderman , Daniel J. Kearney , Wei Huang , K. Paul Muller , William J. Rooney , Guillermo J. Silva , Malcolm S. Ware , Emmanuel Yashchin , Peter B. Yocom
发明人： Scott J. Hadderman , Daniel J. Kearney , Wei Huang , K. Paul Muller , William J. Rooney , Guillermo J. Silva , Malcolm S. Ware , Emmanuel Yashchin , Peter B. Yocom
IPC分类号： G05D23/19
CPC分类号： G05D23/1919 , G06F1/206 , Y02D10/16
摘要： A method to reduce large temperature over/undershoot in a computer system. Using workload data, the method proactively modifies controls of mechanical cooling system to anticipate power and take appropriate actions to maintain temperature. Workload control modifies workload and scheduling to reduce power transients and subsequent temperature deviations. In addition, workload control allows more even distribution of temp across chips, allowing for even wear and reduction of small/ripple/noise temp oscillations. A system and program product for carrying out the method are also provided.
摘要翻译：一种减少计算机系统中温度过高/欠冲击的方法。使用工作负载数据，该方法主动修改机械冷却系统的控制以预测功率并采取适当的措施来保持温度。工作负载控制可以修改工作负载和调度，以减少电力瞬变和随后的温度偏差。此外，工作负载控制可以更均匀地分配芯片间的温度，从而可以均匀磨损和减少小/纹波/噪声温度振荡。还提供了一种用于执行该方法的系统和程序产品。

4. 发明授权

US06499071B1 Interconnection system 失效
标题翻译：互连系统
公开(公告)号：US06499071B1
公开(公告)日：2002-12-24
申请号：US09353244
申请日：1999-07-14
申请人： Scott J. Hadderman , William F. Relyea
发明人： Scott J. Hadderman , William F. Relyea
IPC分类号： G06F1300
CPC分类号： G06F13/4081
摘要： An exemplary embodiment of the invention is an interconnection system including a primary connector having a first detection contact coupled to a first voltage, a second detection contact coupled to said first voltage and a reference contact coupled to a second voltage. The interconnection system includes a secondary connector having a first contact, a second contact and a secondary reference contact. The second contact and secondary reference contact are electrically connected. The first contact makes electrical connection with the first detection contact, the second contact makes electrical connection with the second detection contact and the secondary reference contact makes electrical connection with the reference contact. When the second detection contact makes electrical connection with the second contact, the second detection contact is connected to the second voltage.
摘要翻译：本发明的示例性实施例是一种互连系统，其包括主连接器，其具有耦合到第一电压的第一检测触点，耦合到所述第一电压的第二检测触点和耦合到第二电压的参考触点。互连系统包括具有第一触点，第二触点和次参考触点的次级连接器。第二触点和次参考触点电连接。第一触点与第一检测触点进行电连接，第二触点与第二检测触点进行电连接，次参考触点与参考触点进行电连接。当第二检测触点与第二触点进行电连接时，第二检测触点连接到第二电压。

5. 发明授权

US06239714B1 Controller for use in an interconnection system 失效
标题翻译：用于互连系统的控制器
公开(公告)号：US06239714B1
公开(公告)日：2001-05-29
申请号：US09353209
申请日：1999-07-14
申请人： Scott J. Hadderman , William F. Relyea
发明人： Scott J. Hadderman , William F. Relyea
IPC分类号： G08B2100
CPC分类号： G06F11/2289
摘要： An exemplary embodiment of the invention is a controller for use in an interconnection system having a primary connector and a variable number of secondary connectors. The primary connector includes a first detection contact and a second detection contact. The controller includes a first detection port connected to the first detection contact and a second detection port connected to the second detection contact. The controller also includes a processor for monitoring a first signal at the first detection port and a second signal at the second detection port and determining a number of secondary connectors in response to the first signal and the second signal.
摘要翻译：本发明的示例性实施例是用于具有主连接器和可变数量的次连接器的互连系统中的控制器。主连接器包括第一检测触点和第二检测触点。控制器包括连接到第一检测触点的第一检测端口和连接到第二检测触点的第二检测端口。控制器还包括处理器，用于监测第一检测端口处的第一信号和第二检测端口处的第二信号，并响应于第一信号和第二信号确定多个辅助连接器。

6. 发明授权

US06618942B2 Method for insertion of inserting printed circuit card into socket connectors 失效
标题翻译：将印刷电路卡插入插座连接器的方法
公开(公告)号：US06618942B2
公开(公告)日：2003-09-16
申请号：US09970618
申请日：2001-10-04
申请人： Brian S. Beaman , Scott J. Hadderman , Richard D. Wheeler
发明人： Brian S. Beaman , Scott J. Hadderman , Richard D. Wheeler
IPC分类号： H05K1300
CPC分类号： H01R12/88 , H01R12/721 , Y10T29/49139 , Y10T29/49169 , Y10T29/49217
摘要： A method for insertion of inserting printed circuit card into socket connectors which prevents sockets from getting contaminated or damaged during the insertion of a printed circuit card comprises the steps of: inserting a cam for moving a socket connector's contacts outwardly so that they will not make contact with a card's edge when it is inserted between the contacts of the sockets connector as it is inserted, and after the printed circuit card is inserted the printed circuit card moving the printed circuit card until it makes contact with a stop in the socket connector, and after the printed circuit card has contacted the stop in the socket connector, moving the cam to a closed position allowing the printed circuit card to be seated, and seating the printed circuit card by moving it to cause and allow for an amount of wipe to clean the connector's contacts without contaminating or damaging the socket connector's contacts during the insertion of said printed circuit card.
摘要翻译：将插入印刷电路卡插入到插座连接器中以防止在插入印刷电路卡期间插座受到污染或损坏的插入方法包括以下步骤：插入用于向外移动插座连接器触头的凸轮，使得它们不会接触当插入插座连接器的触点之间时插入卡的边缘，并且在印刷电路卡插入印刷电路卡之后移动印刷电路卡直到其与插座连接器中的止动件接触，并且在印刷电路卡已经与插座连接器中的停止点接触之后，将凸轮移动到关闭位置，允许印刷电路卡就座，并且通过移动印刷电路卡来安置印刷电路板，并允许擦拭量清洁连接器的触点在插入所述印刷电路卡期间不会污染或损坏插座连接器的触头。

7. 发明授权

US06470417B1 Emulation of next generation DRAM technology 失效
标题翻译：仿真下一代DRAM技术
公开(公告)号：US06470417B1
公开(公告)日：2002-10-22
申请号：US09592525
申请日：2000-06-12
申请人： Daniel J. Kolor , Scott J. Hadderman
发明人： Daniel J. Kolor , Scott J. Hadderman
IPC分类号： G06F1202
CPC分类号： G06F12/06
摘要： A current generation, quad RAS, single CAS, stacked component (101) including four 4 Mb×4 bits 11/11 DRAMs (210-213) is arranged to emulate a next generation 16 Mb×4 bits 12/12 DRAM. The (24) bit address signal provided by memory controller (105) includes a row address of 12 bits and a column address of 12 bits. Each DRAM (210-213) within the current generation DRAM component (101) requires only 11 row address bits and 11 column address bits. The additional 1 row address bit and 1 column address bit are provided to decoder logic (103). The additional row address bit is decoded by the decoding logic (103) to direct the RAS signals over two of the four RAS lines (201-204), thereby activating the two signaled DRAMs. The additional column address bit is then decoded by decoding logic (103) to de-activate one of the two signaled DRAMs , leaving only one DRAM activated. CAS line (205) directs the CAS signal to all of the stacked DRAMs (210-213). The combination of both RAS and CAS is provided to only one of the plurality of current generation DRAMs, thereby permitting access to that particular current generation DRAM.
摘要翻译：布置包括四个4Mbx4位11/11 DRAM（210-213）的当前一代，四RAS，单个CAS，堆叠组件（101），以模拟下一代16Mbx4位12/12 DRAM。由存储器控制器（105）提供的（24）位地址信号包括12位的行地址和12位的列地址。当前一代DRAM组件（101）内的每个DRAM（210-213）只需要11行地址位和11列地址位。附加的1行地址位和1列地址位被提供给解码器逻辑（103）。解码逻辑（103）对附加的行地址位进行解码，以将RAS信号引导到四条RAS线（201-204）中的两条线上，由此激活两个信号的DRAM。附加列地址位然后由解码逻辑（103）解码以去激活两个信号化的DRAM中的一个，仅留下一个DRAM被激活。 CAS线（205）将CAS信号引导到所有堆叠的DRAM（210-213）。 RAS和CAS的组合仅提供给多个当前一代DRAM中的一个，从而允许访问该特定的当前一代DRAM。

8. 发明授权

US5615328A PCMCIA SRAM card function using DRAM technology 失效
标题翻译： PCMCIA SRAM卡功能采用DRAM技术
公开(公告)号：US5615328A
公开(公告)日：1997-03-25
申请号：US521509
申请日：1995-08-30
申请人： Scott J. Hadderman , Kraig R. White
发明人： Scott J. Hadderman , Kraig R. White
IPC分类号： G06F13/16 , G01R31/28 , G06F11/00
CPC分类号： G06F13/1694
摘要： An apparatus may be used with a computer system having a PCMCIA interface. The apparatus employs a DRAM device and logic for converting the PCMCIA SRAM control signals into DRAM control signals, so as to permit the communication of data and control signals between the computer system and the DRAM device. The apparatus further provides controls for refreshing the DRAM device, and for arbitrating between the functions of refreshing the DRAM and providing for communication between the DRAM and the computer system. The apparatus further provides the power management functions required for operating a DRAM device in a PCMCIA environment.
摘要翻译：一种装置可以与具有PCMCIA接口的计算机系统一起使用。该装置采用用于将PCMCIA SRAM控制信号转换成DRAM控制信号的DRAM装置和逻辑，以便允许计算机系统和DRAM装置之间的数据和控制信号的通信。该装置还提供用于刷新DRAM设备的控制，以及用于在刷新DRAM并提供DRAM与计算机系统之间的通信的功能之间进行仲裁。该装置还提供在PCMCIA环境中操作DRAM设备所需的电源管理功能。

9. 发明授权

US5566121A Method for PCMCIA card function using DRAM technology 失效
标题翻译：使用DRAM技术的PCMCIA卡功能的方法
公开(公告)号：US5566121A
公开(公告)日：1996-10-15
申请号：US521508
申请日：1995-08-30
申请人： Scott J. Hadderman , Kraig R. White
发明人： Scott J. Hadderman , Kraig R. White
IPC分类号： G11C11/406 , G11C11/4074 , G11C13/00
CPC分类号： G11C11/4074 , G11C11/406
摘要： A method for operating an apparatus including a DRAM with a computer system having a PCMCIA interface. The method includes the steps of converting the PCMCIA SRAM control signals sent by the computer system across the PCMCIA interface into DRAM control signals, so as to permit the communication of data and control signals between the computer system and the DRAM device. The method further includes refreshing the DRAM device and arbitrating between the refreshing of the DRAM and providing for communication between the DRAM and the computer system. The method further teaches providing power management functions required for operating a DRAM device in a PCMCIA environment.
摘要翻译：一种用于操作包括具有PCMCIA接口的计算机系统的DRAM的设备的方法。该方法包括以下步骤：将由PCMCIA接口的计算机系统发送的PCMCIA SRAM控制信号转换成DRAM控制信号，以便允许计算机系统和DRAM设备之间的数据和控制信号的通信。该方法还包括刷新DRAM设备并在DRAM的刷新之间进行仲裁并提供DRAM与计算机系统之间的通信。该方法进一步教导了提供在PCMCIA环境中操作DRAM设备所需的电源管理功能。

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