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21. 发明授权

US08197522B2 Pedicle screw and operating device thereof 有权
标题翻译：椎弓根螺钉及其操作装置
公开(公告)号：US08197522B2
公开(公告)日：2012-06-12
申请号：US12061326
申请日：2008-04-02
申请人： Keun Ho Park , Jong Myeon Choi , Hoon Lee
发明人： Keun Ho Park , Jong Myeon Choi , Hoon Lee
IPC分类号： A61B17/88
CPC分类号： A61B17/7032 , A61B17/7089 , A61B17/864
摘要： Disclosed is a spine fixation apparatus, more particularly, a pedicle screw implanted into a spine and an operating device for the pedicle screw capable of easily inserting a rod to a head 5 section of the pedicle screw in order to securely fix the spine. The pedicle screw has a head section including a recess part defined by first and second sidewalls, a screw section, and a support unit formed at an upper portion of the recess part of the head section while connecting the first sidewall to the second sidewall.
摘要翻译：公开了一种脊柱固定装置，更具体地，植入脊柱的椎弓根螺钉和用于能够容易地将杆插入椎弓根螺钉的头部5的椎弓根螺钉的操作装置，以便可靠地固定脊柱。椎弓根螺钉具有头部，头部包括由第一和第二侧壁限定的凹部，螺钉部和形成在头部的凹部的上部的支撑单元，同时将第一侧壁连接到第二侧壁。

22. 发明申请

US20110292708A1 3D SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20110292708A1
公开(公告)日：2011-12-01
申请号：US13115501
申请日：2011-05-25
申请人： Uk-song Kang , Dong-hyeon Jang , Seong-jin Jang , Hoon Lee , Jin-ho Kim , Nam-seog Kim , Byung-sik Moon , Woo-dong Lee
发明人： Uk-song Kang , Dong-hyeon Jang , Seong-jin Jang , Hoon Lee , Jin-ho Kim , Nam-seog Kim , Byung-sik Moon , Woo-dong Lee
IPC分类号： G11C5/06 , H01L21/66 , H01L21/50 , G11C8/18 , H01L23/48
CPC分类号： H01L23/481 , G11C5/06 , G11C8/18 , H01L22/32 , H01L24/05 , H01L24/16 , H01L24/17 , H01L24/73 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/05572 , H01L2224/16145 , H01L2224/16146 , H01L2224/17051 , H01L2224/17515 , H01L2224/73204 , H01L2224/94 , H01L2225/06513 , H01L2225/06544 , H01L2225/06596 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01047 , H01L2924/01055 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2224/05552 , H01L2924/00
摘要： A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.
摘要翻译：三维（3D）半导体器件可以包括一堆芯片，包括主芯片和一个或多个从芯片。从芯片的I / O连接不需要连接到主板上的通道，只有主芯片的电极焊盘可以连接到通道。只有主芯片可以为通道提供负载。可以在堆叠相同类型的半导体芯片的半导体器件的数据输入路径，数据输出路径，地址/命令路径和/或时钟路径上设置贯穿衬底通孔（TSV）边界。

23. 发明申请

US20100154450A1 Air Conditioning System Using Dehumidifying Cooling Device 有权
标题翻译：空调系统采用除湿冷却装置
公开(公告)号：US20100154450A1
公开(公告)日：2010-06-24
申请号：US11990283
申请日：2007-03-08
申请人： Seok-Mann Yoon , Dae-Young Lee , Hoon Lee , Chang-Ku Kang , Sung-Ook Jeong
发明人： Seok-Mann Yoon , Dae-Young Lee , Hoon Lee , Chang-Ku Kang , Sung-Ook Jeong
IPC分类号： F25B27/00 , F25B41/00
CPC分类号： F24F3/14 , F24F2003/1446 , Y02E20/14
摘要： An air conditioning system using for a dehumidifying cooling device has developed that comprising a heating source for producing hot water, a heat exchanger for transferring heat from the hot water to circulating water, a circulation pump for circulating the resulting hot water heated in the heat exchanger, a heating pipeline connected to the circulation pump for conveying the hot water to a heat supply target area, a user heat exchanger connected to the heating pipeline for conveying hot water to the heat supply target area, a dehumidifying cooling device connected to a hot water pipe of users heat exchanger and installed in each household within the heat supply target area, the dehumidifying cooling device removing moisture from the air by using hot water supplied from the hot water pipe to deal with latent heat load and to lower the temperature of the dehumidified air via evaporation of water contained in the air.
摘要翻译：已经开发了一种用于除湿冷却装置的空调系统，其包括用于产生热水的加热源，用于将热量从热水转移到循环水的热交换器，用于使得在热交换器中加热的所得热水循环的循环泵连接到循环泵的加热管道，用于将热水输送到供热目标区域;连接到加热管道的用户热交换器，用于将热水输送到供热目标区域;连接到热水的除湿冷却装置用户热交换器管道，并安装在供热目标区域内的每个家庭中，除湿冷却装置通过使用从热水管供应的热水来去除空气中的水分，以处理潜热负荷并降低除湿温度空气通过空气中包含的水蒸发。

24. 发明申请

US20100020583A1 Stacked memory module and system 有权
标题翻译：堆叠内存模块和系统
公开(公告)号：US20100020583A1
公开(公告)日：2010-01-28
申请号：US12454064
申请日：2009-05-12
申请人： Uk-Song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
发明人： Uk-Song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
IPC分类号： G11C5/02 , G11C5/06
CPC分类号： G11C5/02 , G11C5/025 , G11C5/04 , G11C8/12 , G11C8/18 , G11C29/14 , H01L23/481 , H01L25/0657 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/05099
摘要： A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.
摘要翻译：三维存储器模块和系统形成有在主芯片上堆叠的至少一个从芯片。通过半导体通孔（TSV）通过主芯片和从芯片中的至少一个形成。主芯片包括用于增加存储器模块/系统容量的存储器核心。此外，公开了形成有效布线的三维存储器模块/系统的容量组织，用于形成三维存储器模块/系统的多个存储器组，多个存储体组和/或多个等级。

25. 发明授权

US07612617B2 Voltage-controlled oscillator gain calibration for two-point modulation in a phase-locked loop 有权
标题翻译：在锁相环中进行两点调制的压控振荡器增益校准
公开(公告)号：US07612617B2
公开(公告)日：2009-11-03
申请号：US12040875
申请日：2008-03-01
申请人： Rajasekhar Pullela , Morten Damgaard , Shahrzad Tadjpour , John E. Vasa , Hoon Lee
发明人： Rajasekhar Pullela , Morten Damgaard , Shahrzad Tadjpour , John E. Vasa , Hoon Lee
IPC分类号： H03L7/099 , H03L7/18
CPC分类号： H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0991
摘要： A phase-locked loop (PLL) is arranged to receive high-pass data at a first input and low-pass data at a second input. A first digital input is coupled to a primary path through a digital-to-analog converter (DAC) and a second digital input is coupled to a feedback path of the PLL. The controller provides the first input and the second input during a calibration procedure. The controller adjusts first and second control inputs in an attempt to keep the input voltage to a voltage-controlled oscillator (VCO) in the PLL constant while determining the gain of the VCO in Hz/LSB.
摘要翻译：锁相环（PLL）被布置成在第一输入处接收高通数据并在第二输入端接收低通数据。第一数字输入通过数模转换器（DAC）耦合到主路径，并且第二数字输入耦合到PLL的反馈路径。控制器在校准过程中提供第一个输入和第二个输入。控制器调整第一和第二控制输入，试图将输入电压保持为PLL中的压控振荡器（VCO），同时以Hz / LSB确定VCO的增益。

26. 发明授权

US07581155B2 Apparatus for FEC supporting transmission of variable-length frames in TDMA system and method of using the same 失效
标题翻译：用于支持TDMA系统中可变长度帧的传输的FEC的装置及其使用方法
公开(公告)号：US07581155B2
公开(公告)日：2009-08-25
申请号：US11004401
申请日：2004-12-03
申请人： Hoon Lee , Tae Whan Yoo , Hyeong Ho Lee
发明人： Hoon Lee , Tae Whan Yoo , Hyeong Ho Lee
IPC分类号： H03M13/00
CPC分类号： H03M13/251 , H03M13/1515 , H03M13/25 , H04L1/0041 , H04L1/0057 , H04L1/0084
摘要： An apparatus for transmitting a FEC frame is provided. In order to correct an error caused by a transmission medium using FEC in a Reed-Solomon code type, FEC encoding/decoding of a frame is performed. A total transmission delay time is not influenced when FEC is bypassed, a delay caused by a shortened codeword is minimized, and a FEC encoding/decoding delays for frames having different lengths are equalized.
摘要翻译：提供了一种用于发送FEC帧的装置。为了校正利用Reed-Solomon码类型的使用FEC的传输介质引起的错误，执行帧的FEC编码/解码。当FEC被旁路时，总传输延迟时间不受影响，由缩短的码字引起的延迟最小化，并且对具有不同长度的帧进行FEC编码/解码延迟相等。

27. 发明申请

US20090115473A1 LOOP FILTER, PHASE-LOCKED LOOP, AND METHOD OF OPERATING THE LOOP FILTER 有权
标题翻译：环路滤波器，相位锁定环路和操作环路滤波器的方法
公开(公告)号：US20090115473A1
公开(公告)日：2009-05-07
申请号：US12267116
申请日：2008-11-07
申请人： Young-don Choi , Hoon Lee
发明人： Young-don Choi , Hoon Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0893 , H03L7/0891 , H03L7/093
摘要： A loop filter capable of controlling a charge sharing point in time, a phase locked loop, and a method of operating the loop filter are provided. The loop filter includes a duty control unit and a variable capacitor unit. The duty control unit generates a duty control clock signal of which an activation section is shorter than an inactivation section, by controlling a duty of an input clock signal. The variable capacitor unit is charged by an input current and has a capacitance that varies according to the duty control clock signal. The variable capacitor unit may include a switch, a first capacitor, and a second capacitor. The switch is turned on or off in response to the duty control clock signal. The first capacitor is serially connected to the switch and charged by the input current when the switch is turned on. The second capacitor is connected in parallel to the switch and the first capacitor and charged by the input current.
摘要翻译：提供了能够控制电荷共享时间点的环路滤波器，锁相环以及环路滤波器的操作方法。环路滤波器包括占空比控制单元和可变电容器单元。占空比控制部通过控制输入时钟信号的占空比，生成启动部比灭活部短的占空比控制时钟信号。可变电容器单元由输入电流充电并且具有根据占空比控制时钟信号而变化的电容。可变电容器单元可以包括开关，第一电容器和第二电容器。响应于占空比控制时钟信号，开关导通或关断。当开关打开时，第一个电容器串联连接到开关并由输入电流充电。第二电容器并联连接到开关和第一个电容器，并由输入电流充电。

28. 发明申请

US20070133653A1 Apparatus and method for sensing target temperature 失效
标题翻译：用于感测目标温度的装置和方法
公开(公告)号：US20070133653A1
公开(公告)日：2007-06-14
申请号：US11481739
申请日：2006-07-06
申请人： Hoon Lee , Hoe-Ju Chung
发明人： Hoon Lee , Hoe-Ju Chung
IPC分类号： G01N25/00 , G01K3/00
CPC分类号： G01K7/425 , G01K7/00 , G01N25/20
摘要： For sensing a target temperature, first and second temperature detectors generate first and second delay signals having negative and positive delay changes with temperature. A comparator senses the target temperature from the first and second delay signals such as by activating an output signal when the temperature is at least the target temperature.
摘要翻译：为了感测目标温度，第一和第二温度检测器产生具有随温度的负和正延迟变化的第一和第二延迟信号。比较器从第一和第二延迟信号感测目标温度，例如当温度至少为目标温度时激活输出信号。

29. 发明申请

US20060022758A1 Direct modulator for shift keying modulation 有权
公开(公告)号：US20060022758A1
公开(公告)日：2006-02-02
申请号：US10902746
申请日：2004-07-29
申请人： Chang-Hyeon Lee , Hoon Lee , Akbar Ali
发明人： Chang-Hyeon Lee , Hoon Lee , Akbar Ali
IPC分类号： H03L7/00
CPC分类号： H03C3/0933 , H03C3/0925
摘要： A system for direct modulation is disclosed. Embodiments of the direct modulator for shift-keying modulation include impressing baseband data on a radio frequency (RF) signal at an oscillator by controlling a digital divider using a sigma-delta modulator.

30. 发明授权

US06690717B1 Multi-tone transceiver system using two steps of DMT-CMFB 失效
标题翻译：使用DMT-CMFB两步的多音调收发系统
公开(公告)号：US06690717B1
公开(公告)日：2004-02-10
申请号：US09498917
申请日：2000-02-04
申请人： Jung Hak Kim , Tae Whan Yoo , Hoon Lee , Jeong Jin Lee , Jae Geun Kim
发明人： Jung Hak Kim , Tae Whan Yoo , Hoon Lee , Jeong Jin Lee , Jae Geun Kim
IPC分类号： H04L516
CPC分类号： H04L5/023 , H04L27/2634 , H04L27/264 , H04L27/265 , H04M11/062
摘要： A wideband multi-tone transceiver system interoperable with Asymmetric Digital Subscriber Line (ADSL) transceiver system, and including a two-step transceiver system having a discrete multi-tone transceiver system and a cosine modulated filter bank (CMFB) transmultiplexer. The two-step transceiver system provides a physically transparent transmission channel to each sub-band signal by minimizing the interference between sub-bands regardless of the transmission channel characteristics. The two-step transceiver system is realized with a comparably simple structure, and the circuit size is drastically reduced by sharing the FFT function with other sub-channels with the maximal utilization of the high-speed circuit when realizing each sub-channel's DMT modulation and demodulation function.
摘要翻译：一种与非对称数字用户线（ADSL）收发器系统可互操作的宽带多音收发器系统，包括具有离散多音收发器系统和余弦调制滤波器组（CMFB）多路复用器的两步收发器系统。两步收发器系统通过最小化子带之间的干扰而不管传输信道特性如何，为每个子带信号提供物理透明的传输信道。两级收发器系统采用比较简单的结构实现，通过在实现每个子通道的DMT调制时与高速电路的最大利用率与其他子通道共享FFT功能，大大降低了电路尺寸，解调功能。

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