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1. 发明授权

US08743582B2 3D semiconductor device 有权
标题翻译： 3D半导体器件
公开(公告)号：US08743582B2
公开(公告)日：2014-06-03
申请号：US13115501
申请日：2011-05-25
申请人： Uk-song Kang , Dong-hyeon Jang , Seong-jin Jang , Hoon Lee , Jin-ho Kim , Nam-seog Kim , Byung-sik Moon , Woo-dong Lee
发明人： Uk-song Kang , Dong-hyeon Jang , Seong-jin Jang , Hoon Lee , Jin-ho Kim , Nam-seog Kim , Byung-sik Moon , Woo-dong Lee
IPC分类号： G11C5/06
CPC分类号： H01L23/481 , G11C5/06 , G11C8/18 , H01L22/32 , H01L24/05 , H01L24/16 , H01L24/17 , H01L24/73 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/05572 , H01L2224/16145 , H01L2224/16146 , H01L2224/17051 , H01L2224/17515 , H01L2224/73204 , H01L2224/94 , H01L2225/06513 , H01L2225/06544 , H01L2225/06596 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01047 , H01L2924/01055 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2224/05552 , H01L2924/00
摘要： A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.
摘要翻译：三维（3D）半导体器件可以包括一堆芯片，包括主芯片和一个或多个从芯片。从芯片的I / O连接不需要连接到主板上的通道，只有主芯片的电极焊盘可以连接到通道。只有主芯片可以为通道提供负载。可以在堆叠相同类型的半导体芯片的半导体器件的数据输入路径，数据输出路径，地址/命令路径和/或时钟路径上设置贯穿衬底通孔（TSV）边界。

2. 发明申请

US20110292708A1 3D SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20110292708A1
公开(公告)日：2011-12-01
申请号：US13115501
申请日：2011-05-25
申请人： Uk-song Kang , Dong-hyeon Jang , Seong-jin Jang , Hoon Lee , Jin-ho Kim , Nam-seog Kim , Byung-sik Moon , Woo-dong Lee
发明人： Uk-song Kang , Dong-hyeon Jang , Seong-jin Jang , Hoon Lee , Jin-ho Kim , Nam-seog Kim , Byung-sik Moon , Woo-dong Lee
IPC分类号： G11C5/06 , H01L21/66 , H01L21/50 , G11C8/18 , H01L23/48
CPC分类号： H01L23/481 , G11C5/06 , G11C8/18 , H01L22/32 , H01L24/05 , H01L24/16 , H01L24/17 , H01L24/73 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/05572 , H01L2224/16145 , H01L2224/16146 , H01L2224/17051 , H01L2224/17515 , H01L2224/73204 , H01L2224/94 , H01L2225/06513 , H01L2225/06544 , H01L2225/06596 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01047 , H01L2924/01055 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2224/05552 , H01L2924/00
摘要： A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.
摘要翻译：三维（3D）半导体器件可以包括一堆芯片，包括主芯片和一个或多个从芯片。从芯片的I / O连接不需要连接到主板上的通道，只有主芯片的电极焊盘可以连接到通道。只有主芯片可以为通道提供负载。可以在堆叠相同类型的半导体芯片的半导体器件的数据输入路径，数据输出路径，地址/命令路径和/或时钟路径上设置贯穿衬底通孔（TSV）边界。

3. 发明申请

US20120120733A1 SEMICONDUCTOR DEVICE INCLUDING FUSE ARRAY AND METHOD OF OPERATION THE SAME 有权
标题翻译：包括保险丝阵列的半导体器件及其操作方法
公开(公告)号：US20120120733A1
公开(公告)日：2012-05-17
申请号：US13295484
申请日：2011-11-14
申请人： Jong-pil Son , Seong-jin Jang , Byung-sik Moon , Ju-seop Park
发明人： Jong-pil Son , Seong-jin Jang , Byung-sik Moon , Ju-seop Park
IPC分类号： G11C17/16 , G11C29/00 , G11C7/10
CPC分类号： H01L27/101 , G11C17/14 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device including a fuse and a method of operating the same. The semiconductor device includes a fuse array, a first register unit, and a second register unit. The fuse array includes a plurality of rows and columns. The first register unit receives at least one row of fuse data from the fuse array. Fuse data of the at least one row of fuse data is received in parallel by the first register unit. The second register unit receives the fuse data at least one bit at a time from the first register unit.
摘要翻译：提供一种包括熔丝的半导体器件及其操作方法。半导体器件包括熔丝阵列，第一寄存器单元和第二寄存器单元。熔丝阵列包括多个行和列。第一寄存器单元从熔丝阵列接收至少一行熔丝数据。至少一行熔丝数据的保险丝数据由第一寄存器单元并行接收。第二寄存器单元从第一寄存器单元一次接收至少一个位的熔丝数据。

4. 发明授权

US08482989B2 Semiconductor device including fuse array and method of operation the same 有权
标题翻译：包括熔丝阵列的半导体装置及其操作方法相同
公开(公告)号：US08482989B2
公开(公告)日：2013-07-09
申请号：US13295484
申请日：2011-11-14
申请人： Jong-pil Son , Seong-jin Jang , Byung-sik Moon , Ju-seop Park
发明人： Jong-pil Son , Seong-jin Jang , Byung-sik Moon , Ju-seop Park
IPC分类号： G11C7/00
CPC分类号： H01L27/101 , G11C17/14 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device including a fuse and a method of operating the same. The semiconductor device includes a fuse array, a first register unit, and a second register unit. The fuse array includes a plurality of rows and columns. The first register unit receives at least one row of fuse data from the fuse array. Fuse data of the at least one row of fuse data is received in parallel by the first register unit. The second register unit receives the fuse data at least one bit at a time from the first register unit.
摘要翻译：提供一种包括熔丝的半导体器件及其操作方法。半导体器件包括熔丝阵列，第一寄存器单元和第二寄存器单元。熔丝阵列包括多个行和列。第一寄存器单元从熔丝阵列接收至少一行熔丝数据。至少一行熔丝数据的保险丝数据由第一寄存器单元并行接收。第二寄存器单元从第一寄存器单元一次接收至少一个位的熔丝数据。

5. 发明授权

US08495437B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08495437B2
公开(公告)日：2013-07-23
申请号：US13602906
申请日：2012-09-04
申请人： Kyo-min Sohn , Byung-sik Moon
发明人： Kyo-min Sohn , Byung-sik Moon
IPC分类号： G11C29/00
CPC分类号： G11C7/1063 , G11C7/1006
摘要： A semiconductor memory device including a data bus inversion (DBI) determination unit, a first inverter, a cyclic redundancy check (CRC) calculation unit, a second inverter, and a DQ pin. The DBI determination unit is configured to determine whether to perform DBI based on first data on a main data line and configured to generate DBI data. The first inverter is configured to invert or non-invert the first data according to the DBI data to generate second data. The CRC calculation unit is configured to generate CRC data based on the second data and the DBI data. The second inverter is configured to invert or non-invert the first data according to the DBI data to generate third data. The DQ pin is configured to output the third data externally.
摘要翻译：一种包括数据总线反相（DBI）确定单元，第一反相器，循环冗余校验（CRC）计算单元，第二反相器和DQ引脚的半导体存储器件。 DBI确定单元被配置为基于主数据线上的第一数据来确定是否执行DBI并且被配置为生成DBI数据。第一反相器被配置为根据DBI数据反转或不反转第一数据以产生第二数据。 CRC计算单元被配置为基于第二数据和DBI数据生成CRC数据。第二反相器被配置为根据DBI数据反转或不反转第一数据以产生第三数据。 DQ引脚配置为从外部输出第三个数据。

6. 发明授权

US06304500B1 Integrated circuit memory devices having data input and output lines extending in the column direction, and circuits and methods for repairing faulty cells 有权
标题翻译：具有沿列方向延伸的数据输入和输出线的集成电路存储器件，以及用于修复故障单元的电路和方法
公开(公告)号：US06304500B1
公开(公告)日：2001-10-16
申请号：US09713107
申请日：2000-11-15
申请人： Kye-hyun Kyung , Byung-sik Moon
发明人： Kye-hyun Kyung , Byung-sik Moon
IPC分类号： G11C700
CPC分类号： G11C29/846 , G11C29/848
摘要： Integrated circuit memory devices having data input and output lines in a column direction and circuits and methods for repairing faulty cells are provided. A column select line according to the present invention extends along a row direction. Data input and output lines extend along a column direction. In repairing faulty cells, the column having the faulty cells is not directly replaced by a redundancy column but rather is replaced by an adjacent column. Thus, an increase of layout area upon increase of the input and output lines can be reduced. The operational current also may be reduced. Differences in parasitic capacitance from the respective columns to global input and output lines also may be reduced. Also, the faulty cells may be repaired without lowering the speed at which data is input and output during the redundancy operation.
摘要翻译：提供具有沿列方向的数据输入和输出线的集成电路存储器件以及用于修复故障单元的电路和方法。根据本发明的列选择线沿行方向延伸。数据输入和输出线沿列方向延伸。在修复故障单元时，具有故障单元的列不直接由冗余列替换，而是由相邻列替代。因此，可以减少输入和输出线增加时的布局面积的增加。操作电流也可能降低。寄生电容从各列到全局输入和输出线的差异也可能会降低。此外，可以修复故障小区而不降低在冗余操作期间输入和输出数据的速度。

7. 发明授权

US06151263A Integrated circuit memory devices having data input and output lines extending along the column direction 有权
标题翻译：具有沿列方向延伸的数据输入和输出线的集成电路存储器件
公开(公告)号：US06151263A
公开(公告)日：2000-11-21
申请号：US203262
申请日：1998-12-01
申请人： Kye-hyun Kyung , Byung-sik Moon
发明人： Kye-hyun Kyung , Byung-sik Moon
IPC分类号： H01L27/10 , G11C29/00 , G11C29/04 , G11C8/00
CPC分类号： G11C29/846 , G11C29/848
摘要： Integrated circuit memory devices having data input and output lines in a column direction are provided. A column select line according to the present invention extends along a row direction. Data input and output lines extend along a column direction. Thus, an increase of layout area upon increase of the input and output lines can be reduced. The operational current also may be reduced. Differences in parasitic capacitance from the respective columns to global input and output lines also may be reduced.
摘要翻译：提供具有在列方向上的数据输入和输出线的集成电路存储器件。根据本发明的列选择线沿行方向延伸。数据输入和输出线沿列方向延伸。因此，可以减少输入和输出线增加时的布局面积的增加。操作电流也可能降低。寄生电容从各列到全局输入和输出线的差异也可能会降低。

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