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1. 发明授权

US09071325B2 Saw-less, LNA-less low noise receiver 有权
标题翻译：无锯齿，无LNA低噪声接收器
公开(公告)号：US09071325B2
公开(公告)日：2015-06-30
申请号：US13232873
申请日：2011-09-14
申请人： Rajasekhar Pullela , William J. Domino
发明人： Rajasekhar Pullela , William J. Domino
IPC分类号： H04B1/16 , H04B1/00 , H04B1/10
CPC分类号： H04B1/1638 , H04B1/006 , H04B1/1018
摘要： A low noise receiver includes a downconverter configured to receive a radio frequency (RF) signal, the downconverter comprising a switching architecture configured to generate a plurality of output phases based on a respective plurality of local oscillator (LO) signals, a differencing circuit configured to combine the plurality of output phases such that an nth output phase is differenced with an (n+K)th output phase, resulting in gain-added output phases, and a summation filter configured to receive the gain-added output phases and configured to combine the gain-added output phases such that a response of the receiver effectively reduces odd harmonics of the RF signal.
摘要翻译：低噪声接收器包括被配置为接收射频（RF）信号的下变频器，所述下变频器包括被配置为基于相应的多个本地振荡器（LO）信号产生多个输出相位的开关结构;差分电路，被配置为组合多个输出相位，使得第n个输出相位与第（n + K）个输出相位差，产生增益输出相位，以及相加滤波器，被配置为接收增益输出相位并被配置为组合增益输出相位使得接收器的响应有效地降低了RF信号的奇次谐波。

2. 发明授权

US08145155B2 Passive mixer and high Q RF filter using a passive mixer 有权
标题翻译：无源混频器和高Q RF滤波器采用无源混频器
公开(公告)号：US08145155B2
公开(公告)日：2012-03-27
申请号：US12144986
申请日：2008-06-24
申请人： Rajasekhar Pullela , Mohamed El Said
发明人： Rajasekhar Pullela , Mohamed El Said
IPC分类号： H04B1/04
CPC分类号： H03D7/166 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/1483 , H03D7/165 , H03D2200/0019 , H04B1/28
摘要： A passive mixer include a switching architecture configured to generate differential in-phase (I) and differential quadrature-phase (Q) signals using differential components of the in-phase (I) and quadrature-phase (Q) signals operating on transitions of an approximate 25% duty cycle signal.
摘要翻译：无源混频器包括被配置为使用在同相（I）和正交相位（Q）信号上的差分分量来产生差分同相（I）和差分正交相位（Q）信号的开关架构，约25％的占空比信号。

3. 发明申请

US20090219100A1 VOLTAGE-CONTROLLED OSCILLATOR GAIN CALIBRATION FOR TWO-POINT MODULATION IN A PHASE-LOCKED LOOP 有权
标题翻译：电压控制振荡器在相位锁定环中进行两点调制的增益校准
公开(公告)号：US20090219100A1
公开(公告)日：2009-09-03
申请号：US12040875
申请日：2008-03-01
申请人： Rajasekhar Pullela , Morten Damgaard , Shahrzad Tadjpour , John E. Vasa , Hoon Lee
发明人： Rajasekhar Pullela , Morten Damgaard , Shahrzad Tadjpour , John E. Vasa , Hoon Lee
IPC分类号： G01R23/00
CPC分类号： H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0991
摘要： A phase-locked loop (PLL) is arranged to receive high-pass data at a first input and low-pass data at a second input. A first digital input is coupled to a primary path through a digital-to-analog converter (DAC) and a second digital input is coupled to a feedback path of the PLL. The controller provides the first input and the second input during a calibration procedure. The controller adjusts first and second control inputs in an attempt to keep the input voltage to a voltage-controlled oscillator (VCO) in the PLL constant while determining the gain of the VCO in Hz/LSB.
摘要翻译：锁相环（PLL）被布置成在第一输入处接收高通数据并在第二输入端接收低通数据。第一数字输入通过数模转换器（DAC）耦合到主路径，并且第二数字输入耦合到PLL的反馈路径。控制器在校准过程中提供第一个输入和第二个输入。控制器调整第一和第二控制输入，试图将输入电压保持为PLL中的压控振荡器（VCO），同时以Hz / LSB确定VCO的增益。

4. 发明授权

US07515880B2 Variable gain frequency multiplier 失效
标题翻译：可变增益倍频器
公开(公告)号：US07515880B2
公开(公告)日：2009-04-07
申请号：US11348001
申请日：2006-02-06
申请人： Dmitriy Rozenblit , Rajasekhar Pullela , Tirdad Sowlati , Shahrzad Tadjpour
发明人： Dmitriy Rozenblit , Rajasekhar Pullela , Tirdad Sowlati , Shahrzad Tadjpour
IPC分类号： H04B1/38
CPC分类号： H03B19/14 , H03G3/3047 , H03L7/081 , H03L7/087 , H03L7/0992 , H03L7/1978 , H03L7/23
摘要： A variable gain frequency multiplier comprises a multiplier circuit and a control circuit configured to receive a power control signal, the power control signal being proportional to a power output signal.
摘要翻译：可变增益倍频器包括乘法器电路和被配置为接收功率控制信号的控制电路，功率控制信号与功率输出信号成比例。

5. 发明授权

US07398073B2 Low noise mixer 有权
标题翻译：低噪音混音器
公开(公告)号：US07398073B2
公开(公告)日：2008-07-08
申请号：US11220030
申请日：2005-09-06
申请人： Rajasekhar Pullela , Tirdad Sowlati , Dmitriy Rozenblit
发明人： Rajasekhar Pullela , Tirdad Sowlati , Dmitriy Rozenblit
IPC分类号： H04B1/26
CPC分类号： H04B1/28 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/165 , H03D2200/0019 , H03D2200/0084
摘要： A low noise mixer comprises a first mixer core configured to receive a radio frequency (RF) input signal having an RF frequency, and a first local oscillator signal, wherein the first local oscillator signal is at a frequency that is nominally twice the frequency of the RF frequency, the first mixer core configured to switch the RF input signal to at least one secondary mixer core at a frequency that coincides with the frequency of the first local oscillator signal, the at least one secondary mixer core configured to receive the switched RF input signal and a second local oscillator signal, where the second local oscillator signal is at the same nominal frequency as the RF input signal, and wherein switching the RF input signal at the frequency of the first local oscillator signal substantially eliminates flicker noise associated with the down-conversion process.
摘要翻译：低噪声混频器包括被配置为接收具有RF频率的射频（RF）输入信号和第一本地振荡器信号的第一混频器核心，其中第一本地振荡器信号的频率是标称频率为 RF频率，所述第一混频器核心被配置为以与所述第一本机振荡器信号的频率一致的频率将所述RF输入信号切换到至少一个辅助混频器内核，所述至少一个辅助混频器核心被配置为接收所述切换的RF输入信号和第二本地振荡器信号，其中第二本机振荡器信号处于与RF输入信号相同的标称频率，并且其中以第一本地振荡器信号的频率切换RF输入信号基本上消除与下降相关联的闪烁噪声转换过程。

6. 发明授权

US07009438B2 Trans-admittance trans-impedance logic for integrated circuits 有权
公开(公告)号：US07009438B2
公开(公告)日：2006-03-07
申请号：US10033525
申请日：2001-12-28
申请人： Rajasekhar Pullela , Mario Reinhold
发明人： Rajasekhar Pullela , Mario Reinhold
IPC分类号： H03K3/02
CPC分类号： H03K3/0231
摘要： A logic circuit with improved performance when operating at the limits of the transistor's bandwidth. In particular, a latch includes a clocked trans-admittance stage circuit for receiving a voltage and producing a current output, and an active load, such as a trans-impedance stage circuit, connected to receive as input the current output of the trans-admittance stage circuit and produce a voltage output. Two independent trans-admittance and trans-impedance stages may be combined as a single latch pair. One or more latch pairs may be arranged in series as a cascaded chain and connected to the output current of a clocked trans-admittance stage latch.

7. 发明授权

US06297706B1 Single stage voltage controlled ring oscillator 失效
标题翻译：单级电压控制环形振荡器
公开(公告)号：US06297706B1
公开(公告)日：2001-10-02
申请号：US09415602
申请日：1999-10-08
申请人： Rajasekhar Pullela
发明人： Rajasekhar Pullela
IPC分类号： H03B502
CPC分类号： H03K3/0231
摘要： A single stage voltage controlled ring oscillator includes a trans-admittance voltage-to-current circuit coupled to a trans-impedance voltage-to-current circuit. The output of the trans-impedance circuit is connected to the input of the trans-admittance circuit. The trans-admittance and trans-impedance circuit are preferably conjugately matched and may be coupled to each other via one or more transmission lines, the length of which can be selected to set a desired nominal oscillation frequency. The trans-impedance and trans-admittance circuits may also include voltage-controllable components which can be adjusted to tune the oscillation frequency.
摘要翻译：单级电压控制环形振荡器包括耦合到跨阻抗电压 - 电流电路的跨导纳电压 - 电流电路。跨阻抗电路的输出端连接到反向导纳电路的输入端。互导体和跨阻抗电路优选地共轭匹配，并且可以经由一个或多个传输线彼此耦合，该传输线的长度可被选择以设定期望的标称振荡频率。跨阻抗和导纳电路还可以包括可以调节以调节振荡频率的电压可控分量。

8. 发明授权

US08406707B2 Systems and methods for implementing a harmonic rejection mixer 有权
标题翻译：用于实现谐波抑制混频器的系统和方法
公开(公告)号：US08406707B2
公开(公告)日：2013-03-26
申请号：US13419741
申请日：2012-03-14
申请人： Rajasekhar Pullela , Dmitriy Rozenblit , Hamid Firouzkouhi
发明人： Rajasekhar Pullela , Dmitriy Rozenblit , Hamid Firouzkouhi
IPC分类号： H04B1/04 , H04B15/00
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D7/165 , H03D2200/0047 , H03D2200/0086
摘要： Various embodiments of systems and methods for generating local oscillator (LO) signals for a harmonic rejection mixer are provided. One embodiment is a system for generating local oscillator (LO) signals for a harmonic rejection mixer. One such system comprises a local oscillator, a divide-by-N frequency divider, a divide-by-three frequency divider, and a harmonic rejection mixer. The local oscillator is configured to provide a reference frequency signal. The divide-by-N frequency divider is configured to divide the reference frequency signal by a value N and provide an output signal. The divide-by-three frequency divider is configured to receive the output signal of the divide-by-N frequency divider and divide the output signal into three phase-offset signals. The harmonic rejection mixer is configured to receive the three phase-offset signals and eliminate third frequency harmonics.
摘要翻译：提供了用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统和方法的各种实施例。一个实施例是用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统。一个这样的系统包括本地振荡器，N分频分频器，除以三分频器和谐波抑制混频器。本地振荡器被配置为提供参考频率信号。 N分频器被配置为将参考频率信号除以值N并提供输出信号。三分频分频器被配置为接收除以N分频器的输出信号，并将输出信号分成三个相位偏移信号。谐波抑制混频器被配置为接收三个相位偏移信号并消除第三频率谐波。

9. 发明申请

US20120171973A1 SYSTEMS AND METHODS FOR IMPLEMENTING A HARMONIC REJECTION MIXER 有权
标题翻译：用于实施谐波抑制混合器的系统和方法
公开(公告)号：US20120171973A1
公开(公告)日：2012-07-05
申请号：US13419741
申请日：2012-03-14
申请人： Rajasekhar Pullela , Dmitriy Rozenblit , Hamid Firouzkouhi
发明人： Rajasekhar Pullela , Dmitriy Rozenblit , Hamid Firouzkouhi
IPC分类号： H04B1/04 , G06G7/00 , H04B1/26
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D7/165 , H03D2200/0047 , H03D2200/0086
摘要： Various embodiments of systems and methods for generating local oscillator (LO) signals for a harmonic rejection mixer are provided. One embodiment is a system for generating local oscillator (LO) signals for a harmonic rejection mixer. One such system comprises a local oscillator, a divide-by-N frequency divider, a divide-by-three frequency divider, and a harmonic rejection mixer. The local oscillator is configured to provide a reference frequency signal. The divide-by-N frequency divider is configured to divide the reference frequency signal by a value N and provide an output signal. The divide-by-three frequency divider is configured to receive the output signal of the divide-by-N frequency divider and divide the output signal into three phase-offset signals. The harmonic rejection mixer is configured to receive the three phase-offset signals and eliminate third frequency harmonics.
摘要翻译：提供了用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统和方法的各种实施例。一个实施例是用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统。一个这样的系统包括本地振荡器，N分频分频器，除以三分频器和谐波抑制混频器。本地振荡器被配置为提供参考频率信号。 N分频器被配置为将参考频率信号除以值N并提供输出信号。三分频分频器被配置为接收除以N分频器的输出信号，并将输出信号分成三个相位偏移信号。谐波抑制混频器被配置为接收三个相位偏移信号并消除第三频率谐波。

10. 发明申请

US20090325510A1 SYSTEMS AND METHODS FOR IMPLEMENTING A HARMONIC REJECTION MIXER 有权
标题翻译：用于实施谐波抑制混合器的系统和方法
公开(公告)号：US20090325510A1
公开(公告)日：2009-12-31
申请号：US12145599
申请日：2008-06-25
申请人： Rajasekhar Pullela , Dmitriy Rozenblit , Hamid Firouzkouhi
发明人： Rajasekhar Pullela , Dmitriy Rozenblit , Hamid Firouzkouhi
IPC分类号： G06G7/161 , H03K5/00
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D7/165 , H03D2200/0047 , H03D2200/0086
摘要： Various embodiments of systems and methods for generating local oscillator (LO) signals for a harmonic rejection mixer are provided. One embodiment is a system for generating local oscillator (LO) signals for a harmonic rejection mixer. One such system comprises a local oscillator, a divide-by-N frequency divider, a divide-by-three frequency divider, and a harmonic rejection mixer. The local oscillator is configured to provide a reference frequency signal. The divide-by-N frequency divider is configured to divide the reference frequency signal by a value N and provide an output signal. The divide-by-three frequency divider is configured to receive the output signal of the divide-by-N frequency divider and divide the output signal into three phase-offset signals. The harmonic rejection mixer is configured to receive the three phase-offset signals and eliminate third frequency harmonics.
摘要翻译：提供了用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统和方法的各种实施例。一个实施例是用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统。一个这样的系统包括本地振荡器，N分频分频器，除以三分频器和谐波抑制混频器。本地振荡器被配置为提供参考频率信号。 N分频器被配置为将参考频率信号除以值N并提供输出信号。三分频分频器被配置为接收除以N分频器的输出信号，并将输出信号分成三个相位偏移信号。谐波抑制混频器被配置为接收三个相位偏移信号并消除第三频率谐波。

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