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1. 发明授权

US07109805B2 Direct modulator for shift keying modulation 有权
标题翻译：用于移位键控调制的直接调制器
公开(公告)号：US07109805B2
公开(公告)日：2006-09-19
申请号：US10902746
申请日：2004-07-29
申请人： Chang-Hyeon Lee , Hoon Lee , Akbar Ali
发明人： Chang-Hyeon Lee , Hoon Lee , Akbar Ali
IPC分类号： H03L7/00 , H03C3/06 , H03M3/00
CPC分类号： H03C3/0933 , H03C3/0925
摘要： A system for direct modulation is disclosed. Embodiments of the direct modulator for shift-keying modulation include impressing baseband data on a radio frequency (RF) signal at an oscillator by controlling a digital divider using a sigma-delta modulator.
摘要翻译：公开了一种用于直接调制的系统。用于移位键控调制的直接调制器的实施例包括通过使用Σ-Δ调制器控制数字分频器在振荡器处对射频（RF）信号施加基带数据。

2. 发明申请

US20060022758A1 Direct modulator for shift keying modulation 有权
公开(公告)号：US20060022758A1
公开(公告)日：2006-02-02
申请号：US10902746
申请日：2004-07-29
申请人： Chang-Hyeon Lee , Hoon Lee , Akbar Ali
发明人： Chang-Hyeon Lee , Hoon Lee , Akbar Ali
IPC分类号： H03L7/00
CPC分类号： H03C3/0933 , H03C3/0925
摘要： A system for direct modulation is disclosed. Embodiments of the direct modulator for shift-keying modulation include impressing baseband data on a radio frequency (RF) signal at an oscillator by controlling a digital divider using a sigma-delta modulator.

3. 发明授权

US07259633B2 Frequency synthesizer with loop filter calibration for bandwidth control 有权
标题翻译：带循环滤波器校准的频率合成器，用于带宽控制
公开(公告)号：US07259633B2
公开(公告)日：2007-08-21
申请号：US11137210
申请日：2005-05-24
申请人： Chang-Hyeon Lee , Akbar Ali
发明人： Chang-Hyeon Lee , Akbar Ali
IPC分类号： H03L7/00 , H03L7/093
CPC分类号： H03L7/093 , H03C3/0925 , H03C3/0933 , H03L7/07 , H03L7/0891 , H03L7/197 , H03L7/1976
摘要： According to one exemplary embodiment, a frequency synthesizer module includes a loop filter, where the loop filter includes a capacitor having a first terminal and a second terminal. The frequency synthesizer module further includes a loop filter calibration module coupled to the capacitor in the loop filter. The loop filter calibration module causes an initial capacitance between the first terminal and the second terminal of the capacitor to increase to a target capacitance when the loop filter is in a calibration mode. The target capacitance can causes in increase in control of a bandwidth of the loop filter and a reduction in percent error of a unity gain bandwidth of the loop filter. The loop filter further includes a switched capacitor array configured to cause the initial capacitance to increase to the target capacitance in response to a digital feedback signal provided by the loop filter calibration module.
摘要翻译：根据一个示例性实施例，频率合成器模块包括环路滤波器，其中环路滤波器包括具有第一端子和第二端子的电容器。频率合成器模块还包括耦合到环路滤波器中的电容器的环路滤波器校准模块。当环路滤波器处于校准模式时，环路滤波器校准模块使得电容器的第一端子和第二端子之间的初始电容增加到目标电容。目标电容可以导致环路滤波器的带宽的控制的增加和环路滤波器的单位增益带宽的百分比误差的减小。环路滤波器还包括开关电容器阵列，其被配置为响应于由环路滤波器校准模块提供的数字反馈信号而使初始电容增加到目标电容。

4. 发明申请

US20060267697A1 Frequency synthesizer with loop filter calibration for bandwidth control 有权
标题翻译：带循环滤波器校准的频率合成器，用于带宽控制
公开(公告)号：US20060267697A1
公开(公告)日：2006-11-30
申请号：US11137210
申请日：2005-05-24
申请人： Chang-Hyeon Lee , Akbar Ali
发明人： Chang-Hyeon Lee , Akbar Ali
IPC分类号： H03L7/00
CPC分类号： H03L7/093 , H03C3/0925 , H03C3/0933 , H03L7/07 , H03L7/0891 , H03L7/197 , H03L7/1976
摘要： According to one exemplary embodiment, a frequency synthesizer module includes a loop filter, where the loop filter includes a capacitor having a first terminal and a second terminal. The frequency synthesizer module further includes a loop filter calibration module coupled to the capacitor in the loop filter. The loop filter calibration module causes an initial capacitance between the first terminal and the second terminal of the capacitor to increase to a target capacitance when the loop filter is in a calibration mode. The target capacitance can causes in increase in control of a bandwidth of the loop filter and a reduction in percent error of a unity gain bandwidth of the loop filter. The loop filter further includes a switched capacitor array configured to cause the initial capacitance to increase to the target capacitance in response to a digital feedback signal provided by the loop filter calibration module.
摘要翻译：根据一个示例性实施例，频率合成器模块包括环路滤波器，其中环路滤波器包括具有第一端子和第二端子的电容器。频率合成器模块还包括耦合到环路滤波器中的电容器的环路滤波器校准模块。当环路滤波器处于校准模式时，环路滤波器校准模块使得电容器的第一端子和第二端子之间的初始电容增加到目标电容。目标电容可以导致环路滤波器的带宽的控制的增加和环路滤波器的单位增益带宽的百分比误差的减小。环路滤波器还包括开关电容器阵列，其被配置为响应于由环路滤波器校准模块提供的数字反馈信号而使初始电容增加到目标电容。

5. 发明授权

US06968029B1 Frequency prescaler 有权
标题翻译：频率预分频器
公开(公告)号：US06968029B1
公开(公告)日：2005-11-22
申请号：US10910731
申请日：2004-08-03
申请人： Chang-Hyeon Lee , Akbar Ali
发明人： Chang-Hyeon Lee , Akbar Ali
IPC分类号： H03K21/00 , H03K23/48
CPC分类号： H03K23/483
摘要： A synchronous prescaler is provided that has an input line for receiving an input signal, which is synchronized to a low order dual modulus prescaler. The dual modulus prescaler generally divides responsive to a mode command line, but may have a dead-zone period where it may fail to respond to a generated mode command. The dual modulus prescaler also has an output line that is synchronized to an extender section. The extender section is used to further divide the input signal, and is synchronized to an adjustable counter section. A sync controller circuit receives an output from the counter section, as well as a timing signal from the extender, and generates the mode signal on the mode command line. In this arrangement, the sync controller generates the mode signal at a time when the low order dual modulus is in a condition to change divide modes, thereby avoiding providing the signal during the dead-zone period.
摘要翻译：提供了一种同步预分频器，其具有用于接收与低阶双模预分频器同步的输入信号的输入线。双模预分频器通常根据模式命令行分隔，但可能具有死区周期，其中它可能无法响应生成的模式命令。双模预分频器还具有与扩展器部分同步的输出线。扩展器部分用于进一步分割输入信号，并与可调节的计数器部分同步。同步控制器电路接收来自计数器部分的输出以及来自延长器的定时信号，并在模式命令行上生成模式信号。在这种布置中，同步控制器在低阶双模量处于改变分频模式的条件下产生模式信号，从而避免在死区期间提供信号。

6. 发明授权

US06954090B2 Charge pump having reduced switching noise 有权
标题翻译：电荷泵具有降低的开关噪声
公开(公告)号：US06954090B2
公开(公告)日：2005-10-11
申请号：US10601959
申请日：2003-06-23
申请人： Chang-Hyeon Lee , Akbar Ali
发明人： Chang-Hyeon Lee , Akbar Ali
IPC分类号： H03L7/08 , H03L7/089 , H03L7/06
CPC分类号： H03L7/0802 , H03L7/0895 , H03L7/0896
摘要： A low power charge pump is provided that has complementary transistors capable of isolating switching noise from the input switching transistors. The charge pump uses charged currents that are matched in both magnitude and time to reduce switching noise in the output of the charge pump. The charge pump is also designed for use in a phase lock loop.
摘要翻译：提供了一种具有能够与开关晶体管隔离开关噪声的互补晶体管的低功率电荷泵。电荷泵使用在幅度和时间上匹配的充电电流来降低电荷泵输出中的开关噪声。电荷泵也设计用于锁相环。

7. 发明授权

US06611160B1 Charge pump having reduced switching noise 有权
公开(公告)号：US06611160B1
公开(公告)日：2003-08-26
申请号：US09718963
申请日：2000-11-21
申请人： Chang-Hyeon Lee , Akbar Ali
发明人： Chang-Hyeon Lee , Akbar Ali
IPC分类号： H03L706
CPC分类号： H03L7/0802 , H03L7/0895 , H03L7/0896
摘要： A low power charge pump is provided that has complementary transistors capable of isolating switching noise from the input switching transistors. The charge pump uses charged currents that are matched in both magnitude and time to reduce switching noise in the output of the charge pump. The charge pump is also designed for use in a phase lock loop.

8. 发明申请

US20050227629A1 High agility frequency synthesizer phase-locked loop 有权
标题翻译：高灵敏度频率合成器锁相环
公开(公告)号：US20050227629A1
公开(公告)日：2005-10-13
申请号：US10821531
申请日：2004-04-09
申请人： Akbar Ali , James Young
发明人： Akbar Ali , James Young
IPC分类号： H03L7/22 , H04B1/38
CPC分类号： H03L7/22
摘要： A highly agile low phase noise frequency synthesizer is provided for rapid generation of frequency specific signals. The frequency synthesizer is capable of rapidly generating signals at different output frequencies while maintaining low cross-coupling. Two or more signal generators utilize a reference frequency to generate two or more signals. These signals are limit processed to reduce cross-coupling prior to being presented to a switch. Responsive to a control signal, the switch outputs one of the signals to a frequency modification device, such as a frequency divider or multiplier. Responsive to a control signal, the frequency modification device scales the frequency of the switch output to convert the frequency of the switch output signal to a desired output frequency. By maintaining sufficient frequency separation between the switch input signals cross-coupling and phase noise is minimized and implementation on an integrated circuit may be achieved.
摘要翻译：提供了一种高灵敏度的低相位噪声频率合成器，用于快速产生频率特定信号。频率合成器能够在保持低交叉耦合的同时快速产生不同输出频率的信号。两个或更多个信号发生器利用参考频率来产生两个或更多个信号。这些信号被限制处理，以便在呈现给开关之前减少交叉耦合。响应于控制信号，开关将一个信号输出到频率修改装置，例如分频器或乘法器。响应于控制信号，频率修改装置缩放开关输出的频率，以将开关输出信号的频率转换为期望的输出频率。通过在开关输入信号之间保持足够的频率间隔，交叉耦合和相位噪声被最小化，并且可以实现集成电路上的实现。

9. 发明授权

US07747237B2 High agility frequency synthesizer phase-locked loop 有权
标题翻译：高灵敏度频率合成器锁相环
公开(公告)号：US07747237B2
公开(公告)日：2010-06-29
申请号：US10821531
申请日：2004-04-09
申请人： Akbar Ali , James P. Young
发明人： Akbar Ali , James P. Young
IPC分类号： H04B1/06 , H04B7/00
CPC分类号： H03L7/22
摘要： A highly agile low phase noise frequency synthesizer is provided for rapid generation of frequency specific signals. The frequency synthesizer is capable of rapidly generating signals at different output frequencies while maintaining low cross-coupling. Two or more signal generators utilize a reference frequency to generate two or more signals. These signals are limit processed to reduce cross-coupling prior to being presented to a switch. Responsive to a control signal, the switch outputs one of the signals to a frequency modification device, such as a frequency divider or multiplier. Responsive to a control signal, the frequency modification device scales the frequency of the switch output to convert the frequency of the switch output signal to a desired output frequency. By maintaining sufficient frequency separation between the switch input signals cross-coupling and phase noise is minimized and implementation on an integrated circuit may be achieved.
摘要翻译：提供了一种高灵敏度的低相位噪声频率合成器，用于快速产生频率特定信号。频率合成器能够在保持低交叉耦合的同时快速产生不同输出频率的信号。两个或更多个信号发生器利用参考频率来产生两个或更多个信号。这些信号被限制处理，以便在呈现给开关之前减少交叉耦合。响应于控制信号，开关将一个信号输出到频率修改装置，例如分频器或乘法器。响应于控制信号，频率修改装置缩放开关输出的频率，以将开关输出信号的频率转换为期望的输出频率。通过在开关输入信号之间保持足够的频率间隔，交叉耦合和相位噪声被最小化，并且可以实现集成电路上的实现。

10. 发明授权

US06377129B1 Programmable relaxation oscillator 有权
标题翻译：可编程松弛振荡器
公开(公告)号：US06377129B1
公开(公告)日：2002-04-23
申请号：US09302754
申请日：1999-04-30
申请人： Woogeun Rhee , Akbar Ali
发明人： Woogeun Rhee , Akbar Ali
IPC分类号： H03K3282
CPC分类号： H03K3/354
摘要： An oscillator has a slope-fixing circuit that generates a control signal and fixes the slope of the control signal, a swing-fixing circuit that fixes the swing of the control signal, and a switching block that generates an output signal having a frequency derived from the swing and the slope of the control signal. The slope-fixing circuit comprises a fixed timing capacitor C1 in parallel with a plurality of switchable timing capacitors C2 . . . CN to provide an effective capacitance C. The slope of the control signal is determined by the ratio of a control current I to the effective capacitance C. The swing-fixing circuit comprises a replica cell that accepts a programmable reference voltage VREF and provides a fixed voltage swing VSW=VDD−VREF across a pair of load transistors. The switching block comprises a pair of switching transistors that alternate between “on” and “off” states depending on the value of the control signal to produce an oscillating output signal. The frequency of the output signal is given by I 4 ⁢ CV SW .
摘要翻译：振荡器具有产生控制信号并固定控制信号的斜率的斜坡固定电路，固定控制信号的摆动的摆动固定电路以及产生具有从...得到的频率的输出信号的开关块控制信号的摆幅和斜率。斜坡固定电路包括与多个可切换定时电容器C2并联的固定定时电容器C1。。。 CN以提供有效电容C.控制信号的斜率由控制电流I与有效电容C的比确定。摆幅固定电路包括接受可编程参考电压VREF的复制单元并提供固定的一对负载晶体管的摆幅VSW = VDD-VREF。切换块包括一对开关晶体管，其根据控制信号的值在“导通”和“断开”状态之间交替以产生振荡输出信号。输出信号的频率由下式给出

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