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1. 发明申请

US20120300528A1 Stacked Memory Module and System 有权
标题翻译：堆叠内存模块和系统
公开(公告)号：US20120300528A1
公开(公告)日：2012-11-29
申请号：US13535363
申请日：2012-06-28
申请人： Uk-song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
发明人： Uk-song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , G11C5/025 , G11C5/04 , G11C8/12 , G11C8/18 , G11C29/14 , H01L23/481 , H01L25/0657 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/05099
摘要： A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.
摘要翻译：三维存储器模块和系统形成有在主芯片上堆叠的至少一个从芯片。通过半导体通孔（TSV）通过主芯片和从芯片中的至少一个形成。主芯片包括用于增加存储器模块/系统容量的存储器核心。此外，公开了形成有效布线的三维存储器模块/系统的容量组织，用于形成三维存储器模块/系统的多个存储器组，多个存储体组和/或多个等级。

2. 发明授权

US08031505B2 Stacked memory module and system 有权
标题翻译：堆叠内存模块和系统
公开(公告)号：US08031505B2
公开(公告)日：2011-10-04
申请号：US12454064
申请日：2009-05-12
申请人： Uk-Song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
发明人： Uk-Song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , G11C5/025 , G11C5/04 , G11C8/12 , G11C8/18 , G11C29/14 , H01L23/481 , H01L25/0657 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/05099
摘要： A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.
摘要翻译：三维存储器模块和系统形成有在主芯片上堆叠的至少一个从芯片。通过半导体通孔（TSV）通过主芯片和从芯片中的至少一个形成。主芯片包括用于增加存储器模块/系统容量的存储器核心。此外，公开了形成有效布线的三维存储器模块/系统的容量组织，用于形成三维存储器模块/系统的多个存储器组，多个存储体组和/或多个等级。

3. 发明授权

US07502274B2 Apparatus and method for sensing target temperature 失效
标题翻译：用于感测目标温度的装置和方法
公开(公告)号：US07502274B2
公开(公告)日：2009-03-10
申请号：US11481739
申请日：2006-07-06
申请人： Hoon Lee , Hoe-Ju Chung
发明人： Hoon Lee , Hoe-Ju Chung
IPC分类号： G11C7/04
CPC分类号： G01K7/425 , G01K7/00 , G01N25/20
摘要： For sensing a target temperature, first and second temperature detectors generate first and second delay signals having negative and positive delay changes with temperature. A comparator senses the target temperature from the first and second delay signals such as by activating an output signal when the temperature is at least the target temperature.
摘要翻译：为了感测目标温度，第一和第二温度检测器产生具有随温度的负和正延迟变化的第一和第二延迟信号。比较器从第一和第二延迟信号感测目标温度，例如当温度至少为目标温度时激活输出信号。

4. 发明授权

US08369123B2 Stacked memory module and system 有权
标题翻译：堆叠内存模块和系统
公开(公告)号：US08369123B2
公开(公告)日：2013-02-05
申请号：US13535363
申请日：2012-06-28
申请人： Uk-Song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
发明人： Uk-Song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , G11C5/025 , G11C5/04 , G11C8/12 , G11C8/18 , G11C29/14 , H01L23/481 , H01L25/0657 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/05099
摘要： A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.
摘要翻译：三维存储器模块和系统形成有在主芯片上堆叠的至少一个从芯片。通过半导体通孔（TSV）通过主芯片和从芯片中的至少一个形成。主芯片包括用于增加存储器模块/系统容量的存储器核心。此外，公开了形成有效布线的三维存储器模块/系统的容量组织，用于形成三维存储器模块/系统的多个存储器组，多个存储体组和/或多个等级。

5. 发明申请

US20100020583A1 Stacked memory module and system 有权
标题翻译：堆叠内存模块和系统
公开(公告)号：US20100020583A1
公开(公告)日：2010-01-28
申请号：US12454064
申请日：2009-05-12
申请人： Uk-Song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
发明人： Uk-Song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
IPC分类号： G11C5/02 , G11C5/06
CPC分类号： G11C5/02 , G11C5/025 , G11C5/04 , G11C8/12 , G11C8/18 , G11C29/14 , H01L23/481 , H01L25/0657 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/05099
摘要： A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.
摘要翻译：三维存储器模块和系统形成有在主芯片上堆叠的至少一个从芯片。通过半导体通孔（TSV）通过主芯片和从芯片中的至少一个形成。主芯片包括用于增加存储器模块/系统容量的存储器核心。此外，公开了形成有效布线的三维存储器模块/系统的容量组织，用于形成三维存储器模块/系统的多个存储器组，多个存储体组和/或多个等级。

6. 发明申请

US20070133653A1 Apparatus and method for sensing target temperature 失效
标题翻译：用于感测目标温度的装置和方法
公开(公告)号：US20070133653A1
公开(公告)日：2007-06-14
申请号：US11481739
申请日：2006-07-06
申请人： Hoon Lee , Hoe-Ju Chung
发明人： Hoon Lee , Hoe-Ju Chung
IPC分类号： G01N25/00 , G01K3/00
CPC分类号： G01K7/425 , G01K7/00 , G01N25/20
摘要： For sensing a target temperature, first and second temperature detectors generate first and second delay signals having negative and positive delay changes with temperature. A comparator senses the target temperature from the first and second delay signals such as by activating an output signal when the temperature is at least the target temperature.
摘要翻译：为了感测目标温度，第一和第二温度检测器产生具有随温度的负和正延迟变化的第一和第二延迟信号。比较器从第一和第二延迟信号感测目标温度，例如当温度至少为目标温度时激活输出信号。

7. 发明授权

US08243487B2 Stacked memory module and system 有权
标题翻译：堆叠内存模块和系统
公开(公告)号：US08243487B2
公开(公告)日：2012-08-14
申请号：US13218646
申请日：2011-08-26
申请人： Uk-Song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
发明人： Uk-Song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , G11C5/025 , G11C5/04 , G11C8/12 , G11C8/18 , G11C29/14 , H01L23/481 , H01L25/0657 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/05099
摘要： A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.
摘要翻译：三维存储器模块和系统形成有在主芯片上堆叠的至少一个从芯片。通过半导体通孔（TSV）通过主芯片和从芯片中的至少一个形成。主芯片包括用于增加存储器模块/系统容量的存储器核心。此外，公开了形成有效布线的三维存储器模块/系统的容量组织，用于形成三维存储器模块/系统的多个存储器组，多个存储体组和/或多个等级。

8. 发明申请

US20110310649A1 Stacked Memory Module and System 有权
标题翻译：堆叠内存模块和系统
公开(公告)号：US20110310649A1
公开(公告)日：2011-12-22
申请号：US13218646
申请日：2011-08-26
申请人： Uk-song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
发明人： Uk-song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , G11C5/025 , G11C5/04 , G11C8/12 , G11C8/18 , G11C29/14 , H01L23/481 , H01L25/0657 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/05099
摘要： A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.
摘要翻译：三维存储器模块和系统形成有在主芯片上堆叠的至少一个从芯片。通过半导体通孔（TSV）通过主芯片和从芯片中的至少一个形成。主芯片包括用于增加存储器模块/系统容量的存储器核心。此外，公开了形成有效布线的三维存储器模块/系统的容量组织，用于形成三维存储器模块/系统的多个存储器组，多个存储体组和/或多个等级。

9. 发明授权

US08230140B2 Latency control circuit and method using queuing design method 失效
标题翻译：延迟控制电路和使用排队设计方法的方法
公开(公告)号：US08230140B2
公开(公告)日：2012-07-24
申请号：US13178846
申请日：2011-07-08
申请人： Byung-Hoon Jeong , Hoe-Ju Chung
发明人： Byung-Hoon Jeong , Hoe-Ju Chung
IPC分类号： G06F3/00
CPC分类号： G11C7/22 , G11C7/1066 , G11C7/1078 , G11C7/109 , G11C8/18 , G11C11/4076 , G11C11/4093 , G11C2207/2272
摘要： A latency control circuit includes a FIFO controller and a register unit. The FIFO controller may generate an increase signal according to an external command, and generate a decrease signal according to an internal command. The FIFO controller may also enable a depth point signal responsive to the increase signal and the decrease signal. The register unit may include n registers. The value n (rounded off) may be obtained by dividing a larger value of a maximum number of additive latencies and a maximum number of write latencies by a column cycle delay time (tCCD). The registers may store an address received with the external command responsive to the increase signal and a clock signal, and may shift either the address or a previous address to a neighboring register. The latency control circuit transmits an address stored in a register as a column address corresponding to the enabled depth point signal.
摘要翻译：等待时间控制电路包括FIFO控制器和寄存器单元。 FIFO控制器可以根据外部命令生成增加信号，并根据内部命令生成减少信号。 FIFO控制器还可以响应于增加信号和减小信号启用深度点信号。寄存器单元可以包括n个寄存器。值n（四舍五入）可以通过将最大数量的加性延迟和最大写入延迟数的较大值除以列周期延迟时间（tCCD）来获得。寄存器可以响应于增加信号和时钟信号而存储与外部命令接收的地址，并且可以将地址或先前地址移位到相邻寄存器。延迟控制电路将存储在寄存器中的地址作为与启用的深度点信号相对应的列地址。

10. 发明授权

US08112680B2 System and device with error detection/correction process and method outputting data 有权
标题翻译：具有错误检测/校正处理和方法输出数据的系统和设备
公开(公告)号：US08112680B2
公开(公告)日：2012-02-07
申请号：US12044183
申请日：2008-03-07
申请人： Hoe-Ju Chung , Jung-Bae Lee
发明人： Hoe-Ju Chung , Jung-Bae Lee
IPC分类号： G06F11/00
CPC分类号： G06F11/1008 , G11C5/02 , G11C5/04 , G11C7/02 , G11C7/1006 , G11C7/1045 , G11C2029/0411 , H04L1/0041 , H04L1/0057
摘要： A system, device and related method are used to communicate data via a plurality of data lanes including a selected data lane. In a first mode of operation, payload data and related supplemental data are communicated via the plurality of data lanes including the selected data lane. In a second mode of operation, only payload data is communicated via the plurality of data lanes, except the selected data lane.
摘要翻译：系统，设备和相关方法用于经由包括所选择的数据通道的多个数据通道来传送数据。在第一操作模式中，经由包括所选择的数据通道的多个数据通道来传送有效载荷数据和相关的补充数据。在第二种操作模式中，只有有效载荷数据经由多个数据通道被传送，除了所选择的数据通道。

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