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11. 发明授权

US06236103B1 Integrated high-performance decoupling capacitor and heat sink 失效
标题翻译：集成高性能去耦电容和散热片
公开(公告)号：US06236103B1
公开(公告)日：2001-05-22
申请号：US09283828
申请日：1999-03-31
申请人： Kerry Bernstein , Robert M. Geffken , Wilbur D. Pricer , Anthony K. Stamper , Steven H. Voldman
发明人： Kerry Bernstein , Robert M. Geffken , Wilbur D. Pricer , Anthony K. Stamper , Steven H. Voldman
IPC分类号： H01L2900
CPC分类号： H01L28/40 , H01L23/3672 , H01L23/3735 , H01L27/0805 , H01L2924/0002 , H01L2924/10158 , H01L2924/00
摘要： A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip. The structure thus provides both a significant and effective decoupling capacitance in close proximity to the active circuit on the chip requiring such decoupling capacitance as well as providing improved heat sinking for the decoupled active circuit.
摘要翻译：一种显着且非常有效的去耦电容器和散热器组合，其在单个结构中提供散热器和去耦电容器，其紧邻芯片上的有源电路，需要散热或去耦电容或两者兼有。这通过在其中具有掩埋氧化物层的半导体芯片上形成集成的高性能去耦电容器来实现，所述高性能去耦电容器使用形成在芯片的背面上并且电连接到有源芯片电路的大于30微米厚的金属沉积物导致显着且非常有效的去耦电容器和散热器紧邻芯片上的有源电路，需要这种去耦电容和散热能力。去耦电容可以使用芯片本身的衬底作为电容板之一，并且形成金属沉积物作为第二电容板，其也用作形成在芯片中的有源电路的散热器。因此，该结构提供了重要且有效的去耦电容，其紧邻芯片上的有源电路，需要这种去耦电容，并为解耦的有源电路提供改进的散热。

12. 发明申请

US20080293242A1 METAL SPACER IN SINGLE AND DUAL DAMASCENE PROCESSING 失效
标题翻译：单金属和双金属加工中的金属间隔
公开(公告)号：US20080293242A1
公开(公告)日：2008-11-27
申请号：US12062612
申请日：2008-04-04
申请人： Edward C. Cooney, III , Robert M. Geffken , Anthony K. Stamper
发明人： Edward C. Cooney, III , Robert M. Geffken , Anthony K. Stamper
IPC分类号： H01L21/768
CPC分类号： H01L21/76843 , H01L21/76808 , H01L21/76811 , H01L21/76865
摘要： A method and structure for a single or dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, patterning the laminated insulator stack, forming vias in the patterned laminated insulator stack, creating sidewall spacers in the bottom portion of the vias, depositing an anti-reflective coating on the sidewall spacers, etching the troughs, removing the anti-reflective coating, depositing a metal layer in the troughs, vias, and sidewall spacers, and applying conductive material in the troughs and the vias. The laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene.
摘要翻译：用于单镶嵌或双镶嵌互连结构的方法和结构包括在衬底上的金属化层中形成布线，在金属化层上形成叠层绝缘体堆叠，在叠层绝缘体堆叠上形成硬掩模，在硬掩模中形成槽，层叠绝缘体堆叠，在图案化的层叠绝缘体堆叠中形成通路，在通孔的底部产生侧壁间隔物，在侧壁间隔物上沉积抗反射涂层，蚀刻槽，去除抗反射涂层，沉积金属槽，通路和侧壁间隔物中的层，以及在槽和通孔中施加导电材料。层压绝缘体堆叠包括还包含氧化物和聚亚芳基的电介质层。

13. 发明授权

US06982227B2 Single and multilevel rework 失效
标题翻译：单层和多层返工
公开(公告)号：US06982227B2
公开(公告)日：2006-01-03
申请号：US10687294
申请日：2003-10-16
申请人： Edward C. Cooney, III , Robert M. Geffken , Vincent J. McGahay , William T. Motsiff , Mark P. Murray , Amanda L. Piper , Anthony K. Stamper , David C. Thomas , Christy S. Tyberg , Elizabeth T. Webster
发明人： Edward C. Cooney, III , Robert M. Geffken , Vincent J. McGahay , William T. Motsiff , Mark P. Murray , Amanda L. Piper , Anthony K. Stamper , David C. Thomas , Christy S. Tyberg , Elizabeth T. Webster
IPC分类号： H01L21/302
CPC分类号： H01L21/76808 , H01L21/76801 , H01L21/76807 , H01L21/76892 , H01L23/525 , H01L23/5329 , H01L23/53295 , H01L2221/1031 , H01L2924/0002 , H01L2924/00
摘要： A method of reworking BEOL (back end of a processing line) metallization levels of damascene metallurgy comprises forming a plurality of BEOL metallization levels over a substrate, forming line and via portions in the BEOL metallization levels, selectively removing at least one of the BEOL metallization levels to expose the line and via portions, and replacing the removed BEOL metallization levels with at least one new BEOL metallization level, wherein the BEOL metallization levels comprise a first dielectric layer and a second dielectric layer, and wherein the first dielectric layer comprising a lower dielectric constant material than the second dielectric layer.
摘要翻译：一种重新加工BEOL（处理线的后端）金刚石冶金的金属化水平的方法包括在衬底上形成多个BEOL金属化水平，在BEOL金属化水平中形成线和通孔部分，选择性地去除BEOL金属化中的至少一个以暴露线路和通孔部分，并且用至少一个新的BEOL金属化水平替换去除的BEOL金属化水平，其中BEOL金属化水平包括第一介电层和第二介电层，并且其中第一介电层包括下部介电常数材料比第二介电层。

14. 发明授权

US06746947B2 Post-fuse blow corrosion prevention structure for copper fuses 有权
标题翻译：铜熔丝保险丝熔断防腐结构
公开(公告)号：US06746947B2
公开(公告)日：2004-06-08
申请号：US10254277
申请日：2002-09-25
申请人： Timothy H. Daubenspeck , Daniel C. Edelstein , Robert M. Geffken , William T. Motsiff , Anthony K. Stamper , Steven H. Voldman
发明人： Timothy H. Daubenspeck , Daniel C. Edelstein , Robert M. Geffken , William T. Motsiff , Anthony K. Stamper , Steven H. Voldman
IPC分类号： H01L2144
CPC分类号： H01L21/76877 , H01L21/76807 , H01L21/76843 , H01L23/5258 , H01L28/20 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A structure and method of fabricating a semiconductor corrosion resistant metal fuse line including a refractory liner which can also act as a resistor is disclosed. Fabrication is accomplished using damascene process. The metal structure can be formed on a semiconductor substrate including a first portion including a first layer and a second layer, the first layer having higher resistivity than the second layer, the second layer having horizontal and vertical surfaces that are in contact with the first layer in the first portion, and a second portion coupled to the first portion, the second portion being comprised of the first layer, the first layer not being in contact with the horizontal and vertical surfaces of the second layer in the second portion. The metal structure can be used as a corrosion resistant fuse. The metal structure can also be used as a resistive element. The high voltage tolerant resistor structure allows for usage in mixed-voltage, and mixed signal and analog/digital applications. The resistor element has low capacitance, low skin effect, high linearity, a high melting temperature, and a high critical current to failure. The resistor structure can be formed on the walls of a dielectric trough. The structure can be applied to circuit applications such as an ESD network, an RC-coupled MOSFET, a resistor ballasted MOSFET and others. The resistors can be in series with the MOSFET or other structures.
摘要翻译：公开了一种制造半导体耐腐蚀金属熔丝线的结构和方法，其包括也可以用作电阻器的耐火衬垫。使用镶嵌工艺完成制作。金属结构可以形成在包括包括第一层和第二层的第一部分的半导体衬底上，第一层具有比第二层更高的电阻率，第二层具有与第一层接触的水平和垂直表面在第一部分中，以及第二部分，其联接到第一部分，第二部分由第一层组成，第一层不与第二部分中的第二层的水平和垂直表面接触。金属结构可用作耐腐蚀保险丝。金属结构也可以用作电阻元件。高耐压电阻器结构允许在混合电压，混合信号和模拟/数字应用中使用。电阻元件具有低电容，低效果，高线性度，高熔点温度和高临界电流故障。电阻器结构可以形成在电介质槽的壁上。该结构可以应用于诸如ESD网络，RC耦合MOSFET，电阻器镇流MOSFET等电路应用。电阻可以与MOSFET或其他结构串联。

15. 发明授权

US06680514B1 Contact capping local interconnect 有权
标题翻译：联系上限本地互连
公开(公告)号：US06680514B1
公开(公告)日：2004-01-20
申请号：US09745047
申请日：2000-12-20
申请人： Robert M. Geffken , David V. Horak , Anthony K. Stamper
发明人： Robert M. Geffken , David V. Horak , Anthony K. Stamper
IPC分类号： H01L2976
CPC分类号： H01L21/76885 , H01L21/2885 , H01L21/76895 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for forming a metallic capping interface between damascene conductive wires/studs and damascene conductive wiring line structures. The method forms a first insulative layer on a substrate layer, followed by forming damascene conductive wires/studs in the first insulative layer. A lower portion of each damascene conductive wire/stud is in contact with an electronic device (e.g., a field effect transistor), or a shallow trench isolation, that is within the substrate layer. A top portion of the first insulative layer is removed, such as by etching, such that an upper portion of the damascene conductive wires/studs remain above the first insulative layer. A metallic capping layer is formed on the upper portions of the damascene conductive wires/studs such that the metallic capping layer is in conductive contact with the damascene conductive wires/studs. Portions of the metallic capping layer between the damascene conductive wires/studs are removed to form a metallic cap on each damascene conductive wire/stud and to conductively isolate one or more of the damascene conductive wires/studs. A portion of the metallic capping layer may be removed from a particular damascene conductive wire/stud such that no metallic capping material remains conductively coupled to the particular damascene conductive wire/stud. A second insulative layer is formed on the first insulative layer such that the second insulative layer covers the metallic caps. Damascene conductive wiring lines are formed within the second insulative layer above the metallic caps and are conductively coupled to the metallic caps.
摘要翻译：用于在镶嵌导电线/螺柱和镶嵌导电布线结构之间形成金属封盖界面的方法和结构。该方法在衬底层上形成第一绝缘层，随后在第一绝缘层中形成镶嵌导电线/螺柱。每个镶嵌导电线/螺柱的下部与衬底层内的电子器件（例如，场效应晶体管）或浅沟槽隔离层接触。去除第一绝缘层的顶部，例如通过蚀刻，使得镶嵌导电线/螺柱的上部保持在第一绝缘层上方。金属盖层形成在镶嵌导电线/螺柱的上部，使得金属覆盖层与镶嵌导电线/螺柱导电接触。去除镶嵌导电线/螺柱之间的金属覆盖层的部分，以在每个镶嵌导电线/柱上形成金属盖，并导电隔离一个或多个镶嵌导电线/螺柱。金属覆盖层的一部分可以从特定的镶嵌导电线/螺柱移除，使得没有金属封盖材料保持与特定的镶嵌导电线/螺柱导电耦合。第二绝缘层形成在第一绝缘层上，使得第二绝缘层覆盖金属盖。大马士革导电布线形成在金属盖上方的第二绝缘层内，并与金属盖导电耦合。

16. 发明授权

US06452251B1 Damascene metal capacitor 有权
标题翻译：大马士革金属电容器
公开(公告)号：US06452251B1
公开(公告)日：2002-09-17
申请号：US09540737
申请日：2000-03-31
申请人： Kerry Bernstein , Robert M. Geffken , Anthony K. Stamper , Stephen A. St. Onge
发明人： Kerry Bernstein , Robert M. Geffken , Anthony K. Stamper , Stephen A. St. Onge
IPC分类号： H01L2900
CPC分类号： H01L23/5223 , H01L21/76877 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A capacitor (60 and 126) fabricated on a semiconductor chip which has a strap contact (41A, 119A) which interconnects the bottom plate (41B, 111A) of the capacitor into the chip circuitry. In one version, an extension of the material making up the bottom plate of the capacitor forms the strap contact. In another version, the capacitor (185) includes a folding of the bottom plate, dielectric layer and top plate to utilize available space and thus increase its capacitance. Several manufacturing methods allow for integration of fabrication of the various versions of the capacitor into a standard dual or single damascene manufacturing process, including a copper damascene process.
摘要翻译：制造在具有将电容器的底板（41B，111A）互连到芯片电路中的带接触（41A，119A）的半导体芯片上制造的电容器（60和126）。在一个版本中，构成电容器底板的材料的延伸形成带接触。在另一版本中，电容器（185）包括底板，电介质层和顶板的折叠，以利用可用空间并因此增加其电容。几种制造方法允许将各种形式的电容器的制造集成到标准的双重或单个镶嵌制造工艺中，包括铜镶嵌工艺。

17. 发明授权

US06426558B1 Metallurgy for semiconductor devices 失效
标题翻译：半导体器件冶金
公开(公告)号：US06426558B1
公开(公告)日：2002-07-30
申请号：US09854890
申请日：2001-05-14
申请人： Jonathan Chapple-Sokol , Paul M. Feeney , Robert M. Geffken , David V. Horak , Mark P. Murray , Anthony K. Stamper
发明人： Jonathan Chapple-Sokol , Paul M. Feeney , Robert M. Geffken , David V. Horak , Mark P. Murray , Anthony K. Stamper
IPC分类号： H01L2348
CPC分类号： H01L23/485 , H01L21/76807 , H01L21/76849 , H01L21/76883 , H01L21/76885 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method and structure is described which improves the manufacturability of integrated circuit interconnect and stud contacts in contact with semiconductor substrates and upper levels of metallization. The monolithic structure is formed from a thick layer of refractory metal. A variation in the monolithic structure is in the use of a dual damascene local interconnect portion of the structure which allows the local interconnect to pass over structures previously formed on the substrate.
摘要翻译：描述了一种方法和结构，其改进了与半导体衬底接触的集成电路互连和螺柱触头的可制造性以及较高级别的金属化。整体结构由难熔金属的厚层形成。整体结构的变化是使用结构的双镶嵌局部互连部分，其允许局部互连通过先前形成在衬底上的结构。

18. 发明授权

US06344373B1 Antifuse structure and process 失效
标题翻译：形成反熔丝的方法
公开(公告)号：US06344373B1
公开(公告)日：2002-02-05
申请号：US09106980
申请日：1998-06-29
申请人： Arup Bhattacharyya , Robert M. Geffken , Chung H. Lam , Robert K. Leidy
发明人： Arup Bhattacharyya , Robert M. Geffken , Chung H. Lam , Robert K. Leidy
IPC分类号： H01L2182
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： According to the preferred embodiment, an antifuse structure and method for personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment antifuse comprises a two layer transformable insulator core between two electrodes. The transformable core is normally non-conductive but can be transformed into a conductive material by supplying a sufficient voltage across the electrodes. The two layer core preferably comprises an injector layer and a dielectric layer. The injector layer preferably comprises a two phase material such as silicon rich nitride or silicon rich oxide. Initially, the injector layer and dielectric layer are non-conductive. When a sufficient voltage is applied the core fuses together and becomes conductive.
摘要翻译：根据优选实施例，提供了克服现有技术限制的用于个性化半导体器件的反熔丝结构和方法。优选的实施例反熔丝包括在两个电极之间的两层可变形的绝缘体芯。可变形的芯通常是非导电的，但是可以通过在电极之间提供足够的电压而将其转变成导电材料。两层芯优选包括注入层和电介质层。注射器层优选地包括两相材料，例如富氮的氮化物或富硅氧化物。最初，喷射器层和电介质层是不导电的。当施加足够的电压时，芯保持在一起并变得导电。

19. 发明授权

US5811870A Antifuse structure 失效
标题翻译：防腐结构
公开(公告)号：US5811870A
公开(公告)日：1998-09-22
申请号：US850033
申请日：1997-05-02
申请人： Arup Bhattacharyya , Robert M. Geffken , Chung H. Lam , Robert K. Leidy
发明人： Arup Bhattacharyya , Robert M. Geffken , Chung H. Lam , Robert K. Leidy
IPC分类号： H01L21/82 , H01L23/525 , H01L29/04
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： According to the preferred embodiment, an antifuse structure and method for personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment antifuse comprises a two layer transformable insulator core between two electrodes. The transformable core is normally non-conductive but can be transformed into a conductive material by supplying a sufficient voltage across the electrodes. The two layer core preferably comprises an injector layer and a dielectric layer. The injector layer preferably comprises a two phase material such as silicon rich nitride or silicon rich oxide. Initially, the injector layer and dielectric layer are non-conductive. When a sufficient voltage is applied the core fuses together and becomes conductive.
摘要翻译：根据优选实施例，提供了克服现有技术限制的用于个性化半导体器件的反熔丝结构和方法。优选的实施例反熔丝包括在两个电极之间的两层可变形的绝缘体芯。可变形的芯通常是非导电的，但是可以通过在电极之间提供足够的电压而将其转变成导电材料。两层芯优选包括注入层和电介质层。注射器层优选地包括两相材料，例如富氮的氮化物或富硅氧化物。最初，喷射器层和电介质层是不导电的。当施加足够的电压时，芯保持在一起并变得导电。

20. 发明授权

US5457345A Metallization composite having nickle intermediate/interface 失效
标题翻译：金属化复合材料具有中间/界面
公开(公告)号：US5457345A
公开(公告)日：1995-10-10
申请号：US182310
申请日：1994-01-14
申请人： Herbert C. Cook , Paul A. Farrar, Sr. , Robert M. Geffken , William T. Motsiff , Adolf E. Wirsing
发明人： Herbert C. Cook , Paul A. Farrar, Sr. , Robert M. Geffken , William T. Motsiff , Adolf E. Wirsing
IPC分类号： H01L21/28 , H01L21/60 , H01L23/485 , H01L29/45 , H01L23/48 , H01L29/46 , H01L29/54 , H01L29/62
CPC分类号： H01L24/11 , H01L24/13 , H01L29/456 , H01L2224/13113 , H01L2224/13116 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01042 , H01L2924/01046 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014
摘要： A metallization composite comprises a refractory metal, nickel, and copper. The refractory metal is preferably titanium (Ti), but other suitable refractory metals such as zirconium and hafnium can also be utilized. An additional optional layer of gold can overlie the copper. The metallization composite is used to connect a solder contact to a semiconductor substrate.
摘要翻译：金属化复合材料包括难熔金属，镍和铜。难熔金属优选为钛（Ti），但也可以使用其它合适的难熔金属如锆和铪。另外一个可选的金层可以覆盖铜。金属化复合材料用于将焊料接触件连接到半导体衬底。

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