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1. 发明授权

US06344373B1 Antifuse structure and process 失效
标题翻译：形成反熔丝的方法
公开(公告)号：US06344373B1
公开(公告)日：2002-02-05
申请号：US09106980
申请日：1998-06-29
申请人： Arup Bhattacharyya , Robert M. Geffken , Chung H. Lam , Robert K. Leidy
发明人： Arup Bhattacharyya , Robert M. Geffken , Chung H. Lam , Robert K. Leidy
IPC分类号： H01L2182
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： According to the preferred embodiment, an antifuse structure and method for personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment antifuse comprises a two layer transformable insulator core between two electrodes. The transformable core is normally non-conductive but can be transformed into a conductive material by supplying a sufficient voltage across the electrodes. The two layer core preferably comprises an injector layer and a dielectric layer. The injector layer preferably comprises a two phase material such as silicon rich nitride or silicon rich oxide. Initially, the injector layer and dielectric layer are non-conductive. When a sufficient voltage is applied the core fuses together and becomes conductive.
摘要翻译：根据优选实施例，提供了克服现有技术限制的用于个性化半导体器件的反熔丝结构和方法。优选的实施例反熔丝包括在两个电极之间的两层可变形的绝缘体芯。可变形的芯通常是非导电的，但是可以通过在电极之间提供足够的电压而将其转变成导电材料。两层芯优选包括注入层和电介质层。注射器层优选地包括两相材料，例如富氮的氮化物或富硅氧化物。最初，喷射器层和电介质层是不导电的。当施加足够的电压时，芯保持在一起并变得导电。

2. 发明授权

US5811870A Antifuse structure 失效
标题翻译：防腐结构
公开(公告)号：US5811870A
公开(公告)日：1998-09-22
申请号：US850033
申请日：1997-05-02
申请人： Arup Bhattacharyya , Robert M. Geffken , Chung H. Lam , Robert K. Leidy
发明人： Arup Bhattacharyya , Robert M. Geffken , Chung H. Lam , Robert K. Leidy
IPC分类号： H01L21/82 , H01L23/525 , H01L29/04
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： According to the preferred embodiment, an antifuse structure and method for personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment antifuse comprises a two layer transformable insulator core between two electrodes. The transformable core is normally non-conductive but can be transformed into a conductive material by supplying a sufficient voltage across the electrodes. The two layer core preferably comprises an injector layer and a dielectric layer. The injector layer preferably comprises a two phase material such as silicon rich nitride or silicon rich oxide. Initially, the injector layer and dielectric layer are non-conductive. When a sufficient voltage is applied the core fuses together and becomes conductive.
摘要翻译：根据优选实施例，提供了克服现有技术限制的用于个性化半导体器件的反熔丝结构和方法。优选的实施例反熔丝包括在两个电极之间的两层可变形的绝缘体芯。可变形的芯通常是非导电的，但是可以通过在电极之间提供足够的电压而将其转变成导电材料。两层芯优选包括注入层和电介质层。注射器层优选地包括两相材料，例如富氮的氮化物或富硅氧化物。最初，喷射器层和电介质层是不导电的。当施加足够的电压时，芯保持在一起并变得导电。

3. 发明授权

US5874778A Embedded power and ground plane structure 失效
标题翻译：嵌入式电源和接地平面结构
公开(公告)号：US5874778A
公开(公告)日：1999-02-23
申请号：US873102
申请日：1997-06-11
申请人： Arup Bhattacharyya , Robert K. Leidy
发明人： Arup Bhattacharyya , Robert K. Leidy
IPC分类号： H01L23/52 , H01L21/3205 , H01L23/528 , H01L23/48
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/3011
摘要： A device architecture with embedded planar conductive ground and power planes in the device architecture. The apparatus includes a first conductive plane, a second conductive plane, a signal plane disposed between the first and second conductive planes, and a logic level disposed adjacent the first conductive plane and connected to the signal plane through at least one via in the conductive plane. The apparatus also includes a built-in alignment scheme. The invention includes a method for making the device and alignment architectures.
摘要翻译：在器件架构中具有嵌入式平面导电接地和电源平面的器件架构。该装置包括第一导电平面，第二导电平面，设置在第一和第二导电平面之间的信号平面以及与第一导电平面相邻设置并通过导电平面中的至少一个通孔连接到信号平面的逻辑电平。该装置还包括内置的对准方案。本发明包括一种用于制造该装置和对准架构的方法。

4. 发明授权

US08802526B2 Methods of forming reverse mode non-volatile memory cell structures 有权
标题翻译：形成反向模式非易失性存储单元结构的方法
公开(公告)号：US08802526B2
公开(公告)日：2014-08-12
申请号：US13409832
申请日：2012-03-01
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： H01L21/336
CPC分类号： H01L29/513 , B82Y10/00 , H01L29/42332 , H01L29/7881 , H01L29/792 , Y10S438/954
摘要： Methods of forming non-volatile memory cell structures are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells that allow for direct tunnel programming and erase, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The low voltage direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and enhancing device lifespan. The low voltage direct tunnel program and erase capability also enables size reduction through low voltage design and further device feature scaling. Such memory cells also allow multiple bit storage. These characteristics allow such memory cells to operate within the definition of a universal memory, capable of replacing both DRAM and ROM in a system.
摘要翻译：描述了形成非易失性存储单元结构的方法，其有助于在反向和正常模式浮动节点存储器单元中使用具有不对称隧道势垒的带隙工程化栅极堆叠，这允许直接隧道编程和擦除，同时保持高电荷阻挡屏障和深载体捕获位点保持良好的电荷。低电压直接隧道编程和擦除能力降低了高能量载流子对栅极堆叠和晶格的损害，减少了写入疲劳和增强了器件寿命。低电压直接隧道编程和擦除功能还可以通过低电压设计和进一步的器件特性缩放来缩小尺寸。这样的存储器单元还允许多个位存储。这些特性允许这样的存储器单元在通用存储器的定义内操作，能够替换系统中的DRAM和ROM。

5. 发明授权

US08557672B2 Dielectrics containing at least one of a refractory metal or a non-refractory metal 有权
$Dielectrics containing at least one of a refractory metal or a non-refractory metal$
公开(公告)号：US08557672B2
公开(公告)日：2013-10-15
申请号：US13368206
申请日：2012-02-07
申请人： Leonard Forbes , Kie Y. Ahn , Arup Bhattacharyya
发明人： Leonard Forbes , Kie Y. Ahn , Arup Bhattacharyya
IPC分类号： H01L21/20
CPC分类号： H01L21/02183 , C23C16/308 , C23C16/45525 , H01L21/02178 , H01L21/02194 , H01L21/02274 , H01L21/0228 , H01L21/02307 , H01L21/28185 , H01L21/28194 , H01L21/28273 , H01L21/3141 , H01L21/3145 , H01L21/31616 , H01L21/31637 , H01L28/60 , H01L28/65 , H01L29/518 , H01L29/7881
摘要： Electronic apparatus and methods of forming the electronic apparatus may include one or more insulator layers having a refractory metal and a non-refractory metal for use in a variety of electronic systems and devices. Embodiments can include electronic apparatus and methods of forming the electronic apparatus having a tantalum aluminum oxynitride film. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film.

6. 发明授权

US08530951B2 Scalable multi-functional and multi-level nano-crystal non-volatile memory device 有权
标题翻译：可扩展的多功能和多级纳米晶体非易失性存储器件
公开(公告)号：US08530951B2
公开(公告)日：2013-09-10
申请号：US13608483
申请日：2012-09-10
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： H01L29/76 , G11C16/04
CPC分类号： H01L29/792 , B82Y10/00 , G11C16/10 , H01L27/115 , H01L29/42332 , H01L29/513
摘要： A multi-functional and multi-level memory cell comprises a tunnel layer formed over a substrate. In one embodiment, the tunnel layer comprises two layers such as HfO2 and LaAlO3. A charge blocking layer is formed over the tunnel layer. In one embodiment, this layer is formed from HfSiON. A control gate is formed over the charge blocking layer. A discrete trapping layer is embedded in either the tunnel layer or the charge blocking layer, depending on the desired level of non-volatility. The closer the discrete trapping layer is formed to the substrate/insulator interface, the lower the non-volatility of the device. The discrete trapping layer is formed from nano-crystals having a uniform size and distribution.
摘要翻译：多功能和多层存储单元包括在衬底上形成的隧道层。在一个实施例中，隧道层包括两层，例如HfO 2和LaAlO 3。在隧道层上形成电荷阻挡层。在一个实施方案中，该层由HfSiON形成。控制栅极形成在电荷阻挡层上。离散的捕获层嵌入在隧道层或电荷阻挡层中，这取决于期望的非挥发性水平。离散捕获层越靠近衬底/绝缘体界面，器件的非易失性越低。离散捕获层由具有均匀尺寸和分布的纳米晶体形成。

7. 发明授权

US08462557B2 Methods of operating memory cell having asymmetric band-gap tunnel insulator using direct tunneling 有权
标题翻译：使用直接隧道操作具有非对称带隙隧道绝缘子的存储单元的方法
公开(公告)号：US08462557B2
公开(公告)日：2013-06-11
申请号：US12941458
申请日：2010-11-08
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： G11C11/34
CPC分类号： H01L29/792 , G11C16/0475 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L29/4232 , H01L29/42336 , H01L29/513 , H01L29/7881
摘要： Methods of operating dual-gate memory cells having asymmetric band-gap tunnel insulators using direct tunneling. The asymmetric band-gap tunnel insulators allow for low voltage direct tunneling programming and efficient erase with holes and/or electrons, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention.
摘要翻译：使用直接隧道操作具有非对称带隙隧道绝缘体的双栅极存储单元的方法。非对称带隙隧道绝缘子允许低电压直接隧道编程和有空和/或电子的有效擦除，同时保持高电荷阻挡屏障和深载流子捕获位点以获得良好的电荷保留。

8. 发明授权

US08399332B2 Lanthanide dielectric with controlled interfaces 有权
公开(公告)号：US08399332B2
公开(公告)日：2013-03-19
申请号：US13430098
申请日：2012-03-26
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： H01L21/20 , H01L21/02
CPC分类号： H01L21/3141 , H01G4/08 , H01L21/28194 , H01L21/316 , H01L28/40 , H01L29/513 , H01L29/517
摘要： Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film.

9. 发明申请

US20130003456A1 SCALABLE MULTI-FUNCTIONAL AND MULTI-LEVEL NANO-CRYSTAL NON-VOLATILE MEMORY DEVICE 有权
标题翻译：可扩展的多功能和多级纳米晶体非易失性存储器件
公开(公告)号：US20130003456A1
公开(公告)日：2013-01-03
申请号：US13608483
申请日：2012-09-10
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： G11C16/10
CPC分类号： H01L29/792 , B82Y10/00 , G11C16/10 , H01L27/115 , H01L29/42332 , H01L29/513
摘要： A multi-functional and multi-level memory cell comprises a tunnel layer formed over a substrate. In one embodiment, the tunnel layer comprises two layers such as HfO2 and LaAlO3. A charge blocking layer is formed over the tunnel layer. In one embodiment, this layer is formed from HfSiON. A control gate is formed over the charge blocking layer. A discrete trapping layer is embedded in either the tunnel layer or the charge blocking layer, depending on the desired level of non-volatility. The closer the discrete trapping layer is formed to the substrate/insulator interface, the lower the non-volatility of the device. The discrete trapping layer is formed from nano-crystals having a uniform size and distribution.
摘要翻译：多功能和多层存储单元包括在衬底上形成的隧道层。在一个实施例中，隧道层包括两层，例如HfO 2和LaAlO 3。在隧道层上形成电荷阻挡层。在一个实施方案中，该层由HfSiON形成。控制栅极形成在电荷阻挡层上。离散的捕获层嵌入在隧道层或电荷阻挡层中，这取决于期望的非挥发性水平。离散捕获层越靠近衬底/绝缘体界面，器件的非易失性越低。离散捕获层由具有均匀尺寸和分布的纳米晶体形成。

10. 发明授权

US08319272B2 Solar cell systems 失效
标题翻译：太阳能电池系统
公开(公告)号：US08319272B2
公开(公告)日：2012-11-27
申请号：US12757870
申请日：2010-04-09
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： H01L29/388 , H01L31/042
CPC分类号： H01L31/022425 , H01L31/0264 , H01L31/062 , H01L31/0725 , H01L31/1085 , Y02E10/50
摘要： The invention includes optoelectronic devices containing one or more layers of semiconductor-enriched insulator (with exemplary semiconductor-enriched insulator being silicon-enriched silicon oxide and silicon-enriched silicon nitride), and includes solar cells containing one or more layers of semiconductor-enriched insulator. The invention also includes methods of forming optoelectronic devices and solar cells.
摘要翻译：本发明包括含有一层或多层半导体富集绝缘体（富含富硅的绝缘体为富硅氧化硅和富含硅的氮化硅）的光电器件，并且包括含有一层或多层半导体富集绝缘体的太阳能电池。本发明还包括形成光电器件和太阳能电池的方法。

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