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11. 发明授权

US06542973B2 Integrated redundancy architecture system for an embedded DRAM 有权
标题翻译：嵌入式DRAM的集成冗余架构系统
公开(公告)号：US06542973B2
公开(公告)日：2003-04-01
申请号：US09898434
申请日：2001-07-03
申请人： Louis L. Hsu , Li-Kong Wang , Toshiaki K. Kirihata , Gregory J. Fredeman
发明人： Louis L. Hsu , Li-Kong Wang , Toshiaki K. Kirihata , Gregory J. Fredeman
IPC分类号： G06F1200
CPC分类号： G11C29/846 , G06F12/0893
摘要： An integrated redundancy eDRAM architecture system for an embedded DRAM macro system having a wide data bandwidth and wide internal bus width is disclosed which provides column and row redundancy for defective columns and rows of the eDRAM macro system. Internally generated column and row addresses of defective columns and rows of each micro-cell block are stored in a memory device, such as a fuse bank, during an eDRAM macro test mode in order for the information to be quickly retrieved during each cycle of eDRAM operation to provide an SRAM-like operation. A column steering circuit steers column redundant elements to replace defective column elements. Redundancy information is either supplied from a SRAM fuse data storage device or from a TAG memory device depending on whether a read or write operation, respectively, is being performed. The integrated redundancy eDRAM architecture system enables data to be sent and received to and from the eDRAM macro system without adding any extra delay to the data flow, thereby protecting data flow pattern integrity.
摘要翻译：公开了一种用于具有宽数据带宽和宽内部总线宽度的嵌入式DRAM宏系统的集成冗余eDRAM架构系统，其为eDRAM宏系统的有缺陷的列和行提供列和行冗余。在eDRAM宏测试模式期间，每个微小区块的有缺陷的列和行的内部生成的列和行地址存储在诸如保险丝库的存储器件中，以便在eDRAM的每个周期期间快速检索信息操作提供类似SRAM的操作。列转向电路引导列冗余元件来替换有缺陷的列元素。根据是否正在执行读取或写入操作，冗余信息是从SRAM熔丝数据存储设备提供的，或者从TAG存储设备提供的。集成冗余eDRAM架构系统使数据能够从eDRAM宏系统发送和接收数据，而不会对数据流增加任何额外的延迟，从而保护数据流模式的完整性。

12. 发明授权

US08324102B2 Techniques for impeding reverse engineering 有权
标题翻译：阻止逆向工程的技术
公开(公告)号：US08324102B2
公开(公告)日：2012-12-04
申请号：US13169248
申请日：2011-06-27
申请人： Louis L. Hsu , Rajiv V. Joshi , David W. Kruger
发明人： Louis L. Hsu , Rajiv V. Joshi , David W. Kruger
IPC分类号： H01L21/00
CPC分类号： H01L21/76816 , H01L21/76825 , H01L21/76831 , H01L21/76834 , H01L23/573 , H01L27/02 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer.
摘要翻译：提供了反逆向工程技术。一方面，提供了一种在绝缘层中形成至少一个特征的方法。该方法包括以下步骤。离子选择性地植入绝缘层中，以在绝缘层内形成至少一个注入区域，所述注入离子被配置为改变通过植入区域内的绝缘层的蚀刻速率。蚀刻绝缘层，同时在植入区域内和植入区域外部形成至少一个空隙，其中通过绝缘层在植入区域内的蚀刻速率与通过绝缘体的蚀刻速率不同在植入区域外侧。空隙填充有至少一种导体材料以在绝缘层中形成特征。

13. 发明申请

US20100201403A1 MULTI-LEVEL POWER SUPPLY SYSTEM FOR A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR 审中-公开
标题翻译：用于补充金属氧化物半导体的多级电源系统
公开(公告)号：US20100201403A1
公开(公告)日：2010-08-12
申请号：US12761872
申请日：2010-04-16
申请人： Rajiv V. Joshi , Louis L. Hsu
发明人： Rajiv V. Joshi , Louis L. Hsu
IPC分类号： H03L5/00 , H02J1/10
CPC分类号： G11C11/4074 , G06F1/26 , G11C5/14 , Y10T307/305
摘要： There is provided a method that includes comparing a voltage level (Vs1) of a lower voltage supply bus to a voltage level (Vs2) of a higher voltage supply bus, and routing current from the lower voltage supply bus to the higher voltage supply bus if Vs2
摘要翻译：提供了一种方法，其包括将较低电压供应总线的电压电平（Vs1）与较高电压电源总线的电压电平（Vs2）进行比较，以及将电流从较低电压供应总线路由到较高电压供应总线，如果 Vs2

14. 发明授权

US06964908B2 Metal-insulator-metal capacitor and method of fabricating same 失效
标题翻译：金属绝缘体金属电容器及其制造方法
公开(公告)号：US06964908B2
公开(公告)日：2005-11-15
申请号：US10643307
申请日：2003-08-19
申请人： Louis L. Hsu , Rajiv V. Joshi , Chun-Yung Sung
发明人： Louis L. Hsu , Rajiv V. Joshi , Chun-Yung Sung
IPC分类号： H01L21/02 , H01L21/768 , H01L23/522 , H01L21/28 , H01L21/308
CPC分类号： H01G4/228 , H01G4/33 , H01L21/768 , H01L23/5223 , H01L28/60 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor including a metal layer, an insulating layer formed on the metal layer, at least a first opening and at least a second opening formed in the first insulating layer, a dielectric layer formed in the first opening, a conductive material deposited in the first and second openings, and a first metal plate formed over the first opening and a second metal plate formed over the second opening. A method for fabricating the MIM capacitor, includes forming the first metal layer, forming the insulating layer on the first metal layer, forming at least the first opening and at least the second opening in the first insulating layer, depositing a mask over the second opening, forming the dielectric layer in the first opening, removing the mask, depositing the conductive material in the first and second openings, and depositing a second metal layer over the first and second openings. MIM capacitors and methods of fabricating same are described, wherein the MIM capacitors are formed simultaneously with the BEOL interconnect and large density MIM capacitors are fabricated at low cost.
摘要翻译：一种金属绝缘体金属（MIM）电容器，包括金属层，形成在金属层上的绝缘层，至少第一开口和形成在第一绝缘层中的至少第二开口，形成在第一开口中的电介质层沉积在第一和第二开口中的导电材料和形成在第一开口上的第一金属板和形成在第二开口上的第二金属板。一种制造MIM电容器的方法，包括形成第一金属层，在第一金属层上形成绝缘层，至少形成第一开口和至少第一绝缘层中的第二开口，在第二开口上沉积掩模在第一开口中形成电介质层，去除掩模，在第一和第二开口中沉积导电材料，并在第一和第二开口上沉积第二金属层。描述MIM电容器及其制造方法，其中MIM电容器与BEOL互连同时形成，并且以低成本制造大密度MIM电容器。

15. 发明授权

US06934182B2 Method to improve cache capacity of SOI and bulk 有权
标题翻译：提高SOI和散货的高速缓存容量的方法
公开(公告)号：US06934182B2
公开(公告)日：2005-08-23
申请号：US10678508
申请日：2003-10-03
申请人： Yuen H. Chan , Louis L. Hsu , Rajiv V. Joshi , Robert Chi-Foon Wong
发明人： Yuen H. Chan , Louis L. Hsu , Rajiv V. Joshi , Robert Chi-Foon Wong
IPC分类号： G11C11/41 , G11C11/00 , G11C11/412 , H01L21/8244 , H01L27/11
CPC分类号： G11C11/412
摘要： Methods for designing a 6T SRAM cell having greater stability and/or a smaller cell size are provided. A 6T SRAM cell has a pair access transistors (NFETs), a pair of pull-up transistors (PFETs), and a pair of pull-down transistors (NFETs), wherein the access transistors have a higher threshold voltage than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic “0” during access of the cell thereby increasing the stability of the cell, especially for cells during “half select.” Further, a channel width of a pull-down transistor can be reduced thereby decreasing the size of a high performance six transistor SRAM cell without effecting cell the stability during access. And, by decreasing the cell size, the overall design layout of a chip may also be decreased.
摘要翻译：提供了设计具有更大稳定性和/或更小单元尺寸的6T SRAM单元的方法。 6T SRAM单元具有一对存取晶体管（NFET），一对上拉晶体管（PFET）和一对下拉晶体管（NFET），其中存取晶体管具有比下拉电阻高的阈值电压晶体管，这使得SRAM单元能够在单元访问期间有效地保持逻辑“0”，从而增加了单元的稳定性，特别是对于“半选择”期间的单元。此外，可以减小下拉晶体管的沟道宽度，从而降低高性能六晶体管SRAM单元的尺寸，而不影响单元在访问期间的稳定性。并且，通过减小单元尺寸，芯片的整体设计布局也可能降低。

16. 发明授权

US06714476B2 Memory array with dual wordline operation 有权
标题翻译：具有双字操作的内存阵列
公开(公告)号：US06714476B2
公开(公告)日：2004-03-30
申请号：US09783918
申请日：2001-02-15
申请人： Louis L. Hsu , Rajiv V. Joshi , Fariborz Assaderaghi
发明人： Louis L. Hsu , Rajiv V. Joshi , Fariborz Assaderaghi
IPC分类号： G11C800
CPC分类号： G11C8/14 , G11C8/10 , G11C11/404 , G11C11/405 , G11C11/4087
摘要： A DRAM array is provided capable of being interchanged between single-cell and twin-cell array operation for storing data in a single-cell or a twin-cell array format, respectively. Preferably, the DRAM array is operated in the single-cell array format during one operating mode and the DRAM array is operated in the twin-cell array format during another operating mode. Wordline decoding circuitry is included for interchanging the DRAM array between single-cell and twin-cell array operation. The wordline decoding circuitry includes a pre-decoder circuit for receiving a control signal and outputting logic outputs to wordline activation circuitry. The wordline activation circuitry then activates at least one wordline traversing the array for interchanging memory cells within the DRAM array between single-cell array operation and twin-cell array operation. Methods are also provided for converting data stored within the DRAM array from the single-cell to the twin-cell array format, and vice versa.
摘要翻译：提供能够在用于以单电池或双电池阵列格式存储数据的单电池和双电池阵列操作之间互换的DRAM阵列。优选地，DRAM阵列在一个操作模式期间以单个单元阵列格式操作，并且DRAM阵列在另一个操作模式期间以双电池阵列格式操作。包括字线解码电路，用于在单电池和双电池阵列操作之间交换DRAM阵列。字线解码电路包括用于接收控制信号并将逻辑输出输出到字线激活电路的预解码器电路。字线激活电路然后激活穿过阵列的至少一个字线，用于在单电池阵列操作和双电池阵列操作之间互换DRAM阵列内的存储器单元。还提供了用于将DRAM阵列中存储的数据从单小区转换为双小区阵列格式的方法，反之亦然。

17. 发明授权

US06549450B1 Method and system for improving the performance on SOI memory arrays in an SRAM architecture system 有权
标题翻译：用于提高SRAM架构系统中SOI存储器阵列性能的方法和系统
公开(公告)号：US06549450B1
公开(公告)日：2003-04-15
申请号：US09708142
申请日：2000-11-08
申请人： Louis L. Hsu , Rajiv V. Joshi , Fariborz Assaderaghi , Mary J. Saccamango
发明人： Louis L. Hsu , Rajiv V. Joshi , Fariborz Assaderaghi , Mary J. Saccamango
IPC分类号： G11C1100
CPC分类号： G11C11/419
摘要： The present invention provides an SOI SRAM architecture system which holds all the bitlines at a lower voltage level, for example, ground, or a fraction of Vdd, during array idle or sleep mode. Preferably, the bitlines are held at a voltage level approximately equal to Vdd minus Vth, where Vth represents the threshold voltage of the transfer devices of the SRAM cells. This prevents the body regions of the transfer devices of each cell of the array from fully charging up, and thus the system avoids the parasitic bipolar leakage current effects attributed to devices fabricated on a partially-depleted SOI substrate. Also, during idle or sleep mode, if all the bitlines are kept at about the Vdd minus Vth voltage level, power consumption by the SRAM architecture system is decreased. This is because the leakage path via one of the transfer gates of all the SRAM cells is greatly minimized. In the SOI SRAM architecture system of the present invention, before the SOI SRAM array is first accessed following the idle or sleep mode, the bitlines are quickly brought up to Vdd. Accordingly, there will not be sufficient time for the SOI body regions of the transfer devices to be charged up. Following access of the array, if the array becomes idle for a period of time, the bitlines are discharged to a lower voltage level again. To realize this, the SOI SRAM architecture system of the present invention includes circuitry for receiving at least one signal indicative of the operating mode of the array and for charging and discharging the array bitlines accordingly.
摘要翻译：本发明提供一种SOI SRAM架构系统，其在阵列空闲或睡眠模式期间将所有位线保持在较低电压电平，例如接地或Vdd的一部分。优选地，位线被保持在大约等于Vdd-Vth的电压电平，其中Vth表示SRAM单元的传送器件的阈值电压。这防止了阵列的每个电池的转移装置的主体区域完全充电，因此系统避免了由部分耗尽的SOI衬底上制造的器件引起的寄生双极泄漏电流效应。而且，在空闲或睡眠模式期间，如果所有位线都保持在Vdd-Vth电压电平左右，则SRAM架构系统的功耗将会降低。这是因为通过所有SRAM单元的传输门之一的泄漏路径被极大地最小化。在本发明的SOI SRAM架构系统中，在空闲或休眠模式之前首先访问SOI SRAM阵列之前，位线被快速地提升到Vdd。因此，传送装置的SOI体区域不会充足的时间。在阵列访问之后，如果阵列空闲一段时间，则位线再次放电到较低的电压电平。为了实现这一点，本发明的SOI SRAM架构系统包括用于接收指示阵列的操作模式的至少一个信号并且相应地对阵列位线进行充电和放电的电路。

18. 发明授权

US06452855B1 DRAM array interchangeable between single-cell and twin-cell array operation 失效
标题翻译： DRAM单元与双电池阵列的操作可互换
公开(公告)号：US06452855B1
公开(公告)日：2002-09-17
申请号：US09755868
申请日：2001-01-05
申请人： Louis L. Hsu , Rajiv V. Joshi , John A. Fifield , Wayne F. Ellis
发明人： Louis L. Hsu , Rajiv V. Joshi , John A. Fifield , Wayne F. Ellis
IPC分类号： H01L27118
CPC分类号： G11C7/1045 , G11C7/1006 , G11C11/4091 , G11C11/4096 , G11C11/4097
摘要： A DRAM array is provided capable of being interchanged between single-cell and twin-cell array operation for storing data in a single-cell or a twin-cell array format, respectively. Preferably, the DRAM array is operated in the single-cell array format during one operating mode and the DRAM array is operated in the twin-cell array format during another operating mode. Switching circuitry is included for interchanging between single-cell and twin-cell array operation, and vice versa. Methods are also provided for converting data stored within the DRAM array from the single-cell to the twin-cell array format, and vice versa.
摘要翻译：提供能够在用于以单电池或双电池阵列格式存储数据的单电池和双电池阵列操作之间互换的DRAM阵列。优选地，DRAM阵列在一个操作模式期间以单个单元阵列格式操作，并且DRAM阵列在另一个操作模式期间以双电池阵列格式操作。包括开关电路用于单电池和双电池阵列操作之间的互换，反之亦然。还提供了用于将DRAM阵列中存储的数据从单小区转换为双小区阵列格式的方法，反之亦然。

19. 发明授权

US06337595B1 Low-power DC voltage generator system 有权
公开(公告)号：US06337595B1
公开(公告)日：2002-01-08
申请号：US09627599
申请日：2000-07-28
申请人： Louis L. Hsu , Rajiv V. Joshi , Russell J. Houghton , Wayne F. Ellis , Jeffrey H. Dreibelbis
发明人： Louis L. Hsu , Rajiv V. Joshi , Russell J. Houghton , Wayne F. Ellis , Jeffrey H. Dreibelbis
IPC分类号： G05F302
CPC分类号： G05F3/265
摘要： A low-voltage, low-power DC voltage generator system is provided having two negative voltage pump circuits for generating voltages for operating negative wordline and substrate bias charge pump circuits, a reference generator for generating a reference voltage, and a two-stage cascaded positive pump system having a first stage pump circuit and a second stage pump circuit. The first stage converts a supply voltage to a higher voltage level, e.g., one volt to 1.5 volts, to be used for I/O drivers, and the second stage converts the output voltage from the first stage to a higher voltage level, e.g., from 1.5 volts to about 2.5 volts, for operating a boost wordline charge pump circuit. The DC voltage generator system further includes a micro pump circuit for providing a voltage level which is greater than one-volt to be used as reference voltages, even when an operating voltage of the DC voltage generator system is at or near one-volt. A one-volt negative voltage pump circuit is also included for pumping the voltages of at least one corresponding charge pump circuit, even when an operating voltage of the DC generator system is at or near one-volt. The DC voltage generator system is specifically designed to be implemented within battery-operated devices having at least one memory unit. The low-power consumption feature of the DC voltage generator system extends battery lifetime and data retention time of the cells of the at least one memory unit.

20. 发明授权

US06323554B1 Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD 失效
$Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD$
标题翻译：使用PVD和CVD形成耐火金属封盖的低电阻率金属导体线和通孔
公开(公告)号：US06323554B1
公开(公告)日：2001-11-27
申请号：US09113916
申请日：1998-07-10
申请人： Rajiv V. Joshi , Jerome J. Cuomo , Hormazdyar M. Dalal , Louis L. Hsu
发明人： Rajiv V. Joshi , Jerome J. Cuomo , Hormazdyar M. Dalal , Louis L. Hsu
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L21/76838 , H01L21/7684 , H01L21/76847 , H01L21/76849 , H01L21/76852 , H01L21/76877 , H01L23/49866 , H01L23/53223 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/09701 , Y10S148/015 , Y10S257/915 , Y10S438/959 , H01L2924/00
摘要： Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH4 to WF6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1 mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1 mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.
摘要翻译：用难熔金属覆盖低电阻率金属导体线或通孔允许有效地使用化学机械抛光技术，因为在化学机械抛光期间难熔金属的硬度降低的磨损性质不会划伤，腐蚀或涂抹。使用低电阻率金属或合金的物理气相沉积（例如，蒸发或准直溅射）以及随后的难熔金属的化学气相沉积（CVD）和随后的平坦化的组合来产生导电线和通孔。在通过CVD施加难熔金属帽时改变SiH4与WF6的比率允许将钨控制并入钨覆盖层中。准直溅射允许在电介质中的开口中形成难熔金属衬垫，其适合作为铜基金属化的扩散阻挡层以及CVD钨。理想地，为了更快地扩散金属如铜，通过两步准直溅射工艺产生衬垫，其中第一层在相对低的真空压力下沉积，其中定向沉积占主导地位（例如，低于1mTorr），并且第二层沉积在较高的散射沉积占主导地位的真空压力（例如高于1mTorr）。对于诸如CVD钨的难熔金属，可以在较高的真空压力下使用准直溅射在一个步骤中创建衬垫。

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