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1. 发明授权

US06542973B2 Integrated redundancy architecture system for an embedded DRAM 有权
标题翻译：嵌入式DRAM的集成冗余架构系统
公开(公告)号：US06542973B2
公开(公告)日：2003-04-01
申请号：US09898434
申请日：2001-07-03
申请人： Louis L. Hsu , Li-Kong Wang , Toshiaki K. Kirihata , Gregory J. Fredeman
发明人： Louis L. Hsu , Li-Kong Wang , Toshiaki K. Kirihata , Gregory J. Fredeman
IPC分类号： G06F1200
CPC分类号： G11C29/846 , G06F12/0893
摘要： An integrated redundancy eDRAM architecture system for an embedded DRAM macro system having a wide data bandwidth and wide internal bus width is disclosed which provides column and row redundancy for defective columns and rows of the eDRAM macro system. Internally generated column and row addresses of defective columns and rows of each micro-cell block are stored in a memory device, such as a fuse bank, during an eDRAM macro test mode in order for the information to be quickly retrieved during each cycle of eDRAM operation to provide an SRAM-like operation. A column steering circuit steers column redundant elements to replace defective column elements. Redundancy information is either supplied from a SRAM fuse data storage device or from a TAG memory device depending on whether a read or write operation, respectively, is being performed. The integrated redundancy eDRAM architecture system enables data to be sent and received to and from the eDRAM macro system without adding any extra delay to the data flow, thereby protecting data flow pattern integrity.
摘要翻译：公开了一种用于具有宽数据带宽和宽内部总线宽度的嵌入式DRAM宏系统的集成冗余eDRAM架构系统，其为eDRAM宏系统的有缺陷的列和行提供列和行冗余。在eDRAM宏测试模式期间，每个微小区块的有缺陷的列和行的内部生成的列和行地址存储在诸如保险丝库的存储器件中，以便在eDRAM的每个周期期间快速检索信息操作提供类似SRAM的操作。列转向电路引导列冗余元件来替换有缺陷的列元素。根据是否正在执行读取或写入操作，冗余信息是从SRAM熔丝数据存储设备提供的，或者从TAG存储设备提供的。集成冗余eDRAM架构系统使数据能够从eDRAM宏系统发送和接收数据，而不会对数据流增加任何额外的延迟，从而保护数据流模式的完整性。

2. 发明授权

US06512683B2 System and method for increasing the speed of memories 有权
标题翻译：提高记忆速度的系统和方法
公开(公告)号：US06512683B2
公开(公告)日：2003-01-28
申请号：US09827071
申请日：2001-04-05
申请人： Louis L. Hsu , Li-Kong Wang , Toshiaki K. Kirihata
发明人： Louis L. Hsu , Li-Kong Wang , Toshiaki K. Kirihata
IPC分类号： G11C1500
CPC分类号： G06F12/0895 , G06F12/0846 , G11C7/1042
摘要： The speed of memories is increased by trading memory density (or area) for speed (or cycle time). An n by n memory array is used to reduce the memory cycle time by 1/n. For example, if an existing memory cycle time is 6 ns, in order to achieve a 3ns (or n=2) cycle time, a 2 by 2 memory array is used. Or, in order to achieve a 1ns cycle time (or n=6), then a 6 by 6 memory array is used.
摘要翻译：通过为速度（或循环时间）交易记忆密度（或面积）来提高记忆速度。 n n存储器阵列用于将存储器周期时间减少1 / n。例如，如果现有存储器周期时间为6ns，为了实现3ns（或n = 2）周期时间，则使用2乘2存储器阵列。或者，为了实现1ns周期时间（或n = 6），则使用6乘6存储器阵列。

3. 发明授权

US06751151B2 Ultra high-speed DDP-SRAM cache 有权
标题翻译：超高速DDP-SRAM缓存
公开(公告)号：US06751151B2
公开(公告)日：2004-06-15
申请号：US09827073
申请日：2001-04-05
申请人： Louis L. Hsu , Toshiaki K. Kirihata , Li-Kong Wang , Robert C. Wong
发明人： Louis L. Hsu , Toshiaki K. Kirihata , Li-Kong Wang , Robert C. Wong
IPC分类号： G11C800
CPC分类号： G06F12/0853 , G11C8/16 , H01L27/1104
摘要： An ultra high-speed DDP-SRAM (Dual Dual-Port Static Random Access Memory) cache having a cache speed in approximately the GHz range. This is accomplished by (1) a specially designed dual-port SRAM whose size is slightly larger than that of a conventional single port SRAM, and (2) the use of a dual dual-port SRAM architecture which doubles its speed by interleaved read and write operations. A first embodiment provides a 6-T (transistor) all nMOS dual-port SRAM cell. A second embodiment provides a dual port 7T-SRAM cell which has only one port for write, and both ports for read.
摘要翻译：具有大约GHz范围内的高速缓存的超高速DDP-SRAM（双重双端口静态随机存取存储器）缓存。这通过（1）专门设计的双端口SRAM（其尺寸略大于常规单端口SRAM）的实现来实现，以及（2）使用双重双端口SRAM架构，其通过交错读取将其速度加倍，写操作。第一实施例提供了6T（晶体管）全部nMOS双端口SRAM单元。第二实施例提供了一个双端口7T-SRAM单元，其仅具有一个用于写入的端口，以及用于读取的两个端口。

4. 发明授权

US06751152B2 Method and configuration to allow a lower wordline boosted voltage operation while increasing a sensing signal with access transistor threshold voltage 失效
标题翻译：方法和配置允许在增加具有存取晶体管阈值电压的感测信号的同时降低字线升压电压操作
公开(公告)号：US06751152B2
公开(公告)日：2004-06-15
申请号：US09999379
申请日：2001-10-31
申请人： Louis L. Hsu , Toshiaki K. Kirihata , Daniel W. Storaska
发明人： Louis L. Hsu , Toshiaki K. Kirihata , Daniel W. Storaska
IPC分类号： G11C800
CPC分类号： G11C11/4085 , G11C7/065 , G11C11/4091
摘要： A memory array architecture employs a full Vdd bitline precharged voltage and a low wordline boost voltage, which is less than Vdd plus the threshold voltage of the access transistor. In a write mode, a first low level of a data bit is almost fully written to a storage element, however a second high level of the data bit is not fully written to the storage element. In a read mode, the first low level of the data bit is fully read out from the storage element, however the second high level of the data bit is not read out by utilizing the access transistor threshold voltage. This allows a sensing signal only with the first voltage level transfer to the Vdd precharged BL. A reference WL is preferably used for generating a reference bitline voltage for a differential Vdd sensing scheme. Alternatively, a single BL digital sensing scheme may be used. Lowering the wordline voltage results in a reduction in power consumption by saving power on Vpp generator and support circuits, and a reduction in the size of the Vpp generator and support circuits, and also eliminates high Vpp voltage related problems such as dielectric breakdown and other reliability concerns while avoiding a complex decoding scheme and saving cost.
摘要翻译：存储器阵列架构采用全Vdd位线预充电电压和低字线升压电压，其小于Vdd加上存取晶体管的阈值电压。在写入模式中，数据位的第一低电平几乎完全写入存储元件，然而数据位的第二高电平未完全写入存储元件。在读取模式下，数据位的第一低电平从存储元件完全读出，然而数据位的第二高电平不通过利用存取晶体管阈值电压被读出。这允许感测信号仅在第一电压电平传输到Vdd预充电BL。参考WL优选地用于产生用于差分Vdd感测方案的参考位线电压。或者，可以使用单个BL数字感测方案。降低字线电压通过节省Vpp发生器和支持电路上的功率以及减小Vpp发生器和支持电路的尺寸而降低功耗，并且消除了与Vpp电压相关的高电压问题，例如介质击穿和其他可靠性同时避免复杂的解码方案并节省成本。

5. 发明授权

US06426914B1 Floating wordline using a dynamic row decoder and bitline VDD precharge 有权
标题翻译：浮动字线使用动态行解码器和位线VDD预充电
公开(公告)号：US06426914B1
公开(公告)日：2002-07-30
申请号：US09839105
申请日：2001-04-20
申请人： Robert H. Dennard , Louis L. Hsu , Toshiaki K. Kirihata
发明人： Robert H. Dennard , Louis L. Hsu , Toshiaki K. Kirihata
IPC分类号： G11C800
CPC分类号： G11C8/08 , G11C7/22 , G11C8/10 , G11C11/4076 , G11C11/4085 , G11C11/4087
摘要： A short cycle DRAM use a floating wordline, dynamic row decoder and bitline VDD precharge, which improves the array efficiency of the short cycle DRAM (3-6 ns) without compromising its performance. A small size wordline driver circuit is provided to reduce the row size of the short cycle DRAM without compromising row access timing. A dynamic decoding operation is implemented which intentionally allows some of the deselected wordlines to float during row access. A Vdd bitline precharge/sensing technique avoids a detrimental (or positive) coupling effect to the floating wordlines during row accessing. A Vdd data-line (or DQ) precharge for a read operation, and control of incoming data timing avoids a detrimental (or positive) coupling effect for a write operation.
摘要翻译：短周期DRAM使用浮动字线，动态行解码器和位线VDD预充电，这提高了短周期DRAM（3-6ns）的阵列效率，而不损害其性能。提供了一种小尺寸字线驱动器电路，以减少短周期DRAM的行大小，而不会影响行访问时序。实现动态解码操作，其有意地允许一些未选择的字线在行访问期间浮动。 Vdd位线预充电/感测技术在行访问期间避免了对浮动字线的有害（或正）耦合效应。用于读取操作的Vdd数据线（或DQ）预充电以及输入数据时序的控制避免了写入操作的有害（或正）耦合效应。

6. 发明授权

US07057866B2 System and method for disconnecting a portion of an integrated circuit 失效
公开(公告)号：US07057866B2
公开(公告)日：2006-06-06
申请号：US09929591
申请日：2001-08-14
申请人： Louis L. Hsu , Rajiv V. Joshi , Chorng-Lii Hwang , Toshiaki K. Kirihata , Paul C. Parries
发明人： Louis L. Hsu , Rajiv V. Joshi , Chorng-Lii Hwang , Toshiaki K. Kirihata , Paul C. Parries
IPC分类号： G11C8/00
CPC分类号： G11C5/14 , G11C5/147
摘要： An integrated circuit system having a plurality of macros is provided. The integrated circuit system includes an external voltage supply input configured for supplying an external voltage to the integrated circuit; and a plurality of internal voltage supply generators, each of the plurality of internal voltage supply generators being connected to a respective macro of the plurality of macros and configured for receiving the external voltage via the external voltage supply input for generating an internal voltage supply for operating its respective macro. Each of the plurality of internal voltage supply generators includes circuitry for generating the internal voltage supply and circuitry for disconnecting at least a portion of its respective macro. The integrated circuit system can be applied to a semiconductor chip to save active or stand-by power. It can also be used to disconnect a defective portion of the chip and optionally replace it with a non-defective portion of the chip.

7. 发明授权

US07774660B2 Flexible row redundancy system 失效
标题翻译：灵活的行冗余系统
公开(公告)号：US07774660B2
公开(公告)日：2010-08-10
申请号：US12131307
申请日：2008-06-02
申请人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
发明人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
IPC分类号： G11C29/00
CPC分类号： G11C29/808
摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.
摘要翻译：提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 其中所述复制逻辑模块被编程为根据可选择的修复字段大小将所述至少一个故障地址复制到对应于预定数量的存储体的行熔丝阵列中的行熔丝信息。

8. 发明申请

US20080229144A1 FLEXIBLE ROW REDUNDANCY SYSTEM 失效
标题翻译：灵活的冗余系统
公开(公告)号：US20080229144A1
公开(公告)日：2008-09-18
申请号：US12131307
申请日：2008-06-02
申请人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
发明人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
IPC分类号： G06F11/00
CPC分类号： G11C29/808
摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.
摘要翻译：提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 其中所述复制逻辑模块被编程为根据可选择的修复字段大小将所述至少一个故障地址复制到对应于预定数量的存储体的行熔丝阵列中的行熔丝信息。

9. 发明授权

US06445626B1 Column redundancy architecture system for an embedded DRAM 失效
标题翻译：用于嵌入式DRAM的列冗余架构系统
公开(公告)号：US06445626B1
公开(公告)日：2002-09-03
申请号：US09821443
申请日：2001-03-29
申请人： Louis L. Hsu , Rajiv V. Joshi , Gregory J. Fredeman
发明人： Louis L. Hsu , Rajiv V. Joshi , Gregory J. Fredeman
IPC分类号： G11C700
CPC分类号： G11C29/848 , G11C29/846 , G11C2207/104
摘要： A column redundancy architecture system for an embedded DRAM (eDRAM) having a wide data bandwidth and wide internal bus width is disclosed which provides column redundancy to defective datalines of the eDRAM. Internally generated column addresses of defective columns of each micro cell block are stored in a memory device during eDRAM array testing. Two redundancy reroute mechanisms are disclosed. The first redundancy reroute mechanism selects at least one defective dataline of the eDRAM and directly replaces the defective dataline(s) with at least one redundancy dataline. The second redundancy reroute mechanism discards the defective dataline column and replaces it with an adjacent dataline column. The dataline columns following the defective dataline column are then replaced with the next adjacent dataline columns including a redundancy dataline column.
摘要翻译：公开了一种具有宽数据带宽和宽内部总线宽度的嵌入式DRAM（eDRAM）的列冗余架构系统，其为eDRAM的缺陷数据库提供列冗余。在eDRAM阵列测试期间，每个微单元块的内部生成的列地址存储在存储器件中。公开了两种冗余重路由机制。第一个冗余重路由机制选择eDRAM的至少一个有缺陷的数据库，并用至少一个冗余数据线直接替换有缺陷的数据库。第二个冗余重路由机制丢弃有缺陷的数据列，并用相邻的数据列替换它。随后，数据线列中的数据栏将被替换为包含冗余数据列的下一个相邻的数据列。

10. 发明授权

US07404113B2 Flexible row redundancy system 有权
标题翻译：灵活的行冗余系统
公开(公告)号：US07404113B2
公开(公告)日：2008-07-22
申请号：US11031138
申请日：2005-01-07
申请人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
发明人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
IPC分类号： G11C29/00
CPC分类号： G11C29/808
摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.
摘要翻译：提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 复制逻辑模块被编程为根据可选择的修复字段大小将至少一个故障地址复制到存储在对应于预定数量的存储体的行熔丝阵列中的行熔丝信息中。

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