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1. 发明申请

US20120008379A1 GLOBAL BIT LINE RESTORE BY MOST SIGNIFICANT BIT OF AN ADDRESS LINE 失效
标题翻译：全球位线由地址线最重要的位复原
公开(公告)号：US20120008379A1
公开(公告)日：2012-01-12
申请号：US13179684
申请日：2011-07-11
申请人： Yuen H. CHAN , Michael KUGEL , Raphael POLIG , Tobias T. WERNER
发明人： Yuen H. CHAN , Michael KUGEL , Raphael POLIG , Tobias T. WERNER
IPC分类号： G11C11/00 , G11C7/12
CPC分类号： G11C11/419 , G11C7/12
摘要： An SRAM circuitry having SRAM cells for storing at least one data word of a length of at least one bit is provided. Each bit of the data words is stored in an assigned SRAM cell, wherein the SRAM circuitry comprises address lines for addressing the at least one data word, a decoding unit for decoding the address signals on the address lines to generate a word line signals on a word line per addressed word, a local bit line to be coupled to SRAM cells of different data words with different addresses, a global bit line to be coupled to the local bit line, and a global bit line restore unit for pre-charging the global bit line. The global bit line restore unit is configured for being triggered by a trigger signal based on the address signal of one of the decoded address lines.
摘要翻译：提供具有用于存储至少一个长度为至少一位的至少一个数据字的SRAM单元的SRAM电路。数据字的每一位被存储在分配的SRAM单元中，其中SRAM电路包括用于寻址至少一个数据字的地址线，解码单元，用于对地址线上的地址信号进行解码，以产生一个字线信号每个寻址字的字线，要耦合到具有不同地址的不同数据字的SRAM单元的局部位线，要耦合到本地位线的全局位线，以及用于对全局进行预充电的全局位线恢复单元位线。全局位线恢复单元被配置为基于解码的地址线之一的地址信号由触发信号触发。

2. 发明申请

US20110304370A1 PROGRAMMABLE CONTROL CLOCK CIRCUIT INCLUDING SCAN MODE 失效
标题翻译：可编程控制时钟电路，包括扫描模式
公开(公告)号：US20110304370A1
公开(公告)日：2011-12-15
申请号：US12796970
申请日：2010-06-09
申请人： Paul A. Bunce , Yuen H. Chan , John D. Davis , Richard E. Serton
发明人： Paul A. Bunce , Yuen H. Chan , John D. Davis , Richard E. Serton
IPC分类号： H03K5/04
CPC分类号： H03K5/156
摘要： A programmable clock control circuit includes a base block configured to control operation of the programmable clock control circuit and a chop block configured to control the width of an output clock signal of the programmable clock control circuit. The circuit also includes a pulse width variation block providing a pulse width variation output to the base block, the base block output being variable to provide at least three different output pulse widths. The circuit also includes a launch clock delay block coupled to delay the output of the base block and a scan clock delay block to delay the output pulse and a selector that causes either the scan clock delay block or the launch clock delay block to be active based on a value of a scan gate signal.
摘要翻译：可编程时钟控制电路包括被配置为控制可编程时钟控制电路的操作的基本块和被配置为控制可编程时钟控制电路的输出时钟信号的宽度的斩波块。电路还包括提供脉冲宽度变化输出到基本块的脉冲宽度变化块，基本块输出是可变的以提供至少三个不同的输出脉冲宽度。电路还包括发射时钟延迟块，其耦合以延迟基本块的输出和延迟输出脉冲的扫描时钟延迟块和使得扫描时钟延迟块或启动时钟延迟块基于有源的选择器对扫描门信号的值。

3. 发明授权

US07787284B2 Integrated circuit chip with improved array stability 有权
标题翻译：集成电路芯片具有改进的阵列稳定性
公开(公告)号：US07787284B2
公开(公告)日：2010-08-31
申请号：US12133450
申请日：2008-06-05
申请人： Yuen H. Chan , Rajiv V. Joshi , Donald W. Plass
发明人： Yuen H. Chan , Rajiv V. Joshi , Donald W. Plass
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C8/08 , G11C11/412 , G11C11/417
摘要： A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g., in the data path and in non-critical logic, are tailored for lower gate and subthreshold leakage. Normal base FETs have a base threshold and tailored FETs have a threshold above. In a multi-supply chip, circuits with tailored FETs are powered by an increased supply voltage.
摘要翻译：可以由多个电源提供的多阈值集成电路（IC），具有诸如阵列静态随机存取存储器（SRAM）单元的锁存器阵列和具有改进的稳定性和减小的亚阈值泄漏的CMOS SRAM。阵列单元中的选定器件（NFET和/或PFET）和支持逻辑，例如在数据通路和非关键逻辑中，都适用于较低的栅极和亚阈值泄漏。正常基极FET具有基极阈值，并且定制的FET具有高于阈值。在多电源芯片中，具有定制FET的电路由增加的电源电压供电。

4. 发明申请

US20080270864A1 DIFFERENCE SIGNAL PATH TEST AND CHARACTERIZATION CIRCUIT 审中-公开
标题翻译：差分信号路径测试和特征电路
公开(公告)号：US20080270864A1
公开(公告)日：2008-10-30
申请号：US12169664
申请日：2008-07-09
申请人： Yuen H. Chan , Rajiv V. Joshi
发明人： Yuen H. Chan , Rajiv V. Joshi
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The programmable voltage divider develops a signal with a selected polarity and magnitude that is provided to a sense amplifier being tested. The sense amplifier is set and its output latched. The latch contents are checked against an expected value. The difference voltage may be changed and the path retested to find passing and failing points.
摘要翻译：可以在测试电路中使用的测试电路和可编程分压器。可编程分压器产生可以数字选择的电压差信号。测试电路可用于测试和表征读出放大器。可编程分压器产生具有所选极性和幅度的信号，该极性和幅度被提供给被测试的读出放大器。读出放大器设置并输出锁存。根据预期值检查锁存内容。可以改变差值电压，重新测试路径以找到通过点和故障点。

5. 发明申请

US20080203980A1 PROGRAMMABLE VOLTAGE DIVIDER 有权
标题翻译：可编程电压分频器
公开(公告)号：US20080203980A1
公开(公告)日：2008-08-28
申请号：US12114853
申请日：2008-05-05
申请人： Yuen H. Chan , Rajiv V. Joshi
发明人： Yuen H. Chan , Rajiv V. Joshi
IPC分类号： G05F1/652
CPC分类号： G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The programmable voltage divider develops a signal with a selected polarity and magnitude that is provided to a sense amplifier being tested. The sense amplifier is set and its output latched. The latch contents are checked against an expected value. The difference voltage may be changed and the path retested to find passing and failing points.
摘要翻译：可以在测试电路中使用的测试电路和可编程分压器。可编程分压器产生可以数字选择的电压差信号。测试电路可用于测试和表征读出放大器。可编程分压器产生具有所选极性和幅度的信号，该极性和幅度被提供给被测试的读出放大器。读出放大器设置并输出锁存。根据预期值检查锁存内容。可以改变差值电压，重新测试路径以找到通过点和故障点。

6. 发明申请

US20080141061A1 PROGRAMMABLE LOCAL CLOCK BUFFER CAPABLE OF VARYING INITIAL SETTINGS 有权
标题翻译：可编程本地时钟缓冲器可以改变初始设置
公开(公告)号：US20080141061A1
公开(公告)日：2008-06-12
申请号：US11609403
申请日：2006-12-12
申请人： Yuen H. Chan , Michael J. Lee
发明人： Yuen H. Chan , Michael J. Lee
IPC分类号： G06F1/00
CPC分类号： G06F1/10
摘要： A programmable local clock buffer for integrated circuit devices which is capable of varying initial settings is provided. The illustrative embodiments allow a single type of local clock buffer (LCB) to be used throughout an integrated circuit design while still being able to provide differing initial offsets and pulse widths for different local circuitry portions of the integrated circuit design. Delay circuit paths are provided, which provide discreet delay values, within the LCB that can be chained together when the LCB is instantiated to set the initial offset and pulse width values. When an LCB is instantiated in the integrated circuit device design, various ones of the delay circuit paths are connected together with the existing circuit paths of the LCB, i.e. the circuit paths that provide the pre-established offset and pulse width values, in order to set the initial offset and pulse width values for the LCB.
摘要翻译：提供了一种能够改变初始设置的集成电路设备的可编程本地时钟缓冲器。说明性实施例允许在整个集成电路设计中使用单一类型的本地时钟缓冲器（LCB），同时仍然能够为集成电路设计的不同本地电路部分提供不同的初始偏移和脉冲宽度。提供延迟电路路径，其提供LCB内的谨慎延迟值，当LCB被实例化以设置初始偏移和脉冲宽度值时，可以将其链接在一起。当在集成电路器件设计中实例化LCB时，各种延迟电路路径与LCB的现有电路路径（即提供预先建立的偏移和脉冲宽度值的电路）连接在一起，以便设置LCB的初始偏移和脉冲宽度值。

7. 发明授权

US07336546B2 Global bit select circuit with dual read and write bit line pairs 失效
标题翻译：具有双读和写位线对的全局位选择电路
公开(公告)号：US07336546B2
公开(公告)日：2008-02-26
申请号：US11054309
申请日：2005-02-09
申请人： Yuen H. Chan , Ryan T. Freese , Antonio R. Pelella , Arthur D. Tuminaro
发明人： Yuen H. Chan , Ryan T. Freese , Antonio R. Pelella , Arthur D. Tuminaro
IPC分类号： G11C7/00
CPC分类号： G11C11/413
摘要： A domino SRAM global bit select circuit provides an interface between dual global read and write bit line pairs to a “local bit select” circuit.
摘要翻译：多米诺SRAM全局位选择电路提供了双局域读和写位线对之间的接口到“本地位选择”电路。

8. 发明授权

US07295458B2 Eight transistor SRAM cell with improved stability requiring only one word line 有权
公开(公告)号：US07295458B2
公开(公告)日：2007-11-13
申请号：US11334647
申请日：2006-01-18
申请人： Yuen H. Chan , William V. Huott , Donald W. Plass
发明人： Yuen H. Chan , William V. Huott , Donald W. Plass
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C8/14
摘要： An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs for a write operation, and a single read bit line transistor in series with the word line transistor, when selected, reads the content of the cell.

9. 发明授权

US06990038B1 Clock driver and boundary latch for a multi-port SRAM 失效
标题翻译：多端口SRAM的时钟驱动器和边界锁存器
公开(公告)号：US06990038B1
公开(公告)日：2006-01-24
申请号：US11056803
申请日：2005-02-11
申请人： Yuen H. Chan , Timothy J. Charest , Rajiv V. Joshi , Rolf Sautter
发明人： Yuen H. Chan , Timothy J. Charest , Rajiv V. Joshi , Rolf Sautter
IPC分类号： G11C8/00
CPC分类号： G11C29/12015 , G11C8/16 , G11C11/41 , G11C11/417 , G11C29/32 , G11C2029/3202
摘要： A multi-port (e.g., two port) CMOS static random access memory (SRAM) with a local clock driver generating clocks for boundary latches. Local clocks select between address inputs clocked into the boundary latches. A read clock selects and latches a read address in the boundary latches. A second clock latches write addresses and, when appropriate, test data addresses.
摘要翻译：具有为边界锁存器产生时钟的本地时钟驱动器的多端口（例如，两端口）CMOS静态随机存取存储器（SRAM）。本地时钟选择时钟输入边界锁存器的地址输入。读取时钟选择并锁存边界锁存器中的读取地址。第二个时钟锁存写入地址，并在适当时锁定测试数据地址。

10. 发明授权

US5315167A Voltage burn-in scheme for BICMOS circuits 失效
标题翻译： BICMOS电路的电压老化方案
公开(公告)号：US5315167A
公开(公告)日：1994-05-24
申请号：US865591
申请日：1992-04-09
申请人： Yuen H. Chan , Anthony R. Pelella , William R. Reohr
发明人： Yuen H. Chan , Anthony R. Pelella , William R. Reohr
IPC分类号： G01R31/26 , G01R31/28 , H01L21/326 , H01L21/822 , H01L27/04 , H03K17/16
CPC分类号： G01R31/2642
摘要： A switchable voltage generator is provided on-chip together with circuitry including transistors formed in accordance with several different technologies and optimized for operation at different voltages. Provision of a voltage generator on the chip avoids the need for dedicated connections for the lower voltage or voltages. To provide similar levels of burn-in voltage to the different transistor types, a bypass or shunt is provided across the regulator of the voltage generator. The on-chip voltage generator avoids the requirement for a large number of chip or module power connections for each supply voltage required in order to meet current requirements of different portions of chip circuitry. The use of a mode select receiver also avoids the requirement of additional connections to the chip. The combination of one or more switchable voltage generators with a mode select receiver allows economical and efficient electrically stressed testing of the chip at different levels of manufacture.
摘要翻译：可切换电压发生器与芯片一起提供，其中包括根据若干不同技术形成的晶体管，并针对在不同电压下工作进行了优化。在芯片上提供电压发生器避免了对于较低电压或电压的专用连接的需要。为了向不同的晶体管类型提供类似级别的老化电压，在电压发生器的调节器之间提供旁路或并联。片内电压发生器避免了为满足芯片电路不同部分的电流要求而需要的每个电源电压需要大量的芯片或模块电源连接。使用模式选择接收机也避免了对芯片的附加连接的要求。一个或多个可切换电压发生器与模式选择接收器的组合允许在不同制造水平下对芯片进行经济且有效的电应力测试。

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