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1. 发明授权

US06934182B2 Method to improve cache capacity of SOI and bulk 有权
标题翻译：提高SOI和散货的高速缓存容量的方法
公开(公告)号：US06934182B2
公开(公告)日：2005-08-23
申请号：US10678508
申请日：2003-10-03
申请人： Yuen H. Chan , Louis L. Hsu , Rajiv V. Joshi , Robert Chi-Foon Wong
发明人： Yuen H. Chan , Louis L. Hsu , Rajiv V. Joshi , Robert Chi-Foon Wong
IPC分类号： G11C11/41 , G11C11/00 , G11C11/412 , H01L21/8244 , H01L27/11
CPC分类号： G11C11/412
摘要： Methods for designing a 6T SRAM cell having greater stability and/or a smaller cell size are provided. A 6T SRAM cell has a pair access transistors (NFETs), a pair of pull-up transistors (PFETs), and a pair of pull-down transistors (NFETs), wherein the access transistors have a higher threshold voltage than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic “0” during access of the cell thereby increasing the stability of the cell, especially for cells during “half select.” Further, a channel width of a pull-down transistor can be reduced thereby decreasing the size of a high performance six transistor SRAM cell without effecting cell the stability during access. And, by decreasing the cell size, the overall design layout of a chip may also be decreased.
摘要翻译：提供了设计具有更大稳定性和/或更小单元尺寸的6T SRAM单元的方法。 6T SRAM单元具有一对存取晶体管（NFET），一对上拉晶体管（PFET）和一对下拉晶体管（NFET），其中存取晶体管具有比下拉电阻高的阈值电压晶体管，这使得SRAM单元能够在单元访问期间有效地保持逻辑“0”，从而增加了单元的稳定性，特别是对于“半选择”期间的单元。此外，可以减小下拉晶体管的沟道宽度，从而降低高性能六晶体管SRAM单元的尺寸，而不影响单元在访问期间的稳定性。并且，通过减小单元尺寸，芯片的整体设计布局也可能降低。

2. 发明授权

US5666320A Storage system 失效
标题翻译：存储系统
公开(公告)号：US5666320A
公开(公告)日：1997-09-09
申请号：US575428
申请日：1995-12-20
申请人： Robert Chi-Foon Wong , Taqi Nasser Buti , Seiki Ogura
发明人： Robert Chi-Foon Wong , Taqi Nasser Buti , Seiki Ogura
IPC分类号： G11C7/06 , G11C11/00 , G11C7/00
CPC分类号： G11C7/062
摘要： An improved storage system for use with computers. The system includes a memory array bifurcated into a first and second array segment and a differential sense amplifier configured for selective operation in a first mode establishing one array segment as a reference load and the other array segment as a dynamic load, and a second mode establishing the other array segment as a reference load and the one array segment as a dynamic load. The amplifier senses changes in a parameter in the dynamic load with respect to the reference load.
摘要翻译：用于计算机的改进的存储系统。该系统包括分为第一和第二阵列段的存储器阵列和配置用于以第一模式选择性操作的差分读出放大器，该第一模式建立一个阵列段作为参考负载，另一阵列段作为动态负载，以及第二模式建立另一个数组段作为参考负载，一个数组段作为动态负载。放大器感测相对于参考负载的动态负载中的参数的变化。

3. 发明授权

US08531907B2 Semiconductor memory device and method 有权
标题翻译：半导体存储器件及方法
公开(公告)号：US08531907B2
公开(公告)日：2013-09-10
申请号：US13016798
申请日：2011-01-28
申请人： Martin Ostermayr , Robert Chi-Foon Wong
发明人： Martin Ostermayr , Robert Chi-Foon Wong
IPC分类号： G11C8/00 , G11C7/00
CPC分类号： G11C11/412
摘要： In an embodiment, a method of operating a memory cell coupled to a first port and to a second port includes determining if a first port is requesting to access the memory cell and determining if a second port is requesting to access the memory cell. Based on the determining, if the first port and the second port are simultaneously requesting to access the memory cell, the second port is deactivated, the memory cell is accessed from the first port, and an accessed memory state is propagated from the first port to circuitry associated with the second port.
摘要翻译：在一个实施例中，操作耦合到第一端口和第二端口的存储器单元的方法包括确定第一端口是否请求访问存储器单元并且确定第二端口是否请求访问存储器单元。基于确定，如果第一端口和第二端口同时请求访问存储器单元，则停用第二端口，从第一端口访问存储器单元，并且将访问的存储器状态从第一端口传播到与第二个端口相关联的电路。

4. 发明授权

US06986078B2 Optimization of storage and power consumption with soft error predictor-corrector 失效
标题翻译：使用软错误预测器校正器优化存储和功耗
公开(公告)号：US06986078B2
公开(公告)日：2006-01-10
申请号：US10213690
申请日：2002-08-07
申请人： Kenneth P. Rodbell , Henry H. K. Tang , Robert M. Trepp , Robert Chi-Foon Wong
发明人： Kenneth P. Rodbell , Henry H. K. Tang , Robert M. Trepp , Robert Chi-Foon Wong
IPC分类号： G06F11/00
CPC分类号： H04L1/0001
摘要： A method and system for mitigating the impact of radiation induced in a data processor incorporating integrated circuits. The method comprises the steps of determining the location of the data processor, determining a set of radiation sources and intensities at that location, and estimating the soft error rate of the data processor as a function of the determined radiation intensities and geometric characteristics of said integrated circuits to provide an estimate value. The data processor is modified (either hardware or software) in response to the estimate value at times the estimate value exceeds a predetermined value.
摘要翻译：一种用于减轻包含集成电路的数据处理器中引起的辐射影响的方法和系统。该方法包括以下步骤：确定数据处理器的位置，确定该位置处的一组辐射源和强度，以及根据确定的所述集成的辐射强度和几何特性来估计数据处理器的软错误率电路提供估计值。数据处理器在估计值超过预定值的时候响应于估计值被修改（硬件或软件）。

5. 发明申请

US20120195151A1 Semiconductor Memory Device and Method 有权
标题翻译：半导体存储器件和方法
公开(公告)号：US20120195151A1
公开(公告)日：2012-08-02
申请号：US13016798
申请日：2011-01-28
申请人： Martin Ostermayr , Robert Chi-Foon Wong
发明人： Martin Ostermayr , Robert Chi-Foon Wong
IPC分类号： G11C8/16
CPC分类号： G11C11/412
摘要： In an embodiment, a method of operating a memory cell coupled to a first port and to a second port includes determining if a first port is requesting to access the memory cell and determining if a second port is requesting to access the memory cell. Based on the determining, if the first port and the second port are simultaneously requesting to access the memory cell, the second port is deactivated, the memory cell is accessed from the first port, and an accessed memory state is propagated from the first port to circuitry associated with the second port.
摘要翻译：在一个实施例中，操作耦合到第一端口和第二端口的存储器单元的方法包括确定第一端口是否请求访问存储器单元并且确定第二端口是否请求访问存储器单元。基于确定，如果第一端口和第二端口同时请求访问存储器单元，则停用第二端口，从第一端口访问存储器单元，并且将访问的存储器状态从第一端口传播到与第二个端口相关联的电路。

6. 发明授权

US5661684A Differential sense amplifier 失效
标题翻译：差分放大器
公开(公告)号：US5661684A
公开(公告)日：1997-08-26
申请号：US577177
申请日：1995-12-22
申请人： Robert Chi-Foon Wong , Taqi Nasser Buti , Seiki Ogura
发明人： Robert Chi-Foon Wong , Taqi Nasser Buti , Seiki Ogura
IPC分类号： G11C7/06 , G11C11/34 , G11C7/02
CPC分类号： G11C7/065
摘要： An improved differential sense amplifier for sensing differences in a parameter at a first locus coupled with a first signal source and a second locus coupled with a second signal source. The sensing is effected by a first sensing element coupled with the first locus and a second sensing element coupled with the second locus. The improvement comprises the first sensing element and the second sensing element having differing sensitivities. In the preferred embodiment of the invention, the sensing elements are field effect transistors, and the sensitivity is established by a threshold voltage characteristic. Preferably, the first signal source provides a dynamic signal to be measured and the second signal source provides a reference signal against which the dynamic signal's changes are compared.
摘要翻译：一种改进的差分读出放大器，用于感测与第一信号源耦合的第一轨迹处的参数和与第二信号源耦合的第二轨迹的差异。感测由与第一轨迹耦合的第一感测元件和与第二轨迹耦合的第二感测元件实现。该改进包括具有不同灵敏度的第一感测元件和第二感测元件。在本发明的优选实施例中，感测元件是场效应晶体管，并且灵敏度由阈值电压特性建立。优选地，第一信号源提供待测量的动态信号，并且第二信号源提供参考信号，对比参考信号对动态信号的变化进行比较。

7. 发明授权

US07542330B2 SRAM with asymmetrical pass gates 失效
标题翻译：具有不对称传递门的SRAM
公开(公告)号：US07542330B2
公开(公告)日：2009-06-02
申请号：US11763555
申请日：2007-06-15
申请人： Brian Joseph Greene , Chun-Yung Sung , Clement Wann , Robert Chi-Foon Wong , Ying Zhang
发明人： Brian Joseph Greene , Chun-Yung Sung , Clement Wann , Robert Chi-Foon Wong , Ying Zhang
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： An SRAM having asymmetrical FET pass gates and a method of fabricating an SRAM having asymmetrical FET pass gates. The pass gates are asymmetrical with respect to current conduction from the drain to the source of the pass gate being different from current conduction from the source to the drain of the pass gate.
摘要翻译：具有不对称FET通孔的SRAM和制造具有不对称FET通孔的SRAM的方法。相对于从栅极的漏极到源极的电流传导，通路门不对称，不同于从通过栅极的源极到漏极的电流传导。

8. 发明申请

US20080310212A1 SRAM WITH ASYMMETRICAL PASS GATES 失效
标题翻译：带不对称门的SRAM
公开(公告)号：US20080310212A1
公开(公告)日：2008-12-18
申请号：US11763555
申请日：2007-06-15
申请人： Brian Joseph Greene , Chun-Yung Sung , Clement Wann , Robert Chi-Foon Wong , Ying Zhang
发明人： Brian Joseph Greene , Chun-Yung Sung , Clement Wann , Robert Chi-Foon Wong , Ying Zhang
IPC分类号： G11C11/40
CPC分类号： G11C11/412
摘要： An SRAM having asymmetrical FET pass gates and a method of fabricating an SRAM having asymmetrical FET pass gates. The pass gates are asymmetrical with respect to current conduction from the drain to the source of the pass gate being different from current conduction from the source to the drain of the pass gate.
摘要翻译：具有不对称FET通孔的SRAM和制造具有不对称FET通孔的SRAM的方法。相对于从栅极的漏极到源极的电流传导，通路门不对称，不同于从通过栅极的源极到漏极的电流传导。

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