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11. 发明申请

US20050070041A1 Atomic layer deposition (ALD) method with enhanced deposition rate 有权
标题翻译：原子层沉积（ALD）方法具有提高的沉积速率
公开(公告)号：US20050070041A1
公开(公告)日：2005-03-31
申请号：US10672778
申请日：2003-09-26
申请人： Chih-Ta Wu , Kuo-Yin Lin , Chia-Shiung Tsai
发明人： Chih-Ta Wu , Kuo-Yin Lin , Chia-Shiung Tsai
IPC分类号： H01L21/00 , H01L21/314
CPC分类号： H01L21/0228 , C23C16/45527 , H01L21/3141
摘要： An atomic layer deposition method for forming a microelectronic layer employs a reactor chamber pressure of greater than about 500 mtorr and more preferably from about 20 to about 50 torr. By employing a reactor chamber pressure within the foregoing range, the microelectronic layer is formed with an enhanced deposition rate while employing the atomic layer deposition method, due to a gas phase chemical vapor deposition component to the atomic layer deposition method.
摘要翻译：用于形成微电子层的原子层沉积方法采用的反应器室压力大于约500mtorr，更优选为约20至约50托。通过采用上述范围内的反应室压力，由于采用原子层沉积方法的气相化学气相沉积成分，由于采用原子层沉积法，所以微电子层以增加的沉积速率形成。

12. 发明授权

US06803291B1 Method to preserve alignment mark optical integrity 有权
标题翻译：保持对准标记光学完整性的方法
公开(公告)号：US06803291B1
公开(公告)日：2004-10-12
申请号：US10394089
申请日：2003-03-20
申请人： Shih-Chi Fu , Feng-Jia Shih , Chia-Tung Ho , Chih-Ta Wu , Ching-Sen Kuo , Jieh-Jang Chen , Gwo-Yuh Shiau , Chia-Shiung Tsia
发明人： Shih-Chi Fu , Feng-Jia Shih , Chia-Tung Ho , Chih-Ta Wu , Ching-Sen Kuo , Jieh-Jang Chen , Gwo-Yuh Shiau , Chia-Shiung Tsia
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method for protecting an alignment mark area during a CMP process including forming at least a first material layer over a process surface of a semiconductor wafer including active areas and alignment mark trenches formed in the at least one alignment mark area; forming at least a second material layer over the first material layer including the active areas and the at least one alignment mark area; lithographically patterning and etching the at least a second material layer to form at least a plurality lines of the at least a second material layer adjacent to the alignment mark trenches; and, carrying out a CMP process to remove at least a portion of the at least a second material layer.
摘要翻译：一种用于在CMP工艺期间保护对准标记区域的方法，包括在半导体晶片的工艺表面上形成至少第一材料层，所述半导体晶片包括形成在所述至少一个对准标记区域中的有源区和对准标记沟槽; 在包括所述有源区域和所述至少一个对准标记区域的所述第一材料层上形成至少第二材料层; 对所述至少第二材料层进行光刻图案化和蚀刻，以形成与所述对准标记沟槽相邻的所述至少第二材料层的至少多条线; 以及执行CMP处理以去除所述至少第二材料层的至少一部分。

13. 发明授权

US07851324B2 Method of forming metal-insulator-metal structure 有权
标题翻译：金属绝缘体金属结构形成方法
公开(公告)号：US07851324B2
公开(公告)日：2010-12-14
申请号：US11586528
申请日：2006-10-26
申请人： Yu-Jen Wang , Chia-Shiung Tsai , Yeur-Luen Tu , Lan-Lin Chao , Chih-Ta Wu , Hsing-Lien Lin , Chung Chien Wang
发明人： Yu-Jen Wang , Chia-Shiung Tsai , Yeur-Luen Tu , Lan-Lin Chao , Chih-Ta Wu , Hsing-Lien Lin , Chung Chien Wang
IPC分类号： H01L29/94
CPC分类号： H01L28/60 , H01L21/321
摘要： A method of manufacturing a semiconductor device includes forming a metal-insulator-metal (MIM) device having a metal organic chemical vapor deposited (MOCVD) lower electrode and an atomic layer deposited (ALD) upper electrode.
摘要翻译：一种制造半导体器件的方法包括形成具有金属有机化学气相沉积（MOCVD）下电极和原子层沉积（ALD）上电极的金属 - 绝缘体 - 金属（MIM）器件。

14. 发明授权

US07554145B2 Magnetic memory cells and manufacturing methods 有权
标题翻译：磁记忆体和制造方法
公开(公告)号：US07554145B2
公开(公告)日：2009-06-30
申请号：US11610760
申请日：2006-12-14
申请人： Yuan-Hung Liu , Chih-Ta Wu , Lan-Lin Chao , Yeur-Luen Tu , Wen-Chin Lin , Chia-Shiung Tsai
发明人： Yuan-Hung Liu , Chih-Ta Wu , Lan-Lin Chao , Yeur-Luen Tu , Wen-Chin Lin , Chia-Shiung Tsai
IPC分类号： H01L29/76
CPC分类号： H01L43/12 , H01L27/228
摘要： An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.
摘要翻译：改进的磁阻存储器件具有减小的磁存储元件与用于写入磁存储器元件的导电存储器线之间的距离。通过根据包括在磁阻存储元件上形成掩模并在掩模层上形成绝缘层，然后使用平坦化处理去除绝缘层的部分的方法，通过形成改进的磁阻存储器件来简化缩短的距离。然后可以在掩模层中形成导电通孔，例如使用镶嵌工艺。然后可以在掩模层和导电通孔上形成导电存储器线。

15. 发明授权

US07202130B2 Spacer for a split gate flash memory cell and a memory cell employing the same 有权
标题翻译：分离栅闪存单元的间隔器和采用其的存储单元
公开(公告)号：US07202130B2
公开(公告)日：2007-04-10
申请号：US10775290
申请日：2004-02-10
申请人： Yuan-Hung Liu , Chih-Ta Wu , Yeur-Luen Tu , Chi-Hsin Lo , Chia-Shiung Tsai
发明人： Yuan-Hung Liu , Chih-Ta Wu , Yeur-Luen Tu , Chi-Hsin Lo , Chia-Shiung Tsai
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A spacer, a split gate flash memory cell, and related method of forming the same. In one aspect, a composite spacer includes a first spacer insulating layer having a first deposition distribution that varies as a function of a location on a substrate. The composite spacer also includes a second spacer insulating layer having a second deposition distribution that varies in substantial opposition to the first deposition distribution. In another aspect, a composite spacer includes a first spacer insulating layer having a substantially uniform deposition distribution across a surface thereof. The composite spacer also includes a second spacer insulating layer having a varying deposition distribution with a thinner composition in selected regions of the memory cell. In another aspect, a coupling spacer provides for a conductive layer that extends between a floating gate and a substrate insulating layer adjacent a source recessed into the substrate of the memory cell.
摘要翻译：间隔物，分裂栅极闪存单元及其相关方法。在一个方面，一种复合间隔物包括具有第一沉积分布的第一间隔绝缘层，其随着基底上的位置而变化。复合间隔物还包括具有与第一沉积分布基本相反的第二沉积分布的第二间隔绝缘层。在另一方面，复合间隔物包括在其表面上具有基本均匀的沉积分布的第一间隔绝缘层。复合间隔物还包括具有在存储单元的选定区域中具有较薄组成的不同沉积分布的第二间隔绝缘层。在另一方面，耦合间隔物提供导电层，该导电层在浮置栅极和与凹入到存储器单元的衬底中的源极相邻的衬底绝缘层之间延伸。

16. 发明授权

US6150238A Method for fabricating a trench isolation 有权
标题翻译：沟槽隔离方法
公开(公告)号：US6150238A
公开(公告)日：2000-11-21
申请号：US313129
申请日：1999-05-17
申请人： Chih-Ta Wu , Wen-Jet Su , Tun-Fu Hung , Ming-Ren Chi
发明人： Chih-Ta Wu , Wen-Jet Su , Tun-Fu Hung , Ming-Ren Chi
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： A method for fabricating a trench isolation is disclosed. First, a first insulated layer having a void is formed within the trench of the semiconductor. Next, the upper portion of said first insulated layer is etched to remove the void of said first insulated layer. Then, a second insulated layer having a void is formed over the first insulated layer. Next, the upper portion of said second insulated layer is etched to remove the void of said second insulated layer, thereby forming a trench isolation including the remainder of said first and second insulated layers.
摘要翻译：公开了一种用于制造沟槽隔离的方法。首先，在半导体的沟槽内形成具有空隙的第一绝缘层。接下来，蚀刻所述第一绝缘层的上部以去除所述第一绝缘层的空隙。然后，在第一绝缘层上形成具有空隙的第二绝缘层。接下来，蚀刻所述第二绝缘层的上部以去除所述第二绝缘层的空隙，由此形成包括所述第一和第二绝缘层的剩余部分的沟槽隔离。

17. 发明授权

US07443005B2 Lens structures suitable for use in image sensors and method for making the same 有权
标题翻译：适用于图像传感器的镜头结构及其制作方法
公开(公告)号：US07443005B2
公开(公告)日：2008-10-28
申请号：US10982978
申请日：2004-11-05
申请人： Ching-Sen Kuo , Feng-Jia Shiu , Gwo-Yuh Shiau , Jieh-Jang Chen , Shih-Chi Fu , Chien Hsien Tseng , Chia-Shiung Tsai , Yuan-Hung Liu , Yeur-Luen Tu , Chih-Ta Wu , Chi-Hsin Lo
发明人： Ching-Sen Kuo , Feng-Jia Shiu , Gwo-Yuh Shiau , Jieh-Jang Chen , Shih-Chi Fu , Chien Hsien Tseng , Chia-Shiung Tsai , Yuan-Hung Liu , Yeur-Luen Tu , Chih-Ta Wu , Chi-Hsin Lo
IPC分类号： H01L29/78
CPC分类号： H01L27/14621 , H01L27/14625 , H01L27/14627 , H01L27/14632 , H01L27/14685 , H01L27/14687
摘要： An image sensor includes a double-microlens structure with an outer microlens aligned over an inner microlens, both microlenses aligned over a corresponding photosensor. The inner or outer microlens may be formed by a silylation process in which a reactive portion of a photoresist material reacts with a silicon-containing agent. The inner or outer microlens may be formed by step etching of a dielectric material, the step etching process including a series of alternating etch steps including an anisotropic etching step and an etching step that causes patterned photoresist to laterally recede. Subsequent isotropic etching processes may be used to smooth the etched step structure and form a smooth lens. A thermally stable and photosensitive polymeric/organic material may also be used to form permanent inner or outer lenses. The photosensitive material is coated then patterned using photolithography, reflowed, then cured to form a permanent lens structure.
摘要翻译：图像传感器包括双微透镜结构，其外部微透镜在内部微透镜上对准，两个微透镜在相应的光电传感器上对准。内部或外部微透镜可以通过甲硅烷基化方法形成，其中光致抗蚀剂材料的反应性部分与含硅试剂反应。内部或外部微透镜可以通过介电材料的步骤蚀刻形成，该步骤蚀刻工艺包括一系列交替蚀刻步骤，其包括各向异性蚀刻步骤和使图案化光致抗蚀剂横向后退的蚀刻步骤。可以使用随后的各向同性蚀刻工艺来平滑蚀刻的台阶结构并形成光滑的透镜。热稳定和感光的聚合物/有机材料也可用于形成永久的内镜片或外镜片。感光材料被涂覆，然后使用光刻图案化，回流，然后固化以形成永久性透镜结构。

18. 发明申请

US20060183318A1 MAGNETIC MEMORY CELLS AND MANUFACTURING METHODS 有权
标题翻译：磁记忆细胞和制造方法
公开(公告)号：US20060183318A1
公开(公告)日：2006-08-17
申请号：US10906357
申请日：2005-02-15
申请人： Yuan-Hung Liu , Chih-Ta Wu , Lan-Lin Chao , Yeur-Luen Tu , Wen-Chin Lin , Chia-Shiung Tsai
发明人： Yuan-Hung Liu , Chih-Ta Wu , Lan-Lin Chao , Yeur-Luen Tu , Wen-Chin Lin , Chia-Shiung Tsai
IPC分类号： H01L21/4763 , H01L21/00
CPC分类号： H01L43/12 , H01L27/228
摘要： An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.
摘要翻译：改进的磁阻存储器件具有减小的磁存储元件与用于写入磁存储器元件的导电存储器线之间的距离。通过根据包括在磁阻存储元件上形成掩模并在掩模层上形成绝缘层，然后使用平坦化处理去除绝缘层的部分的方法，通过形成改进的磁阻存储器件来简化缩短的距离。然后可以在掩模层中形成导电通孔，例如使用镶嵌工艺。然后可以在掩模层和导电通孔上形成导电存储器线。

19. 发明授权

US06265269B1 Method for fabricating a concave bottom oxide in a trench 有权
标题翻译：在沟槽中制造凹底氧化物的方法
公开(公告)号：US06265269B1
公开(公告)日：2001-07-24
申请号：US09369266
申请日：1999-08-06
申请人： Chien-Hung Chen , Chih-Ta Wu , Ching-Shun Lin , Juinn-Sheng Chen
发明人： Chien-Hung Chen , Chih-Ta Wu , Ching-Shun Lin , Juinn-Sheng Chen
IPC分类号： H01L21336
CPC分类号： H01L29/42368 , H01L29/7813
摘要： A method for forming a concave bottom oxide layer in a trench, comprising: providing a semiconductor substrate; forming a pad oxide layer on the semiconductor substrate; forming a silicon nitride layer on the pad oxide layer; etching the silicon nitride layer, the pad oxide layer and the semiconductor substrate to form the trench in the semiconductor substrate; depositing a silicon oxide layer to refill into the trench and cover on the silicon nitride layer, wherein the silicon oxide layer has overhang portions at corners of the trench; anisotropically etching the silicon oxide layer to form a concave bottom oxide layer in the trench; etching the silicon oxide layer to remove the silicon oxide layer on the silicon nitride layer and the sidewalls of the trench; removing the silicon nitride layer and the pad oxide layer.
摘要翻译：一种在沟槽中形成凹底部氧化物层的方法，包括：提供半导体衬底; 在所述半导体衬底上形成衬垫氧化物层; 在所述焊盘氧化物层上形成氮化硅层; 蚀刻氮化硅层，焊盘氧化物层和半导体衬底，以在半导体衬底中形成沟槽; 沉积硅氧化物层以重新填充到沟槽中并覆盖在氮化硅层上，其中氧化硅层在沟槽的拐角处具有突出部分; 各向异性地蚀刻氧化硅层以在沟槽中形成凹的底部氧化物层; 蚀刻氧化硅层以除去氮化硅层和沟槽的侧壁上的氧化硅层; 去除氮化硅层和衬垫氧化物层。

20. 发明授权

US06265233B1 Method for determining crack limit of film deposited on semiconductor wafer 有权
标题翻译：确定沉积在半导体晶圆上的薄膜裂纹极限的方法
公开(公告)号：US06265233B1
公开(公告)日：2001-07-24
申请号：US09326096
申请日：1999-06-04
申请人： Jason C. S. Chu , Jerry C. S. Lin , Roger Tun-Fu Hung , Chih-Ta Wu
发明人： Jason C. S. Chu , Jerry C. S. Lin , Roger Tun-Fu Hung , Chih-Ta Wu
IPC分类号： G01R3126
CPC分类号： H01L22/34 , H01L21/02164 , H01L21/02271 , H01L21/31612
摘要： A method for determining a crack limit of a target film deposited on a wafer in production after a post annealing procedure is disclosed. The crack limit is determined by adopting and adjusting the thermal shrinkage rates of a plurality of target films deposited on bare wafers and annealed. The test results on bare wafers can be applied to the production wafers to prevent from film cracking and/or inspect instrumental conditions.
摘要翻译：公开了一种用于确定在后退火程序之后在生产中沉积在晶片上的靶膜的裂纹极限的方法。通过采用和调整沉积在裸晶片上并退火的多个靶膜的热收缩率来确定裂纹极限。裸晶片上的测试结果可以应用于生产晶片，以防止膜破裂和/或检查仪器条件。

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