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11. 发明申请

US20070075789A1 STRUCTURE AND METHOD FOR PROVIDING GATE LEAKAGE ISOLATION LOCALLY WITHIN ANALOG CIRCUITS 失效
标题翻译：在模拟电路中局部地提供闸门泄漏隔离的结构和方法
公开(公告)号：US20070075789A1
公开(公告)日：2007-04-05
申请号：US11163013
申请日：2005-09-30
申请人： Anthony Bonaccio , Hayden Cranford , Joseph Iadanza , Stephen Wyatt
发明人： Anthony Bonaccio , Hayden Cranford , Joseph Iadanza , Stephen Wyatt
IPC分类号： H03B5/12
CPC分类号： H03L7/093 , H03L7/0891
摘要： A loop filter for a phase-locked-loop is provided, comprising a set of capacitor banks coupled in parallel to form the loop filter, and a detection circuit for identifying and isolating defective capacitor banks. A method for providing a loop filter for a phase-locked-loop in accordance with an embodiment of the present invention includes the steps of forming the loop filter using a set of capacitor banks coupled in parallel, detecting any defective capacitor banks in the set of capacitor banks, isolating each defective capacitor bank, providing a set of redundant capacitor banks, and replacing each defective capacitor bank with a redundant capacitor bank from the set of redundant capacitor banks.
摘要翻译：提供了一种用于锁相环的环路滤波器，包括并联耦合以形成环路滤波器的一组电容器组，以及用于识别和隔离有缺陷的电容器组的检测电路。根据本发明的实施例的用于提供用于锁相环的环路滤波器的方法包括以下步骤：使用并联耦合的一组电容器组形成环路滤波器，检测该组中的任何有缺陷的电容器组电容器组，隔离每个有缺陷的电容器组，提供一组冗余电容器组，并从冗余电容器组组中的冗余电容器组替换每个有缺陷的电容器组。

12. 发明申请

US20060192611A1 BODY-BIASED ENHANCED PRECISION CURRENT MIRROR 失效
标题翻译：身体偏心增强精度电流镜
公开(公告)号：US20060192611A1
公开(公告)日：2006-08-31
申请号：US10906628
申请日：2005-02-28
申请人： Anthony Bonaccio , Hayden Cranford
发明人： Anthony Bonaccio , Hayden Cranford
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： A body-biased enhanced current mirror reference circuit is disclosed wherein the body bias voltage of a current mirror device is varied to adjust its threshold voltage. Both the drain and body potentials of a replica mirror transistor are controlled to selected values. The drain is set to an expected DC voltage output of an NFET current mirror device. The body potential is set to a maximum desired value to prevent forward biasing of the body-to-diffusion junction(s) of one or more current mirror devices, which is accomplished by a feedback control circuit. A low-frequency, low-precision op amp drives the gate of a replica load device so that the body of the replica NFET current mirror device is set to a maximum bias voltage. The maximum bias voltage is also used to bias the body of a diode connected NMOS reference transistor, so that the current in the NFET current mirror device will be approximately equal to the current in the diode-connected NMOS reference. An auxiliary NFET current mirror device may be added to the body-biased enhanced current mirror circuit with the body connected to ground as in the unmodified current mirror to negate a non-monotonicity of the current output.
摘要翻译：公开了一种体偏置增强电流镜参考电路，其中电流镜装置的体偏置电压被改变以调节其阈值电压。复制镜晶体管的漏极和体电位都被控制为选定值。漏极设置为NFET电流镜器件的预期直流电压输出。身体电位被设置为最大期望值，以防止由反馈控制电路实现的一个或多个电流镜装置的体对扩散结的正向偏置。低频，低精度运算放大器驱动复制负载装置的栅极，使得复制NFET电流镜装置的主体被设置为最大偏置电压。最大偏置电压也用于偏置二极管连接的NMOS参考晶体管的主体，使得NFET电流镜器件中的电流将近似等于连接二极管的NMOS参考电流。辅助NFET电流镜装置可以被添加到主体偏置的增强电流镜电路中，其中主体连接到地面，如在未修改的电流镜中，以消除电流输出的非单调性。

13. 发明申请

US20060038602A1 Clock signal distribution utilizing differential sinusoidal signal pair 失效
公开(公告)号：US20060038602A1
公开(公告)日：2006-02-23
申请号：US11255707
申请日：2005-10-21
申请人： Anthony Bonaccio , John Cohn , Alvar Dean , Amir Farrahi , David Hathaway , Sebastian Ventrone
发明人： Anthony Bonaccio , John Cohn , Alvar Dean , Amir Farrahi , David Hathaway , Sebastian Ventrone
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.

14. 发明申请

US20060259840A1 SELF-TEST CIRCUITRY TO DETERMINE MINIMUM OPERATING VOLTAGE 审中-公开
标题翻译：自检电路确定最小工作电压
公开(公告)号：US20060259840A1
公开(公告)日：2006-11-16
申请号：US10908452
申请日：2005-05-12
申请人： Wagdi Abadeer , George Braceras , Anthony Bonaccio , Kevin Gorman
发明人： Wagdi Abadeer , George Braceras , Anthony Bonaccio , Kevin Gorman
IPC分类号： G01R31/28
CPC分类号： G01R31/3004
摘要： A solution for determining minimum operating voltages due to performance/power requirements would be valid for a wide range of actual uses. The solution includes a test flow methodology for dynamically reducing power consumption under applied conditions while maintaining application performance via a BIST circuit. There is additionally provided a test flow method for dynamically reducing power consumption to the lowest possible stand-by/very low power level under applied conditions that will still be sufficient to maintain data/state information. One possible application would be for controlling the voltage supply to a group of particular circuits on an ASIC (Application Specific Integrated Circuit). These circuits are grouped together in a voltage island where they would receive a voltage supply that can be different from the voltage supply other circuits on the same chip are receiving. The same solution could be applied to a portion of a microprocessor (the cache logic control, for example).
摘要翻译：用于确定由于性能/功率要求而导致的最小工作电压的解决方案对于广泛的实际应用是有效的。该解决方案包括测试流程方法，用于在应用条件下动态降低功耗，同时通过BIST电路保持应用性能。另外提供了一种测试流程方法，用于在仍然足以维护数据/状态信息的应用条件下将功耗动态地降低到最低可能待机/极低功率水平。一种可能的应用是用于控制对ASIC（专用集成电路）上的一组特定电路的电压供应。这些电路分组在一个电压岛中，在那里它们将接收可以与同一芯片正在接收的其它电路的电压供给不同的电压源。相同的解决方案可以应用于微处理器的一部分（例如，高速缓存逻辑控制）。

15. 发明申请

US20050110551A1 Damping of LC Ringing in IC (Integrated Circuit) Power Distribution Systems 失效
标题翻译： IC（集成电路）配电系统中LC振荡的阻尼
公开(公告)号：US20050110551A1
公开(公告)日：2005-05-26
申请号：US10707171
申请日：2003-11-25
申请人： Anthony Bonaccio , Allen Haar , Michael Sorna , Ivan Wemple , Stephen Wyatt
发明人： Anthony Bonaccio , Allen Haar , Michael Sorna , Ivan Wemple , Stephen Wyatt
IPC分类号： G05F1/10 , G05F3/02 , H03K17/16 , H03L5/00
CPC分类号： G11C5/14 , H01L23/50 , H01L2924/0002 , H03K17/164 , H01L2924/00
摘要： A structure and method for damping LC (inductance-capacitance) ringing in integrated circuit (IC) power distribution systems. The structure comprises a resistance electrically connected in parallel with a plurality of electrical switches. The resistance and electrical switches are electrically connected in series with the package and on-chip power distribution circuit. When on-chip switching activity creates a sudden and appreciable change in IC power demand the electrical switches are opened to temporarily increase the resistance in series with the power supply. This serves to dampen the power-distribution LC ringing. Later, the electrical switches are closed to shunt the series resistance and reduce the level of steady-state voltage drop in the power structure.
摘要翻译：用于阻尼集成电路（IC）配电系统中LC（电感 - 电容）振铃的结构和方法。该结构包括与多个电开关并联电连接的电阻。电阻和电气开关与封装和片上配电电路串联电连接。当片上切换活动产生IC功率需求的突然和明显的变化时，电开关被打开以临时增加与电源串联的电阻。这用于抑制功率分配LC振铃。之后，电开关闭合以分流串联电阻并降低电源结构中稳态电压降的水平。

16. 发明申请

US20070200744A1 INTRINSIC RC POWER DISTRIBUTION FOR NOISE FILTERING OF ANALOG SUPPLIES 有权
标题翻译：用于噪声滤波的模拟电源的内部RC功率分配
公开(公告)号：US20070200744A1
公开(公告)日：2007-08-30
申请号：US11276451
申请日：2006-02-28
申请人： Anthony Bonaccio , Hayden Cranford , Joseph Iadanza , Sebastian Ventrone , Stephen Wyatt
发明人： Anthony Bonaccio , Hayden Cranford , Joseph Iadanza , Sebastian Ventrone , Stephen Wyatt
IPC分类号： H03M1/66
CPC分类号： G05F1/46
摘要： Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit.
摘要翻译：用于模拟电路的模拟电源和用于向模拟电路提供模拟信号的过程。模拟电源包括具有可变电阻器的噪声滤波器和耦合以调节可变电阻器的控制装置。控制装置被构造和布置成设置可变电阻器的电阻以最大化噪声滤波并优化模拟电路的性能。

17. 发明申请

US20070115019A1 METHOD AND APPARATUS FOR STORING CIRCUIT CALIBRATION INFORMATION 失效
标题翻译：存储电路校准信息的方法和装置
公开(公告)号：US20070115019A1
公开(公告)日：2007-05-24
申请号：US11164040
申请日：2005-11-08
申请人： Anthony Bonaccio , Allen Haar , Joseph Iadanza , Douglas Stout , Ivan Wemple
发明人： Anthony Bonaccio , Allen Haar , Joseph Iadanza , Douglas Stout , Ivan Wemple
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , G01R35/005
摘要： A method for altering circuit characteristics to make them independent of processing parameters of devices within an integrated circuit is disclosed. A process parameter is measured by a kerf or on-chip built-in test on a selective set of chip on a wafer, and the results are stored on a storage device within each respective chip. Then, for each of the remaining chips, a two-dimensional interpolation is performed to determine the process parameter value for the respective chip based on the measured value. The interpolated values are recorded along with the coordinates of the chip in an efuse control file. Such information is subsequently stored into an efuse module within the chip. On-chip digital control structures are used to adjust certain operational characteristics of a functional component within the chip based on the information stored in the efuse module.
摘要翻译：公开了一种用于改变电路特性以使它们与集成电路内的器件的处理参数无关的方法。通过在晶片上的选择性芯片组上的切口或片上内置测试来测量工艺参数，并将结果存储在每个相应芯片内的存储装置上。然后，对于剩余的每个芯片，执行二维内插，以基于测量值确定各个芯片的处理参数值。内插值与芯片在efuse控制文件中的坐标一起被记录。这样的信息随后被存储在芯片内的efuse模块中。片上数字控制结构用于根据存储在efuse模块中的信息来调整芯片内的功能组件的某些操作特性。

18. 发明申请

US20060285584A1 Jitter generator to simulate a closed data eye 审中-公开
标题翻译：抖动发生器来模拟一个封闭的数据眼睛
公开(公告)号：US20060285584A1
公开(公告)日：2006-12-21
申请号：US11155028
申请日：2005-06-16
申请人： Steven Baumgartner , Anthony Bonaccio , Timothy Buchholtz , Charles Geer , Daniel Young
发明人： Steven Baumgartner , Anthony Bonaccio , Timothy Buchholtz , Charles Geer , Daniel Young
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , G01R31/31709
摘要： Techniques and apparatus for testing jitter tolerance of a device are provided. Jitter control logic within a device may include a master phase rotator to rapidly adjust the phase of a clock signal to simulate jitter in a data stream received by the device. For some embodiments, the rate, magnitude, and signature (or waveform shape) of the phase adjustments may be controlled to simulate high frequency jitter. Errors in received data packets may be monitored while simulating this jitter (e.g., as part of a built in self test) to test the jitter tolerance of a device under test.
摘要翻译：提供了用于测试设备的抖动容限的技术和设备。设备内的抖动控制逻辑可以包括主相位旋转器，用于快速调整时钟信号的相位以模拟由设备接收的数据流中的抖动。对于一些实施例，可以控制相位调整的速率，幅度和签名（或波形形状）以模拟高频抖动。可以在模拟该抖动（例如，作为内置自检的一部分）的同时监视接收到的数据分组中的错误，以测试被测器件的抖动容限。

19. 发明申请

US20060285583A1 Phase rotator control test scheme 失效
公开(公告)号：US20060285583A1
公开(公告)日：2006-12-21
申请号：US11155027
申请日：2005-06-16
申请人： Steven Baumgartner , Anthony Bonaccio , Timothy Buchholtz , Charles Geer , Daniel Young
发明人： Steven Baumgartner , Anthony Bonaccio , Timothy Buchholtz , Charles Geer , Daniel Young
IPC分类号： H04L27/06
CPC分类号： G01R31/317
摘要： Techniques and apparatus for testing phase rotators for detecting defective tap weights are provided. Phase rotator test logic may include a master phase rotator to cycle the phase of a clock signal distributed to operational phase rotators through an entire cycle of phases (e.g., an entire 360 degree rotation). Each operational phase rotator should respond with an equal but opposite phase shift in order to maintain phase lock. Thus, after sweeping, each tap weight is exercised, which may help ensure defective tap weights in any (e.g., quadrant) are detected during testing.

20. 发明申请

US20060022753A1 METHOD AND APPARATUS FOR CONTROLLING COMMON-MODE OUTPUT VOLTAGE IN FULLY DIFFERENTIAL AMPLIFIERS 有权
标题翻译：用于控制全差分放大器中的共模输出电压的方法和装置
公开(公告)号：US20060022753A1
公开(公告)日：2006-02-02
申请号：US10710745
申请日：2004-07-30
申请人： Anthony Bonaccio , Hayden Cranford, Jr. , Michael Sorna , Sebastian Ventrone
发明人： Anthony Bonaccio , Hayden Cranford, Jr. , Michael Sorna , Sebastian Ventrone
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/4565 , H03F3/45659 , H03F2200/78 , H03F2203/45418 , H03F2203/45424 , H03F2203/45521
摘要： A method for controlling the common-mode output voltage in a fully differential amplifier includes comparing a sensed common-mode output voltage of the fully differential amplifier to a reference voltage, and generating an error signal representing the difference between the sensed common-mode output voltage and the reference voltage. The error signal is utilized to control the body voltage of one or more FET devices included within the fully differential amplifier until the sensed common-mode output voltage is in agreement with said reference voltage.
摘要翻译：一种用于控制全差分放大器中的共模输出电压的方法包括将全差分放大器的感测共模输出电压与参考电压进行比较，并产生一个误差信号，该误差信号表示检测到的共模输出电压和参考电压。误差信号用于控制包括在全差分放大器内的一个或多个FET器件的体电压，直到检测到的共模输出电压与所述参考电压一致。

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