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1. 发明申请

US20060259840A1 SELF-TEST CIRCUITRY TO DETERMINE MINIMUM OPERATING VOLTAGE 审中-公开
标题翻译：自检电路确定最小工作电压
公开(公告)号：US20060259840A1
公开(公告)日：2006-11-16
申请号：US10908452
申请日：2005-05-12
申请人： Wagdi Abadeer , George Braceras , Anthony Bonaccio , Kevin Gorman
发明人： Wagdi Abadeer , George Braceras , Anthony Bonaccio , Kevin Gorman
IPC分类号： G01R31/28
CPC分类号： G01R31/3004
摘要： A solution for determining minimum operating voltages due to performance/power requirements would be valid for a wide range of actual uses. The solution includes a test flow methodology for dynamically reducing power consumption under applied conditions while maintaining application performance via a BIST circuit. There is additionally provided a test flow method for dynamically reducing power consumption to the lowest possible stand-by/very low power level under applied conditions that will still be sufficient to maintain data/state information. One possible application would be for controlling the voltage supply to a group of particular circuits on an ASIC (Application Specific Integrated Circuit). These circuits are grouped together in a voltage island where they would receive a voltage supply that can be different from the voltage supply other circuits on the same chip are receiving. The same solution could be applied to a portion of a microprocessor (the cache logic control, for example).
摘要翻译：用于确定由于性能/功率要求而导致的最小工作电压的解决方案对于广泛的实际应用是有效的。该解决方案包括测试流程方法，用于在应用条件下动态降低功耗，同时通过BIST电路保持应用性能。另外提供了一种测试流程方法，用于在仍然足以维护数据/状态信息的应用条件下将功耗动态地降低到最低可能待机/极低功率水平。一种可能的应用是用于控制对ASIC（专用集成电路）上的一组特定电路的电压供应。这些电路分组在一个电压岛中，在那里它们将接收可以与同一芯片正在接收的其它电路的电压供给不同的电压源。相同的解决方案可以应用于微处理器的一部分（例如，高速缓存逻辑控制）。

2. 发明申请

US20070188249A1 Programmable capacitors and methods of using the same 有权
标题翻译：可编程电容器及其使用方法
公开(公告)号：US20070188249A1
公开(公告)日：2007-08-16
申请号：US11353516
申请日：2006-02-14
申请人： Wagdi Abadeer , Anthony Bonaccio , Jack Mandelman , William Tonti , Sebastian Ventrone
发明人： Wagdi Abadeer , Anthony Bonaccio , Jack Mandelman , William Tonti , Sebastian Ventrone
IPC分类号： H03B5/12
CPC分类号： H03L7/099 , H03B5/1212 , H03B5/1228 , H03B5/124 , H03L7/095 , H03L7/10 , H03L7/18 , H03L2207/06
摘要： In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the transistor is adapted to operate in a first mode to provide a capacitance and further adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode; and (2) employing the transistor in a circuit. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种调整半导体器件的电容的方法。第一种方法包括以下步骤：（1）提供包括具有约3.9至约25的介电常数的介电材料的晶体管，其中该晶体管适于在第一模式下工作以提供电容，并进一步适于在将晶体管的阈值电压从初始阈值电压改变到改变的阈值电压，使得当在第一模式中操作时，改变的阈值电压影响由晶体管提供的电容; 和（2）在电路中采用晶体管。提供了许多其他方面。

3. 发明申请

US20060091951A1 INTEGRATED CIRCUIT AMPLIFIER DEVICE AND METHOD USING FET TUNNELING GATE CURRENT 失效
标题翻译：集成电路放大器装置及使用FET隧道栅极电流的方法
公开(公告)号：US20060091951A1
公开(公告)日：2006-05-04
申请号：US10904238
申请日：2004-10-29
申请人： Wagdi Abadeer , Anthony Bonaccio , Kiran Chatty , John Fifield
发明人： Wagdi Abadeer , Anthony Bonaccio , Kiran Chatty , John Fifield
IPC分类号： H03F3/45 , H03F3/16
CPC分类号： H03F3/16 , H03F3/45179 , H03F3/505 , H03F2203/45468
摘要： An integrated circuit amplifier includes, in an exemplary embodiment, a first field effect transistor (FET) device configured as a source follower and a second FET device configured as a tunneling gate FET, the tunneling gate FET coupled to the source follower. The tunneling gate FET is further configured so as to set a transconductance of the amplifier and the source follower is configured so as to set an output conductance of the amplifier.
摘要翻译：在示例性实施例中，集成电路放大器包括被配置为源极跟随器的第一场效应晶体管（FET）器件和被配置为隧道栅极FET的第二FET器件，所述隧道栅极FET耦合到源极跟随器。隧道栅极FET进一步配置为设置放大器的跨导，并且配置源极跟随器以便设置放大器的输出电导。

4. 发明申请

US20070189076A1 Memory elements and methods of using the same 失效
标题翻译：内存元素和使用方法
公开(公告)号：US20070189076A1
公开(公告)日：2007-08-16
申请号：US11353493
申请日：2006-02-14
申请人： Wagdi Abadeer , Anthony Bonaccio , Jack Mandelman , William Tonti , Sebastian Ventrone
发明人： Wagdi Abadeer , Anthony Bonaccio , Jack Mandelman , William Tonti , Sebastian Ventrone
IPC分类号： G11C16/04
CPC分类号： G11C16/0466
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由存储元件在第一模式下操作。提供了许多其他方面。

5. 发明申请

US20070222488A1 ADJUSTABLE PHASE CONTROLLED CLOCK AND DATA RECOVERY CIRCUIT 失效
标题翻译：可调相位控制时钟和数据恢复电路
公开(公告)号：US20070222488A1
公开(公告)日：2007-09-27
申请号：US11757510
申请日：2007-06-04
申请人： Anthony Bonaccio , Charles Masenas , Troy Seman
发明人： Anthony Bonaccio , Charles Masenas , Troy Seman
IPC分类号： H03L7/00
CPC分类号： H03L7/081 , H04L7/033
摘要： A clock and data recovery circuit including: means for generating a first and a second clock signal; means for receiving the first clock signal and for generating a third clock signal from the first clock signal and means for receiving the second clock signal and for generating a fourth clock signal, wherein at least one of the third and the fourth clock signals differ in phase from the first and the second clock signal respectively; means for receiving the third and fourth clock signals and a serial data stream and for generating a reconstructed serial data stream and a phase error signal; means for receiving the phase error signal and for generating a phase adjustment signal and means for receiving the phase adjustment signal by the by the clock generation circuit in a feedback loop to adjust the phases of the first and second clock signals.
摘要翻译：一种时钟和数据恢复电路，包括：用于产生第一和第二时钟信号的装置; 用于接收第一时钟信号并用于从第一时钟信号产生第三时钟信号的装置，以及用于接收第二时钟信号并产生第四时钟信号的装置，其中第三和第四时钟信号中的至少一个在相位上是不同的分别从第一和第二时钟信号; 用于接收第三和第四时钟信号和串行数据流并用于产生重建的串行数据流和相位误差信号的装置; 用于接收相位误差信号并产生相位调整信号的装置，以及用于在反馈回路中由时钟产生电路接收相位调整信号的装置，以调整第一和第二时钟信号的相位。

6. 发明申请

US20050125707A1 Digital reliability monitor having autonomic repair and notification capability 有权
标题翻译：数字可靠性监控器具有自主修复和通知功能
公开(公告)号：US20050125707A1
公开(公告)日：2005-06-09
申请号：US10729751
申请日：2003-12-04
申请人： Anthony Bonaccio , Michael LeStrange , William Tonti , Sebastian Ventrone
发明人： Anthony Bonaccio , Michael LeStrange , William Tonti , Sebastian Ventrone
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： An integrated circuit, including: a pulse generator adapted to generate a pulsed signal; a cycle counter adapted to count cycles of the pulsed signal; one or more repairable circuit elements; and a repair processor adapted to repair a repairable circuit element when the cycle counter reaches a pre-determined cycle count.
摘要翻译：一种集成电路，包括：适于产生脉冲信号的脉冲发生器; 适于计数所述脉冲信号的周期的周期计数器; 一个或多个可修复电路元件; 以及修理处理器，其适于在循环计数器达到预定周期计数时修复可修复的电路元件。

7. 发明申请

US20050071399A1 PSEUDO-RANDOM BINARY SEQUENCE CHECKER WITH AUTOMATIC SYNCHRONIZATION 有权
标题翻译：具有自动同步的PSEUDO随机二进制序列检查器
公开(公告)号：US20050071399A1
公开(公告)日：2005-03-31
申请号：US10605381
申请日：2003-09-26
申请人： Anthony Bonaccio , Allen Haar
发明人： Anthony Bonaccio , Allen Haar
IPC分类号： G01R31/317 , G01R31/3183 , G06F1/02 , G06F7/58
CPC分类号： G01R31/318385 , G01R31/31703 , G01R31/31728 , G06F7/584 , G06F2207/582
摘要： A pseudo-random binary sequence checker having automatic synchronization is disclosed. The pseudo-random binary sequence checker includes a receiver, a synchronizer, and a comparator. The receiver is capable of receiving a pseudo-random binary sequence, which is generated by a pseudo-random binary sequence generator, in a parallel fashion n bits at a time. The synchronizer automatically synchronizes the state of the receiver with an n-bit sample within the pseudo-random binary sequence and calculate all subsequent n-bit sample within the pseudo-random binary sequence. The comparator compares the subsequent calculated n-bit sample within the pseudo-random binary sequence to the next subsequent next received n-bit sample within the pseudo-random binary sequence to indicate an error condition has occurred if each calculated n-bit sample within the pseudo-random binary sequence does not equal to the corresponding received n-bit sample within the pseudo-random binary sequence.
摘要翻译：公开了具有自动同步的伪随机二进制序列检验器。伪随机二进制序列检查器包括接收器，同步器和比较器。接收机能够以并行方式一次接收由伪随机二进制序列生成器生成的伪随机二进制序列，每个n位。同步器自动将接收器的状态与伪随机二进制序列内的n位采样同步，并计算伪随机二进制序列内的所有随后的n位采样。比较器将伪随机二进制序列中随后计算的n位采样与伪随机二进制序列中的下一个接下来的接收到的n位采样进行比较，以指示如果每个计算的n位采样在伪随机二进制序列不等于伪随机二进制序列内的相应接收的n位样本。

8. 发明申请

US20070075789A1 STRUCTURE AND METHOD FOR PROVIDING GATE LEAKAGE ISOLATION LOCALLY WITHIN ANALOG CIRCUITS 失效
标题翻译：在模拟电路中局部地提供闸门泄漏隔离的结构和方法
公开(公告)号：US20070075789A1
公开(公告)日：2007-04-05
申请号：US11163013
申请日：2005-09-30
申请人： Anthony Bonaccio , Hayden Cranford , Joseph Iadanza , Stephen Wyatt
发明人： Anthony Bonaccio , Hayden Cranford , Joseph Iadanza , Stephen Wyatt
IPC分类号： H03B5/12
CPC分类号： H03L7/093 , H03L7/0891
摘要： A loop filter for a phase-locked-loop is provided, comprising a set of capacitor banks coupled in parallel to form the loop filter, and a detection circuit for identifying and isolating defective capacitor banks. A method for providing a loop filter for a phase-locked-loop in accordance with an embodiment of the present invention includes the steps of forming the loop filter using a set of capacitor banks coupled in parallel, detecting any defective capacitor banks in the set of capacitor banks, isolating each defective capacitor bank, providing a set of redundant capacitor banks, and replacing each defective capacitor bank with a redundant capacitor bank from the set of redundant capacitor banks.
摘要翻译：提供了一种用于锁相环的环路滤波器，包括并联耦合以形成环路滤波器的一组电容器组，以及用于识别和隔离有缺陷的电容器组的检测电路。根据本发明的实施例的用于提供用于锁相环的环路滤波器的方法包括以下步骤：使用并联耦合的一组电容器组形成环路滤波器，检测该组中的任何有缺陷的电容器组电容器组，隔离每个有缺陷的电容器组，提供一组冗余电容器组，并从冗余电容器组组中的冗余电容器组替换每个有缺陷的电容器组。

9. 发明申请

US20060192611A1 BODY-BIASED ENHANCED PRECISION CURRENT MIRROR 失效
标题翻译：身体偏心增强精度电流镜
公开(公告)号：US20060192611A1
公开(公告)日：2006-08-31
申请号：US10906628
申请日：2005-02-28
申请人： Anthony Bonaccio , Hayden Cranford
发明人： Anthony Bonaccio , Hayden Cranford
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： A body-biased enhanced current mirror reference circuit is disclosed wherein the body bias voltage of a current mirror device is varied to adjust its threshold voltage. Both the drain and body potentials of a replica mirror transistor are controlled to selected values. The drain is set to an expected DC voltage output of an NFET current mirror device. The body potential is set to a maximum desired value to prevent forward biasing of the body-to-diffusion junction(s) of one or more current mirror devices, which is accomplished by a feedback control circuit. A low-frequency, low-precision op amp drives the gate of a replica load device so that the body of the replica NFET current mirror device is set to a maximum bias voltage. The maximum bias voltage is also used to bias the body of a diode connected NMOS reference transistor, so that the current in the NFET current mirror device will be approximately equal to the current in the diode-connected NMOS reference. An auxiliary NFET current mirror device may be added to the body-biased enhanced current mirror circuit with the body connected to ground as in the unmodified current mirror to negate a non-monotonicity of the current output.
摘要翻译：公开了一种体偏置增强电流镜参考电路，其中电流镜装置的体偏置电压被改变以调节其阈值电压。复制镜晶体管的漏极和体电位都被控制为选定值。漏极设置为NFET电流镜器件的预期直流电压输出。身体电位被设置为最大期望值，以防止由反馈控制电路实现的一个或多个电流镜装置的体对扩散结的正向偏置。低频，低精度运算放大器驱动复制负载装置的栅极，使得复制NFET电流镜装置的主体被设置为最大偏置电压。最大偏置电压也用于偏置二极管连接的NMOS参考晶体管的主体，使得NFET电流镜器件中的电流将近似等于连接二极管的NMOS参考电流。辅助NFET电流镜装置可以被添加到主体偏置的增强电流镜电路中，其中主体连接到地面，如在未修改的电流镜中，以消除电流输出的非单调性。

10. 发明申请

US20060136751A1 Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable 有权
公开(公告)号：US20060136751A1
公开(公告)日：2006-06-22
申请号：US11016219
申请日：2004-12-17
申请人： Anthony Bonaccio , Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
发明人： Anthony Bonaccio , Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
IPC分类号： G06F12/14
CPC分类号： G06F12/1433 , G06F21/6245
摘要： Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).

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