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1. 发明申请

US20070200744A1 INTRINSIC RC POWER DISTRIBUTION FOR NOISE FILTERING OF ANALOG SUPPLIES 有权
标题翻译：用于噪声滤波的模拟电源的内部RC功率分配
公开(公告)号：US20070200744A1
公开(公告)日：2007-08-30
申请号：US11276451
申请日：2006-02-28
申请人： Anthony Bonaccio , Hayden Cranford , Joseph Iadanza , Sebastian Ventrone , Stephen Wyatt
发明人： Anthony Bonaccio , Hayden Cranford , Joseph Iadanza , Sebastian Ventrone , Stephen Wyatt
IPC分类号： H03M1/66
CPC分类号： G05F1/46
摘要： Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit.
摘要翻译：用于模拟电路的模拟电源和用于向模拟电路提供模拟信号的过程。模拟电源包括具有可变电阻器的噪声滤波器和耦合以调节可变电阻器的控制装置。控制装置被构造和布置成设置可变电阻器的电阻以最大化噪声滤波并优化模拟电路的性能。

2. 发明申请

US20070075789A1 STRUCTURE AND METHOD FOR PROVIDING GATE LEAKAGE ISOLATION LOCALLY WITHIN ANALOG CIRCUITS 失效
标题翻译：在模拟电路中局部地提供闸门泄漏隔离的结构和方法
公开(公告)号：US20070075789A1
公开(公告)日：2007-04-05
申请号：US11163013
申请日：2005-09-30
申请人： Anthony Bonaccio , Hayden Cranford , Joseph Iadanza , Stephen Wyatt
发明人： Anthony Bonaccio , Hayden Cranford , Joseph Iadanza , Stephen Wyatt
IPC分类号： H03B5/12
CPC分类号： H03L7/093 , H03L7/0891
摘要： A loop filter for a phase-locked-loop is provided, comprising a set of capacitor banks coupled in parallel to form the loop filter, and a detection circuit for identifying and isolating defective capacitor banks. A method for providing a loop filter for a phase-locked-loop in accordance with an embodiment of the present invention includes the steps of forming the loop filter using a set of capacitor banks coupled in parallel, detecting any defective capacitor banks in the set of capacitor banks, isolating each defective capacitor bank, providing a set of redundant capacitor banks, and replacing each defective capacitor bank with a redundant capacitor bank from the set of redundant capacitor banks.
摘要翻译：提供了一种用于锁相环的环路滤波器，包括并联耦合以形成环路滤波器的一组电容器组，以及用于识别和隔离有缺陷的电容器组的检测电路。根据本发明的实施例的用于提供用于锁相环的环路滤波器的方法包括以下步骤：使用并联耦合的一组电容器组形成环路滤波器，检测该组中的任何有缺陷的电容器组电容器组，隔离每个有缺陷的电容器组，提供一组冗余电容器组，并从冗余电容器组组中的冗余电容器组替换每个有缺陷的电容器组。

3. 发明申请

US20060181323A1 SYSTEM AND METHOD FOR BALANCING DELAY OF SIGNAL COMMUNICATION PATHS THROUGH WELL VOLTAGE ADJUSTMENT 有权
标题翻译：通过良好的电压调整来平衡信号通信的延迟的系统和方法
公开(公告)号：US20060181323A1
公开(公告)日：2006-08-17
申请号：US10906343
申请日：2005-02-15
申请人： Hayden Cranford , Joseph Iadanza , Sebastian Ventrone
发明人： Hayden Cranford , Joseph Iadanza , Sebastian Ventrone
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00032
摘要： A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and a falling edge delay of the test signal is equalized by adjusting a body bias voltage of a delay element configured within the selected communication path. A rising edge delay and a falling edge delay for each of the remaining communication paths is compared with the equalized rising edge delay and falling edge delay of the selected communication path, and a body bias voltage for one or more of a plurality of delay elements configured within each of the remaining communication paths is adjusted until corresponding rising and falling edge delays thereof match the equalized rising edge delay and falling edge delay of the selected communication path.
摘要翻译：在集成电路的模拟域和数字域之间平衡信号互连路径延迟的方法包括将测试信号应用于模拟域和数字域之间的多个通信路径中的所选择的一个。通过调整配置在所选择的通信路径内的延迟元件的体偏置电压来平衡测试信号的上升沿延迟和下降沿延迟。将每个剩余通信路径的上升沿延迟和下降沿延迟与所选择的通信路径的均衡的上升沿延迟和下降沿延迟进行比较，并且配置多个延迟元件中的一个或多个的体偏置电压在每个剩余的通信路径内进行调整，直到相应的上升沿和下降沿延迟与所选通信路径的均衡上升沿延迟和下降沿延迟相匹配。

4. 发明申请

US20070075731A1 METHOD AND APPARATUS FOR REDUCING NOISE IN A DYNAMIC MANNER 有权
标题翻译：用于减少动态漫画噪声的方法和装置
公开(公告)号：US20070075731A1
公开(公告)日：2007-04-05
申请号：US11163015
申请日：2005-09-30
申请人： Igor Arsovski , Hayden Cranford , Joseph Iadanza , Sebastian Ventrone
发明人： Igor Arsovski , Hayden Cranford , Joseph Iadanza , Sebastian Ventrone
IPC分类号： H03K19/003
CPC分类号： H03K19/00346
摘要： An integrated circuit device includes functional logic, an anti-noise machine, and state monitoring points providing the anti-noise machine with an interface to the functional logic for monitoring states of the functional logic. The anti-noise machine includes indicia defining noise precursor states for the functional logic, and recognition logic coupled to the state monitoring points. The anti-noise machine is operable to generate anti-noise responsive to the recognition logic detecting in the functional logic noise precursor states matching the indicia.
摘要翻译：集成电路设备包括功能逻辑，抗噪声机器和状态监测点，其为抗噪声机器提供与用于监视功能逻辑状态的功能逻辑的接口。抗噪声机器包括定义用于功能逻辑的噪声前导状态的标记，以及耦合到状态监测点的识别逻辑。抗噪声机器可操作以响应于与标记匹配的功能逻辑噪声前导状态中的识别逻辑检测产生抗噪声。

5. 发明申请

US20060192611A1 BODY-BIASED ENHANCED PRECISION CURRENT MIRROR 失效
标题翻译：身体偏心增强精度电流镜
公开(公告)号：US20060192611A1
公开(公告)日：2006-08-31
申请号：US10906628
申请日：2005-02-28
申请人： Anthony Bonaccio , Hayden Cranford
发明人： Anthony Bonaccio , Hayden Cranford
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： A body-biased enhanced current mirror reference circuit is disclosed wherein the body bias voltage of a current mirror device is varied to adjust its threshold voltage. Both the drain and body potentials of a replica mirror transistor are controlled to selected values. The drain is set to an expected DC voltage output of an NFET current mirror device. The body potential is set to a maximum desired value to prevent forward biasing of the body-to-diffusion junction(s) of one or more current mirror devices, which is accomplished by a feedback control circuit. A low-frequency, low-precision op amp drives the gate of a replica load device so that the body of the replica NFET current mirror device is set to a maximum bias voltage. The maximum bias voltage is also used to bias the body of a diode connected NMOS reference transistor, so that the current in the NFET current mirror device will be approximately equal to the current in the diode-connected NMOS reference. An auxiliary NFET current mirror device may be added to the body-biased enhanced current mirror circuit with the body connected to ground as in the unmodified current mirror to negate a non-monotonicity of the current output.
摘要翻译：公开了一种体偏置增强电流镜参考电路，其中电流镜装置的体偏置电压被改变以调节其阈值电压。复制镜晶体管的漏极和体电位都被控制为选定值。漏极设置为NFET电流镜器件的预期直流电压输出。身体电位被设置为最大期望值，以防止由反馈控制电路实现的一个或多个电流镜装置的体对扩散结的正向偏置。低频，低精度运算放大器驱动复制负载装置的栅极，使得复制NFET电流镜装置的主体被设置为最大偏置电压。最大偏置电压也用于偏置二极管连接的NMOS参考晶体管的主体，使得NFET电流镜器件中的电流将近似等于连接二极管的NMOS参考电流。辅助NFET电流镜装置可以被添加到主体偏置的增强电流镜电路中，其中主体连接到地面，如在未修改的电流镜中，以消除电流输出的非单调性。

6. 发明申请

US20060267616A1 Systems and methods for controlling of electro-migration 有权
标题翻译：用于控制电迁移的系统和方法
公开(公告)号：US20060267616A1
公开(公告)日：2006-11-30
申请号：US11140765
申请日：2005-05-31
申请人： Hayden Cranford , Louis Hsu , James Mason , Chih-Chao Yang
发明人： Hayden Cranford , Louis Hsu , James Mason , Chih-Chao Yang
IPC分类号： G01R31/02
CPC分类号： G01R31/2858 , H01L21/76886 , H01L2924/0002 , H04B7/0814 , H01L2924/00
摘要： Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration. A plurality of switches are provided to switch current directions through a lowest level of metallization so that the circuits function normally even though the polarity of the applied voltage has been reversed.
摘要翻译：公开了用于控制电迁移的系统和方法，并减少其有害影响。实施例提供了当指示电迁移程度的测量指示操作的愈合周期是有必要的时将施加的电压反转到集成电路。在愈合周期中，集成电路的电路正常工作，但电迁移效应相反。在一个实施例中，微电子机械开关设置在最低级别的金属化处，以将电流方向切换到集成电路的金属化水平。在另一个实施例中，如果指示电迁移程度的测量超过参考电平达指定量，则施加到集成电路的电压的极性反转，导致电流切换方向以对抗电迁移。提供多个开关以切换电流方向通过最低金属化水平，使得即使施加的电压的极性已经被反转，电路也能正常工作。

7. 发明申请

US20050127978A1 Electronic component value trimming systems 失效
标题翻译：电子元件修整系统
公开(公告)号：US20050127978A1
公开(公告)日：2005-06-16
申请号：US10967756
申请日：2004-10-18
申请人： Hayden Cranford , Louis Hsu , James Mason , Gareth Nicholls , Philip Murfet , Samuel Ray
发明人： Hayden Cranford , Louis Hsu , James Mason , Gareth Nicholls , Philip Murfet , Samuel Ray
IPC分类号： H01C17/22 , H03K3/00
CPC分类号： H01C17/22
摘要： Described is a system for trimming the value of an electronic component. The system comprises: at least one trimming component, each trimming component having an associated switch for selectively connecting that trimming component to the electronic component in response to a corresponding bit in a control vector. A comparator is included for generating an output bit having a first value if a net value of the electronic component and any connected trimming components differs from a desired value. A controller connected to the switches and the comparator generates the control vector in dependence on the output of comparator, the controller comprising a shift register for sequentially receiving successive output bits from the comparator; wherein the control vector comprises the contents of the shift register and wherein a bit of said first value in control vector effects switching of the corresponding switch.
摘要翻译：描述了一种用于修整电子部件的值的系统。该系统包括：至少一个修整部件，每个修剪部件具有相关联的开关，用于响应于控制矢量中的对应位选择性地将修剪部件连接到电子部件。如果电子部件的净值和任何连接的修整部件与期望值不同，则包括比较器以产生具有第一值的输出位。连接到开关和比较器的控制器根据比较器的输出产生控制向量，该控制器包括用于顺序地从比较器接收连续输出位的移位寄存器; 其中所述控制向量包括所述移位寄存器的内容，并且其中所述控制矢量中的所述第一值的位影响相应开关的切换。

8. 发明申请

US20080112521A1 Clock Data Recovering System with External Early/Late Input 有权
标题翻译：具有外部早/晚输入的时钟数据恢复系统
公开(公告)号：US20080112521A1
公开(公告)日：2008-05-15
申请号：US11966438
申请日：2007-12-28
申请人： Martin Schmatz , Hayden Cranford , Vernon Norman
发明人： Martin Schmatz , Hayden Cranford , Vernon Norman
IPC分类号： H04L7/00
CPC分类号： H03L7/091 , H03L7/0814 , H03L7/089 , H04L7/0331
摘要： The invention is directed to a clock data recovery system for resampling a clock signal according to an incoming data signal. The clock data recovery system comprises a clock generator for generating the clock signal and a phase adjustment unit for generating sampling phases dependent on a phase adjustment control signal. It also comprises a data sampling unit operable to generate a stream of input samples and an edge detector for generating therefrom an internal early signal and an internal late signal. A phase adjustment control unit is disposed for generating under use of the early signal and the late signal the phase adjustment control signal. The phase adjustment control unit is feedable with an external early/late signal and/or comprises an output for delivering an export early/late signal.
摘要翻译：本发明涉及一种用于根据输入数据信号重新采样时钟信号的时钟数据恢复系统。时钟数据恢复系统包括用于产生时钟信号的时钟发生器和用于根据相位调整控制信号产生采样相位的相位调整单元。它还包括可操作以产生输入样本流的数据采样单元和用于从其产生内部早期信号和内部迟滞信号的边缘检测器。设置相位调整控制单元，用于在早期信号的使用下产生相位调整控制信号，并且延迟信号。相位调整控制单元可以用外部早/晚信号进给，和/或包括用于传送出口早/晚信号的输出。

9. 发明申请

US20080012642A1 SERIAL LINK RECEIVER WITH WIDE INPUT VOLTAGE RANGE AND TOLERANCE TO HIGH POWER VOLTAGE SUPPLY 有权
标题翻译：具有宽输入电压范围和宽电压电源供应的串行接收器
公开(公告)号：US20080012642A1
公开(公告)日：2008-01-17
申请号：US11417626
申请日：2006-05-04
申请人： Hayden Cranford , Westerfield Ficken , David Freitas , Joseph Stevens
发明人： Hayden Cranford , Westerfield Ficken , David Freitas , Joseph Stevens
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F1/52 , H03F3/45973 , H03F2203/45078 , H03F2203/45431 , H03F2203/45541 , H03F2203/45561 , H03F2203/45588
摘要： A circuit device and method for designing a serial link receiver, which accommodates a wide input voltage range and provides tolerance to high termination voltages. The receiver is designed with a pair of RC networks connected inline between the input and the preamplifier and a common mode feedback loop, which monitors shifts in the common mode voltage and adjusts the inputs provided to the preamplifier. The circuit device maintains a flat bandwidth to accommodate all signaling rates.
摘要翻译：一种用于设计串行链路接收机的电路装置和方法，其适应宽的输入电压范围并且提供对高终端电压的容限。接收机设计有一对连接在输入和前置放大器之间的RC网络和一个共模反馈环路，它监控共模电压的变化并调整提供给前置放大器的输入。电路设备保持平坦的带宽以适应所有信令速率。

10. 发明申请

US20070244656A1 METHOD AND APPARATUS FOR DETERMINING JITTER AND PULSE WIDTH FROM CLOCK SIGNAL COMPARISONS 失效
标题翻译：用于确定时钟信号比较的抖动和脉冲宽度的方法和装置
公开(公告)号：US20070244656A1
公开(公告)日：2007-10-18
申请号：US11279651
申请日：2006-04-13
申请人： Hayden Cranford , Fadi Gebara , Jeremy Schaub
发明人： Hayden Cranford , Fadi Gebara , Jeremy Schaub
IPC分类号： G06F19/00 , G01R29/02 , G06F17/40
CPC分类号： G01R31/31709 , G01R31/31725
摘要： A method and apparatus for determining jitter and pulse width from clock signal comparisons provides a low cost and production-integrable mechanism for measuring a clock signal with a reference clock, both of unknown frequency. The measured clock signal is sampled at transitions of a reference clock and the sampled values are collected in a histogram according to a folding of the samples around a timebase which is either swept to detect a minimum jitter for the folded data or is obtained from direct frequency analysis for the sample set. The histogram for the correct estimated period is statistically analyzed to yield the pulse width, which is the difference between the peaks of the probability density function and jitter, which corresponds to width of the density function peaks. Frequency drift is corrected by adjusting the timebase used to fold the data across the sample set.
摘要翻译：用于从时钟信号比较确定抖动和脉冲宽度的方法和装置提供了一种低成本和可生产可集成的机制，用于测量具有未知频率的参考时钟的时钟信号。测量的时钟信号在参考时钟的转变时被采样，并且采样值被收集在直方图中，根据时基的周围样本的折叠，该时基被扫描以检测折叠数据的最小抖动，或者从直接频率获得分析样本集。统计分析正确估计周期的直方图以产生脉冲宽度，其是概率密度函数和抖动的峰值之间的差异，其对应于密度函数峰值的宽度。通过调整用于将样本集合中的数据折叠的时基来校正频率漂移。

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