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1. 发明申请

US20070115019A1 METHOD AND APPARATUS FOR STORING CIRCUIT CALIBRATION INFORMATION 失效
标题翻译：存储电路校准信息的方法和装置
公开(公告)号：US20070115019A1
公开(公告)日：2007-05-24
申请号：US11164040
申请日：2005-11-08
申请人： Anthony Bonaccio , Allen Haar , Joseph Iadanza , Douglas Stout , Ivan Wemple
发明人： Anthony Bonaccio , Allen Haar , Joseph Iadanza , Douglas Stout , Ivan Wemple
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , G01R35/005
摘要： A method for altering circuit characteristics to make them independent of processing parameters of devices within an integrated circuit is disclosed. A process parameter is measured by a kerf or on-chip built-in test on a selective set of chip on a wafer, and the results are stored on a storage device within each respective chip. Then, for each of the remaining chips, a two-dimensional interpolation is performed to determine the process parameter value for the respective chip based on the measured value. The interpolated values are recorded along with the coordinates of the chip in an efuse control file. Such information is subsequently stored into an efuse module within the chip. On-chip digital control structures are used to adjust certain operational characteristics of a functional component within the chip based on the information stored in the efuse module.
摘要翻译：公开了一种用于改变电路特性以使它们与集成电路内的器件的处理参数无关的方法。通过在晶片上的选择性芯片组上的切口或片上内置测试来测量工艺参数，并将结果存储在每个相应芯片内的存储装置上。然后，对于剩余的每个芯片，执行二维内插，以基于测量值确定各个芯片的处理参数值。内插值与芯片在efuse控制文件中的坐标一起被记录。这样的信息随后被存储在芯片内的efuse模块中。片上数字控制结构用于根据存储在efuse模块中的信息来调整芯片内的功能组件的某些操作特性。

2. 发明申请

US20070226667A1 STATIC TIMING SLACKS ANALYSIS AND MODIFICATION 有权
标题翻译：静态时序分析与修改
公开(公告)号：US20070226667A1
公开(公告)日：2007-09-27
申请号：US11277385
申请日：2006-03-24
申请人： Thomas Chadwick , Margaret Charlebois , David Hathaway , Jason Rotella , Douglas Stout , Ivan Wemple
发明人： Thomas Chadwick , Margaret Charlebois , David Hathaway , Jason Rotella , Douglas Stout , Ivan Wemple
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5031
摘要： A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.
摘要翻译：公开了一种用于在具有瞬态电源的集成电路（IC）的设计的静态时序分析中分析和修改定时路径的静态定时松弛的方法，系统和计算机程序产品。在IC中的选定端点处执行静态时序松弛分析，以获得以最差的静态时序松弛通向端点的候选定时路径。瞬态电源下的时钟信号的每个时钟周期的候选定时路径确定瞬态静态时序松弛。使用确定的瞬态静态时序松弛来调整IC的定时并修改候选定时路径的静态时序松弛。

3. 发明申请

US20060229828A1 VOLTAGE DEPENDENT PARAMETER ANALYSIS 有权
标题翻译：电压依赖参数分析
公开(公告)号：US20060229828A1
公开(公告)日：2006-10-12
申请号：US11095327
申请日：2005-03-31
申请人： David Hathaway , Douglas Stout , Ivan Wemple
发明人： David Hathaway , Douglas Stout , Ivan Wemple
IPC分类号： G06F19/00
CPC分类号： G06F17/5036
摘要： A method of, and a system for, determining an extreme value of a voltage dependent parameter of an integrated circuit design is provided. The method includes determining a plurality of current waveforms, each of the plurality of waveforms corresponding to one of a plurality of aggressor objects in the design of the integrated circuit; applying each of the plurality of current waveforms to a subset of the plurality of power bus nodes, the subset of the plurality of power bus nodes being designed to supply power to a corresponding one of the plurality of aggressor objects; determining a plurality of voltage waveforms, each of the plurality of voltage waveforms being at one of the plurality of power bus nodes and corresponding to one of the plurality of current waveforms; using the plurality of voltage waveforms to determine the extreme value.
摘要翻译：提供了一种用于确定集成电路设计的电压相关参数的极值的方法和系统。所述方法包括确定多个电流波形，所述多个波形中的每一个对应于所述集成电路的设计中的多个侵略对象中的一个; 将所述多个电流波形中的每一个应用于所述多个电力总线节点的子集，所述多个电力总线节点的子集被设计为向所述多个侵权者对象中的相应一个提供电力; 确定多个电压波形，所述多个电压波形中的每一个在所述多个电力总线节点中的一个处并且对应于所述多个电流波形中的一个; 使用多个电压波形来确定极值。

4. 发明申请

US20070278582A1 STRUCTURE AND METHOD FOR IMPLEMENTING OXIDE LEAKAGE BASED VOLTAGE DIVIDER NETWORK FOR INTEGRATED CIRCUIT DEVICES 审中-公开
公开(公告)号：US20070278582A1
公开(公告)日：2007-12-06
申请号：US11841247
申请日：2007-08-20
申请人： Kenneth Goodnow , Joseph Iadanza , Edward Nowak , Douglas Stout
发明人： Kenneth Goodnow , Joseph Iadanza , Edward Nowak , Douglas Stout
IPC分类号： H01L29/739
CPC分类号： H01L29/42384 , H01L21/823842 , H01L21/823857 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/785 , H01L29/78645 , H01L29/78648
摘要： A voltage divider device includes a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region. An input voltage is coupled between the first and second gates, and an output voltage is taken from at least one of a source of the FET and a drain of the FET, wherein the output voltage represents a divided voltage with respect to the input voltage.

5. 发明申请

US20070252641A1 STRUCTURE AND METHOD FOR IMPLEMENTING OXIDE LEAKAGE BASED VOLTAGE DIVIDER NETWORK FOR INTEGRATED CIRCUIT DEVICES 有权
标题翻译：用于集成电路设备实现基于氧化物泄漏的电压分压网络的结构和方法
公开(公告)号：US20070252641A1
公开(公告)日：2007-11-01
申请号：US11380799
申请日：2006-04-28
申请人： Kenneth Goodnow , Joseph Iadanza , Edward Nowak , Douglas Stout
发明人： Kenneth Goodnow , Joseph Iadanza , Edward Nowak , Douglas Stout
IPC分类号： G05F1/10
CPC分类号： H01L29/42384 , H01L21/823842 , H01L21/823857 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/785 , H01L29/78645 , H01L29/78648
摘要： A voltage divider device includes a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region. An input voltage is coupled between the first and second gates, and an output voltage is taken from at least one of a source of the FET and a drain of the FET, wherein the output voltage represents a divided voltage with respect to the input voltage.
摘要翻译：分压器件包括具有第一栅极的双栅极场效应晶体管（FET）和设置在主体区域的相对侧的第二栅极。输入电压耦合在第一和第二栅极之间，并且输出电压取自FET的源极和FET的漏极中的至少一个，其中输出电压表示相对于输入电压的分压。

6. 发明申请

US20060190744A1 METHOD OF SWITCHING VOLTAGE ISLANDS IN INTEGRATED CIRCUITS 有权
标题翻译：在电路中切换电压岛的方法
公开(公告)号：US20060190744A1
公开(公告)日：2006-08-24
申请号：US10906476
申请日：2005-02-22
申请人： Rafael Blanco , John Cohn , Kenneth Goodnow , Douglas Stout , Sebastian Ventrone
发明人： Rafael Blanco , John Cohn , Kenneth Goodnow , Douglas Stout , Sebastian Ventrone
IPC分类号： G06F1/26
CPC分类号： G06F1/3287 , G06F1/26 , G06F1/3203 , Y02D10/171
摘要： An integrated circuit has a power grid and a set of independently switchable voltage islands, together with a system and method for measuring the voltage and history of the voltage on the power grid to determine the correct time to allow a large capacitive load (such as a voltage island) to be switched on to or off the power grid.
摘要翻译：集成电路具有电网和一组可独立切换的电压岛，以及用于测量电网电压和历史的系统和方法，以确定允许大容性负载（例如，电压岛）被接通或断开电网。

7. 发明申请

US20110192840A1 TECHNIQUES FOR AT LEAST ONE OF TRANSPORT, STORAGE, AND DISPLAY OF ONE OR MORE ITEMS OF AT LEAST ONE OF APPAREL AND ACCESSORIES 失效
标题翻译：至少一个运输，存储和显示一个或多个服装和附件的物品的技术
公开(公告)号：US20110192840A1
公开(公告)日：2011-08-11
申请号：US12941950
申请日：2010-11-08
申请人： Kristin Marie Raffone VAZQUEZ , Robert Gooch , Douglas Stout
发明人： Kristin Marie Raffone VAZQUEZ , Robert Gooch , Douglas Stout
IPC分类号： B65D6/28 , A47F7/19 , B65D43/14
CPC分类号： A47F7/08 , B65D25/102 , B65D81/02 , B65D85/187
摘要： An apparatus for at least one of the transport, storage, and display of one or more items of at least one of apparel and accessories is provided. The apparatus includes at least one crib defined by a bottom plate, a back plate, and first and second side plates, each of the at least one crib for having disposed therein one or more items of at least one of apparel and accessories. The at least one crib includes the bottom plate that is one of square and rectangular in shape, the back plate that is one of square and rectangular in shape, and the first and second side plates that have the same shape and that are facing each other. Each of the back plate and first and second side plates are perpendicular to the bottom plate. One edge of each of the back plate and first and second side plates is coupled to a respective one edge of the bottom plate. One edge of each of first and second side plates is coupled to a respective one edge of the back plat. An opening of the crib is defined by one edge of each of the bottom plate, the back plate, and the first and second side plates.
摘要翻译：提供了用于服装和附件中的至少一个的一个或多个物品的运输，存储和显示中的至少一个的装置。该装置包括由底板，后板和第一和第二侧板限定的至少一个婴儿床，所述至少一个婴儿床中的每一个在其中设置有一件或多件衣服和附件中的至少一个。至少一个婴儿床包括底板，其为正方形和矩形之一，后板为正方形和矩形之一，第一和第二侧板具有相同的形状并且彼此相对。背板和第一和第二侧板中的每一个垂直于底板。背板和第一和第二侧板中的每一个的一个边缘联接到底板的相应的一个边缘。第一和第二侧板中的每一个的一个边缘连接到背板的相应的一个边缘。婴儿床的开口由底板，后板和第一和第二侧板中的每一个的一个边缘限定。

8. 发明申请

US20080086706A1 METHODS AND CIRCUITS TO REDUCE THRESHOLD VOLTAGE TOLERANCE AND SKEW IN MULTI-THRESHOLD VOLTAGE APPLICATIONS 失效
标题翻译：降低多电压电压应用中阈值电压公差和电流的方法和电路
公开(公告)号：US20080086706A1
公开(公告)日：2008-04-10
申请号：US11941342
申请日：2007-11-16
申请人： Corey Barrows , Douglas Kemerer , Stephen Shuma , Douglas Stout , Oscar Strohacker , Mark Styduhar , Paul Zuchowski
发明人： Corey Barrows , Douglas Kemerer , Stephen Shuma , Douglas Stout , Oscar Strohacker , Mark Styduhar , Paul Zuchowski
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , H01L27/088 , H01L27/092
摘要： A design structure. The design structure includes: a first set of FETs having a designed first Vt and a second set of FETs having a designed second Vt, the first Vt different from the second Vt; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and of the second monitor circuit; a control unit responsive to the compare signal and configured to generate a control signal regulator based on the compare signal; and an adjustable voltage regulator responsive to the control signal and configured to voltage bias wells of FETs of the second set of FETs, the value of the voltage bias applied based on the control signal.
摘要翻译：设计结构。该设计结构包括：具有设计的第一V FET的第一组FET和具有设计的第二V FET的第二组FET，第一V T 与第二V 不同; 包含第一组FET的至少一个FET的第一监视器电路和包含第二组FET的至少一个FET的第二监视电路; 比较电路，被配置为基于所述第一监视电路和所述第二监视电路的性能测量来产生比较信号; 控制单元，响应于比较信号并被配置为基于比较信号产生控制信号调节器; 以及响应于所述控制信号并被配置为所述第二组FET的FET的电压偏置阱的可调电压调节器，所述电压偏置值基于所述控制信号施加。

9. 发明申请

US20060064660A1 METHOD AND APPARATUS FOR DEPOPULATING PERIPHERAL INPUT/OUTPUT CELLS 失效
标题翻译：用于解剖外周输入/输出细胞的方法和装置
公开(公告)号：US20060064660A1
公开(公告)日：2006-03-23
申请号：US10711431
申请日：2004-09-17
申请人： Wai Chung-Maloney , Douglas Stout , Steven Urish
发明人： Wai Chung-Maloney , Douglas Stout , Steven Urish
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5068 , H01L24/06 , H01L2224/05554 , H01L2924/1305 , H01L2924/14 , H01L2924/00
摘要： Chip area corresponding to unnecessary I/O cell sites is recovered and made usable for additional core cells and power connections by grouping I/O cells into I/O kernels of contiguous I/O cells having power connections independent of other I/O kernels and depopulating I/O cell sites in accordance with areas corresponding to I/O kernels. Since I/O kernels have dedicated power connections, no power busses are present in the depopulated I/O cell sites which can then be freely use for additional core cells, power connections or the like. This technique also allows selection of a chip of minimum required area to be determined prior to design of chip layout.
摘要翻译：通过将I / O单元分组成具有独立于其它I / O内核的电源连接的连续I / O单元的I / O内核，可以恢复对应于不需要的I / O单元位置的芯片区域并使其可用于附加核心单元和电源连接，根据对应于I / O内核的区域，减少I / O单元位置。由于I / O内核具有专用电源连接，所以在经过缩减的I / O单元站点中不存在功率总线，然后可以自由地使用电源总线用于其他核心单元，电源连接等。该技术还允许在设计芯片布局之前选择要确定的最小所需区域的芯片。

10. 发明申请

US20100213640A1 MASONRY UNIT FORMING SYSTEMS AND METHODS 审中-公开
标题翻译： MASONRY单位形成系统和方法
公开(公告)号：US20100213640A1
公开(公告)日：2010-08-26
申请号：US12393951
申请日：2009-02-26
申请人： Mario Piazzesi , Douglas Stout , Trevor Stout , David Easton
发明人： Mario Piazzesi , Douglas Stout , Trevor Stout , David Easton
IPC分类号： B28B3/08 , B29C43/00
CPC分类号： B28B3/08 , B28B3/086
摘要： A masonry unit forming system including a mold box having a first open side and a second open side; a first mold plate; a second mold plate; a first drive mechanism configured to move the first mold plate into the first open side of the mold box; and a second drive mechanism configured to move the second mold plate into the second open side of the mold box.
摘要翻译：一种砖石单元形成系统，包括具有第一开口侧和第二开口侧的模具箱; 第一模板; 第二模板; 第一驱动机构，其构造成将第一模板移动到模具箱的第一开口侧; 以及第二驱动机构，其构造成将所述第二模板移动到所述模具箱的所述第二开口侧。

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