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1. 发明申请

US20070200744A1 INTRINSIC RC POWER DISTRIBUTION FOR NOISE FILTERING OF ANALOG SUPPLIES 有权
标题翻译：用于噪声滤波的模拟电源的内部RC功率分配
公开(公告)号：US20070200744A1
公开(公告)日：2007-08-30
申请号：US11276451
申请日：2006-02-28
申请人： Anthony Bonaccio , Hayden Cranford , Joseph Iadanza , Sebastian Ventrone , Stephen Wyatt
发明人： Anthony Bonaccio , Hayden Cranford , Joseph Iadanza , Sebastian Ventrone , Stephen Wyatt
IPC分类号： H03M1/66
CPC分类号： G05F1/46
摘要： Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit.
摘要翻译：用于模拟电路的模拟电源和用于向模拟电路提供模拟信号的过程。模拟电源包括具有可变电阻器的噪声滤波器和耦合以调节可变电阻器的控制装置。控制装置被构造和布置成设置可变电阻器的电阻以最大化噪声滤波并优化模拟电路的性能。

2. 发明申请

US20060022753A1 METHOD AND APPARATUS FOR CONTROLLING COMMON-MODE OUTPUT VOLTAGE IN FULLY DIFFERENTIAL AMPLIFIERS 有权
标题翻译：用于控制全差分放大器中的共模输出电压的方法和装置
公开(公告)号：US20060022753A1
公开(公告)日：2006-02-02
申请号：US10710745
申请日：2004-07-30
申请人： Anthony Bonaccio , Hayden Cranford, Jr. , Michael Sorna , Sebastian Ventrone
发明人： Anthony Bonaccio , Hayden Cranford, Jr. , Michael Sorna , Sebastian Ventrone
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/4565 , H03F3/45659 , H03F2200/78 , H03F2203/45418 , H03F2203/45424 , H03F2203/45521
摘要： A method for controlling the common-mode output voltage in a fully differential amplifier includes comparing a sensed common-mode output voltage of the fully differential amplifier to a reference voltage, and generating an error signal representing the difference between the sensed common-mode output voltage and the reference voltage. The error signal is utilized to control the body voltage of one or more FET devices included within the fully differential amplifier until the sensed common-mode output voltage is in agreement with said reference voltage.
摘要翻译：一种用于控制全差分放大器中的共模输出电压的方法包括将全差分放大器的感测共模输出电压与参考电压进行比较，并产生一个误差信号，该误差信号表示检测到的共模输出电压和参考电压。误差信号用于控制包括在全差分放大器内的一个或多个FET器件的体电压，直到检测到的共模输出电压与所述参考电压一致。

3. 发明申请

US20060181323A1 SYSTEM AND METHOD FOR BALANCING DELAY OF SIGNAL COMMUNICATION PATHS THROUGH WELL VOLTAGE ADJUSTMENT 有权
标题翻译：通过良好的电压调整来平衡信号通信的延迟的系统和方法
公开(公告)号：US20060181323A1
公开(公告)日：2006-08-17
申请号：US10906343
申请日：2005-02-15
申请人： Hayden Cranford , Joseph Iadanza , Sebastian Ventrone
发明人： Hayden Cranford , Joseph Iadanza , Sebastian Ventrone
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00032
摘要： A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and a falling edge delay of the test signal is equalized by adjusting a body bias voltage of a delay element configured within the selected communication path. A rising edge delay and a falling edge delay for each of the remaining communication paths is compared with the equalized rising edge delay and falling edge delay of the selected communication path, and a body bias voltage for one or more of a plurality of delay elements configured within each of the remaining communication paths is adjusted until corresponding rising and falling edge delays thereof match the equalized rising edge delay and falling edge delay of the selected communication path.
摘要翻译：在集成电路的模拟域和数字域之间平衡信号互连路径延迟的方法包括将测试信号应用于模拟域和数字域之间的多个通信路径中的所选择的一个。通过调整配置在所选择的通信路径内的延迟元件的体偏置电压来平衡测试信号的上升沿延迟和下降沿延迟。将每个剩余通信路径的上升沿延迟和下降沿延迟与所选择的通信路径的均衡的上升沿延迟和下降沿延迟进行比较，并且配置多个延迟元件中的一个或多个的体偏置电压在每个剩余的通信路径内进行调整，直到相应的上升沿和下降沿延迟与所选通信路径的均衡上升沿延迟和下降沿延迟相匹配。

4. 发明申请

US20070075731A1 METHOD AND APPARATUS FOR REDUCING NOISE IN A DYNAMIC MANNER 有权
标题翻译：用于减少动态漫画噪声的方法和装置
公开(公告)号：US20070075731A1
公开(公告)日：2007-04-05
申请号：US11163015
申请日：2005-09-30
申请人： Igor Arsovski , Hayden Cranford , Joseph Iadanza , Sebastian Ventrone
发明人： Igor Arsovski , Hayden Cranford , Joseph Iadanza , Sebastian Ventrone
IPC分类号： H03K19/003
CPC分类号： H03K19/00346
摘要： An integrated circuit device includes functional logic, an anti-noise machine, and state monitoring points providing the anti-noise machine with an interface to the functional logic for monitoring states of the functional logic. The anti-noise machine includes indicia defining noise precursor states for the functional logic, and recognition logic coupled to the state monitoring points. The anti-noise machine is operable to generate anti-noise responsive to the recognition logic detecting in the functional logic noise precursor states matching the indicia.
摘要翻译：集成电路设备包括功能逻辑，抗噪声机器和状态监测点，其为抗噪声机器提供与用于监视功能逻辑状态的功能逻辑的接口。抗噪声机器包括定义用于功能逻辑的噪声前导状态的标记，以及耦合到状态监测点的识别逻辑。抗噪声机器可操作以响应于与标记匹配的功能逻辑噪声前导状态中的识别逻辑检测产生抗噪声。

5. 发明申请

US20070283185A1 DIGITAL RELIABILITY MONITOR HAVING AUTONOMIC REPAIR AND NOTIFICATION CAPABILITY 有权
标题翻译：具有自动维修和通知能力的数字可靠性监控器
公开(公告)号：US20070283185A1
公开(公告)日：2007-12-06
申请号：US11772418
申请日：2007-07-02
申请人： Anthony Bonaccio , Michael LeStrange , William Tonti , Sebastian Ventrone
发明人： Anthony Bonaccio , Michael LeStrange , William Tonti , Sebastian Ventrone
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： An integrated circuit, including: a pulse generator adapted to generate a pulsed signal; a cycle counter adapted to count cycles of the pulsed signal; one or more repairable circuit elements; and a repair processor adapted to repair a repairable circuit element when the cycle counter reaches a pre-determined cycle count.
摘要翻译：一种集成电路，包括：适于产生脉冲信号的脉冲发生器; 适于计数所述脉冲信号周期的循环计数器; 一个或多个可修复电路元件; 以及修理处理器，其适于在循环计数器达到预定周期计数时修复可修复的电路元件。

6. 发明申请

US20050144524A1 Digital reliability monitor having autonomic repair and notification capability 审中-公开
标题翻译：数字可靠性监控器具有自主修复和通知功能
公开(公告)号：US20050144524A1
公开(公告)日：2005-06-30
申请号：US10863194
申请日：2004-06-08
申请人： Anthony Bonaccio , Michael LeStrange , William Tonti , Sebastian Ventrone
发明人： Anthony Bonaccio , Michael LeStrange , William Tonti , Sebastian Ventrone
IPC分类号： G06F1/04 , G06F11/00
CPC分类号： G06F1/04
摘要： A method a circuit for preventing failure in an integrated circuit. The circuit including: an original circuit; one or more redundant circuits; and a repair processor, including a clock cycle counter adapted to count pulses of a pulsed signal, the repair processor adapted to (a) replace the original circuit with a first redundant circuit or (b) adapted to select another redundant circuit, the selection in sequence from a second redundant circuit to a last redundant circuit, and to replace a previously selected redundant circuit with the selected redundant circuit each time the cycle counter reaches a predetermined count of a set of predetermined cycle counts.
摘要翻译：一种用于防止集成电路中的故障的电路的方法。电路包括：原电路; 一个或多个冗余电路; 以及修复处理器，包括适于计数脉冲信号的脉冲的时钟周期计数器，所述修复处理器适于（a）用第一冗余电路替换原始电路，或（b）适于选择另一个冗余电路，从第二冗余电路到最后一个冗余电路的序列，并且每次循环计数器达到一组预定循环计数的预定计数时，用选定的冗余电路替换先前选择的冗余电路。

7. 发明申请

US20050125707A1 Digital reliability monitor having autonomic repair and notification capability 有权
标题翻译：数字可靠性监控器具有自主修复和通知功能
公开(公告)号：US20050125707A1
公开(公告)日：2005-06-09
申请号：US10729751
申请日：2003-12-04
申请人： Anthony Bonaccio , Michael LeStrange , William Tonti , Sebastian Ventrone
发明人： Anthony Bonaccio , Michael LeStrange , William Tonti , Sebastian Ventrone
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： An integrated circuit, including: a pulse generator adapted to generate a pulsed signal; a cycle counter adapted to count cycles of the pulsed signal; one or more repairable circuit elements; and a repair processor adapted to repair a repairable circuit element when the cycle counter reaches a pre-determined cycle count.
摘要翻译：一种集成电路，包括：适于产生脉冲信号的脉冲发生器; 适于计数所述脉冲信号的周期的周期计数器; 一个或多个可修复电路元件; 以及修理处理器，其适于在循环计数器达到预定周期计数时修复可修复的电路元件。

8. 发明申请

US20070188249A1 Programmable capacitors and methods of using the same 有权
标题翻译：可编程电容器及其使用方法
公开(公告)号：US20070188249A1
公开(公告)日：2007-08-16
申请号：US11353516
申请日：2006-02-14
申请人： Wagdi Abadeer , Anthony Bonaccio , Jack Mandelman , William Tonti , Sebastian Ventrone
发明人： Wagdi Abadeer , Anthony Bonaccio , Jack Mandelman , William Tonti , Sebastian Ventrone
IPC分类号： H03B5/12
CPC分类号： H03L7/099 , H03B5/1212 , H03B5/1228 , H03B5/124 , H03L7/095 , H03L7/10 , H03L7/18 , H03L2207/06
摘要： In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the transistor is adapted to operate in a first mode to provide a capacitance and further adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode; and (2) employing the transistor in a circuit. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种调整半导体器件的电容的方法。第一种方法包括以下步骤：（1）提供包括具有约3.9至约25的介电常数的介电材料的晶体管，其中该晶体管适于在第一模式下工作以提供电容，并进一步适于在将晶体管的阈值电压从初始阈值电压改变到改变的阈值电压，使得当在第一模式中操作时，改变的阈值电压影响由晶体管提供的电容; 和（2）在电路中采用晶体管。提供了许多其他方面。

9. 发明申请

US20070189076A1 Memory elements and methods of using the same 失效
标题翻译：内存元素和使用方法
公开(公告)号：US20070189076A1
公开(公告)日：2007-08-16
申请号：US11353493
申请日：2006-02-14
申请人： Wagdi Abadeer , Anthony Bonaccio , Jack Mandelman , William Tonti , Sebastian Ventrone
发明人： Wagdi Abadeer , Anthony Bonaccio , Jack Mandelman , William Tonti , Sebastian Ventrone
IPC分类号： G11C16/04
CPC分类号： G11C16/0466
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由存储元件在第一模式下操作。提供了许多其他方面。

10. 发明申请

US20060038602A1 Clock signal distribution utilizing differential sinusoidal signal pair 失效
公开(公告)号：US20060038602A1
公开(公告)日：2006-02-23
申请号：US11255707
申请日：2005-10-21
申请人： Anthony Bonaccio , John Cohn , Alvar Dean , Amir Farrahi , David Hathaway , Sebastian Ventrone
发明人： Anthony Bonaccio , John Cohn , Alvar Dean , Amir Farrahi , David Hathaway , Sebastian Ventrone
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.

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