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1. 发明公开

US20240219460A1 ENHANCED ELECTRON BEAM (E-BEAM) APPARATUS AND METHODOLOGY WITH NANO-SCALE E-BEAM PROBE TIPS FOR FAULT ISOLATION IN INTEGRATED CIRCUITS AND OTHER STRUCTURES 审中-公开
公开(公告)号：US20240219460A1
公开(公告)日：2024-07-04
申请号：US18090415
申请日：2022-12-28
申请人： Xianghong TONG , Jennifer HUENING , Joshua KEVEK , Kimberlee CELIO , Tristan DEBORDE , Prasoon JOSHI , May Ling OH , Hyuk Ju RYU , Mitchell SENGER , Martin VON HAARTMAN , Yunfei WANG , Shuai ZHAO
发明人： Xianghong TONG , Jennifer HUENING , Joshua KEVEK , Kimberlee CELIO , Tristan DEBORDE , Prasoon JOSHI , May Ling OH , Hyuk Ju RYU , Mitchell SENGER , Martin VON HAARTMAN , Yunfei WANG , Shuai ZHAO
IPC分类号： G01R31/307 , G01R31/311
CPC分类号： G01R31/307 , G01R31/311
摘要： This disclosure describes systems, methods, and devices related to electron beam and nanoprobing techniques with probe tips for fault isolation in integrated circuits. A method may include generating a signal at a circuit device under test while a probe tip electrically interacts with a transistor of the circuit device under test; detecting, based on the signal and the laser at the transistor, an electrical output of the circuit device under test; and identifying, based on the electrical output, a location of a fault at the circuit device under test.

2. 发明授权

US07348636B2 CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof 有权
标题翻译： CMOS晶体管具有不同的PMOS和NMOS栅电极结构及其制造方法
公开(公告)号：US07348636B2
公开(公告)日：2008-03-25
申请号：US11030245
申请日：2005-01-06
申请人： Hyuk-Ju Ryu , Young-Wug Kim , Chang-Bong Oh , Hee-Sung Kang
发明人： Hyuk-Ju Ryu , Young-Wug Kim , Chang-Bong Oh , Hee-Sung Kang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L27/092 , H01L21/823842
摘要： In a CMOS semiconductor device using a silicon germanium gate and a method of fabricating the same, a gate insulating layer, a conductive electrode layer that is a seed layer, a silicon germanium electrode layer, and an amorphous conductive electrode layer are sequentially formed on a semiconductor substrate. A photolithographic process is then carried out to remove the silicon germanium electrode layer in the NMOS region, so that the silicon germanium layer is formed only in the PMOS region and is not formed in the NMOS region.
摘要翻译：在使用硅锗栅极的CMOS半导体器件及其制造方法中，栅极绝缘层，作为晶种层的导电电极层，硅锗电极层和非晶导电电极层依次形成在半导体衬底。然后进行光刻工艺以除去NMOS区域中的硅锗电极层，使得硅锗层仅形成在PMOS区域中，并且不形成在NMOS区域中。

3. 发明申请

US20060099766A1 Method of manufacturing a semiconductor device having a gate structure with low parasitic capacitance 失效
公开(公告)号：US20060099766A1
公开(公告)日：2006-05-11
申请号：US11313631
申请日：2005-12-21
申请人： You-Seung Jin , Jong-Hyon Ahn , Hyuk-Ju Ryu
发明人： You-Seung Jin , Jong-Hyon Ahn , Hyuk-Ju Ryu
IPC分类号： H01L21/336
CPC分类号： H01L29/4925 , H01L21/28035 , H01L21/28044 , H01L21/28052 , H01L21/28114 , H01L21/823425 , H01L21/823437 , H01L21/823443 , H01L21/823468 , H01L29/42376 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/78 , H01L29/7833
摘要： In a method of manufacturing a semiconductor device, a gate insulation layer and a gate electrode are sequentially formed on a substrate on which an active region is defined. A planarized layer is formed on the substrate including the gate electrode. The planarized layer partially removed, and an upper portion of the gate electrode is exposed. A silicon epitaxial layer is selectively formed only on the exposed gate electrode, and the planarized layer is completely removed. A gate spacer is formed along side surfaces of the gate electrode and the silicon epitaxial layer. A source/drain region is formed on a surface portion of the active region corresponding to the gate electrode. Since the silicon epitaxial layer is formed only on the gate region except the source/drain region, the gate resistance is stabilized and the parasitic capacitance between the gate electrode and the source/drain region is reduce.

4. 发明申请

US20050116297A1 CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof 有权
标题翻译： CMOS晶体管具有不同的PMOS和NMOS栅电极结构及其制造方法
公开(公告)号：US20050116297A1
公开(公告)日：2005-06-02
申请号：US11030245
申请日：2005-01-06
申请人： Hyuk-Ju Ryu , Young-Wug Kim , Chang-Bong Oh , Hee-Sung Kang
发明人： Hyuk-Ju Ryu , Young-Wug Kim , Chang-Bong Oh , Hee-Sung Kang
IPC分类号： H01L21/28 , H01L21/306 , H01L21/3065 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L21/336 , H01L29/76 , H01L31/062 , H01L31/119
CPC分类号： H01L27/092 , H01L21/823842
摘要： In a CMOS semiconductor device using a silicon germanium gate and a method of fabricating the same, a gate insulating layer, a conductive electrode layer that is a seed layer, a silicon germanium electrode layer, and an amorphous conductive electrode layer are sequentially formed on a semiconductor substrate. A photolithographic process is then carried out to remove the silicon germanium electrode layer in the NMOS region, so that the silicon germanium layer is formed only in the PMOS region and is not formed in the NMOS region.
摘要翻译：在使用硅锗栅极的CMOS半导体器件及其制造方法中，栅极绝缘层，作为晶种层的导电电极层，硅锗电极层和非晶导电电极层依次形成在半导体衬底。然后进行光刻工艺以除去NMOS区域中的硅锗电极层，使得硅锗层仅形成在PMOS区域中，并且不形成在NMOS区域中。

5. 发明申请

US20060027876A1 CMOS device with improved performance and method of fabricating the same 失效
标题翻译：具有改进性能的CMOS器件及其制造方法
公开(公告)号：US20060027876A1
公开(公告)日：2006-02-09
申请号：US11179434
申请日：2005-07-12
申请人： Mu-kyeng Jung , Hee-sung Kang , Hyuk-ju Ryu , Woo-young Chung , Kyung-soo Kim
发明人： Mu-kyeng Jung , Hee-sung Kang , Hyuk-ju Ryu , Woo-young Chung , Kyung-soo Kim
IPC分类号： H01L29/76
CPC分类号： H01L29/7846 , H01L21/823814 , H01L21/82385 , H01L29/7833 , H01L29/7843
摘要： A complementary metal oxide semiconductor (CMOS) device having improved performance includes a first device active region including at least one pair of transistor active regions wherein one transistor active region has a first width and the other transistor active region for forming a contact has a second width, a first gate arranged on the first device active region, a MOS transistor of a first conductivity type including a source/drain region of the first conductivity type formed in the first device active region, a second device active region having a third width greater than the first width, a second gate arranged on the second device active region, and a MOS transistor of a second conductivity type including a source/drain region of the second conductivity type formed in the second device active region.
摘要翻译：具有改进性能的互补金属氧化物半导体（CMOS）器件包括包括至少一对晶体管有源区的第一器件有源区，其中一个晶体管有源区具有第一宽度，而用于形成接触的另一晶体管有源区具有第二宽度布置在第一器件有源区上的第一栅极，第一导电类型的MOS晶体管，包括形成在第一器件有源区中的第一导电类型的源极/漏极区域，第三器件有源区域的第三宽度大于所述第一宽度，布置在所述第二器件有源区上的第二栅极和包括形成在所述第二器件有源区中的所述第二导电类型的源极/漏极区的第二导电类型的MOS晶体管。

6. 发明授权

US07323420B2 Method for manufacturing multi-thickness gate dielectric layer of semiconductor device 有权
标题翻译：制造半导体器件多层栅极电介质层的方法
公开(公告)号：US07323420B2
公开(公告)日：2008-01-29
申请号：US11652186
申请日：2007-01-11
申请人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
发明人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
IPC分类号： H01L21/302
CPC分类号： H01L29/42368 , H01L21/28194 , H01L21/28202 , H01L21/31116 , H01L21/31604 , H01L21/31616 , H01L21/3185 , H01L27/11 , H01L29/513 , H01L29/517 , H01L29/518
摘要： In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion of the second dielectric layer is selectively removed so as to selectively expose the first dielectric layer under the second dielectric layer. A portion of the exposed first dielectric layer is selectively removed so as to selectively expose the semiconductor substrate under the exposed first dielectric layer. Thereafter, a third dielectric layer having a thinner thickness than the first dielectric layer is formed on the exposed semiconductor substrate. As a result, a gate dielectric layer is formed to include a thick portion formed of the first dielectric layer and remaining second dielectric layer, a medium-thickness portion formed of the remaining first dielectric layer, and a thin portion formed of the third dielectric layer.
摘要翻译：在制造半导体器件的多层栅极电介质层的方法中，在半导体衬底上形成第一介电层。使用与构成第一电介质层上的第一电介质层的材料不同的电介质材料形成第二电介质层。选择性地去除第二电介质层的一部分，以选择性地暴露第二介电层下的第一介电层。选择性地去除暴露的第一介电层的一部分，以便在暴露的第一介电层下选择性地暴露半导体衬底。此后，在暴露的半导体衬底上形成厚度比第一电介质层薄的第三电介质层。结果，形成栅极电介质层，包括由第一电介质层和剩余的第二电介质层形成的厚部，由剩余的第一电介质层形成的中等厚度部分和由第三电介质层形成的薄壁部分。

7. 发明授权

US07285831B2 CMOS device with improved performance and method of fabricating the same 失效
标题翻译：具有改进性能的CMOS器件及其制造方法
公开(公告)号：US07285831B2
公开(公告)日：2007-10-23
申请号：US11179434
申请日：2005-07-12
申请人： Mu-kyeng Jung , Hee-sung Kang , Hyuk-ju Ryu , Woo-young Chung , Kyung-soo Kim
发明人： Mu-kyeng Jung , Hee-sung Kang , Hyuk-ju Ryu , Woo-young Chung , Kyung-soo Kim
IPC分类号： H01L29/94
CPC分类号： H01L29/7846 , H01L21/823814 , H01L21/82385 , H01L29/7833 , H01L29/7843
摘要： A complementary metal oxide semiconductor (CMOS) device having improved performance includes a first device active region including at least one pair of transistor active regions wherein one transistor active region has a first width and the other transistor active region for forming a contact has a second width, a first gate arranged on the first device active region, a MOS transistor of a first conductivity type including a source/drain region of the first conductivity type formed in the first device active region, a second device active region having a third width greater than the first width, a second gate arranged on the second device active region, and a MOS transistor of a second conductivity type including a source/drain region of the second conductivity type formed in the second device active region.
摘要翻译：具有改进性能的互补金属氧化物半导体（CMOS）器件包括包括至少一对晶体管有源区的第一器件有源区，其中一个晶体管有源区具有第一宽度，而用于形成接触的另一晶体管有源区具有第二宽度布置在第一器件有源区上的第一栅极，第一导电类型的MOS晶体管，包括形成在第一器件有源区中的第一导电类型的源极/漏极区域，第三器件有源区域的第三宽度大于所述第一宽度，布置在所述第二器件有源区上的第二栅极和包括形成在所述第二器件有源区中的所述第二导电类型的源极/漏极区的第二导电类型的MOS晶体管。

8. 发明申请

US20070117391A1 Method for manufacturing multi-thickness gate dielectric layer of semiconductor device 有权
标题翻译：制造半导体器件多层栅极电介质层的方法
公开(公告)号：US20070117391A1
公开(公告)日：2007-05-24
申请号：US11652186
申请日：2007-01-11
申请人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
发明人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L29/42368 , H01L21/28194 , H01L21/28202 , H01L21/31116 , H01L21/31604 , H01L21/31616 , H01L21/3185 , H01L27/11 , H01L29/513 , H01L29/517 , H01L29/518
摘要： In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion of the second dielectric layer is selectively removed so as to selectively expose the first dielectric layer under the second dielectric layer. A portion of the exposed first dielectric layer is selectively removed so as to selectively expose the semiconductor substrate under the exposed first dielectric layer. Thereafter, a third dielectric layer having a thinner thickness than the first dielectric layer is formed on the exposed semiconductor substrate. As a result, a gate dielectric layer is formed to include a thick portion formed of the first dielectric layer and remaining second dielectric layer, a medium-thickness portion formed of the remaining first dielectric layer, and a thin portion formed of the third dielectric layer.
摘要翻译：在制造半导体器件的多层栅极电介质层的方法中，在半导体衬底上形成第一介电层。使用与构成第一电介质层上的第一电介质层的材料不同的电介质材料形成第二电介质层。选择性地去除第二电介质层的一部分，以选择性地暴露第二介电层下的第一介电层。选择性地去除暴露的第一介电层的一部分，以便在暴露的第一介电层下选择性地暴露半导体衬底。此后，在暴露的半导体衬底上形成厚度比第一电介质层薄的第三电介质层。结果，形成栅极电介质层，包括由第一电介质层和剩余的第二电介质层形成的厚部，由剩余的第一电介质层形成的中等厚度部分和由第三电介质层形成的薄壁部分。

9. 发明申请

US20060240636A1 Trench isolation methods of semiconductor device 审中-公开
标题翻译：半导体器件的沟槽隔离方法
公开(公告)号：US20060240636A1
公开(公告)日：2006-10-26
申请号：US11358454
申请日：2006-02-21
申请人： Hyuk-Ju Ryu , Heon-Jong Shin , Hee-Sung Kang , Choong-Ryul Ryou , Mu-Kyeng Jung , Kyung-Soo Kim
发明人： Hyuk-Ju Ryu , Heon-Jong Shin , Hee-Sung Kang , Choong-Ryul Ryou , Mu-Kyeng Jung , Kyung-Soo Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/76237 , H01L21/76224 , H01L21/823878
摘要： In a trench isolation method, a semiconductor substrate having an N-MOS region and a P-MOS region is prepared. A first mask pattern exposing an N-MOS field region is formed on the N-MOS region, and a second mask pattern exposing a P-MOS field region is formed on the P-MOS region. A first photoresist pattern is formed to cover the P-MOS region and expose the N-MOS region. First impurity ions are implanted into the N-MOS region, using the first mask pattern and the first photoresist pattern as ion implantation masks, thereby forming a first impurity layer in the N-MOS field region. In this case, a portion of the first impurity layer is formed to extend below the first mask pattern. The first photoresist pattern is removed. The semiconductor substrate is etched using the first and second mask patterns as etch masks, thereby forming trenches in the N-MOS field region and the P-MOS field region and concurrently, forming a first impurity pattern of the first impurity layer remaining below the first mask pattern. A trench isolation layer filling the trenches is then formed.
摘要翻译：在沟槽隔离方法中，制备具有N-MOS区和P-MOS区的半导体衬底。在N-MOS区形成露出N-MOS场区的第一掩模图案，在P-MOS区形成露出P-MOS场区的第二掩模图案。形成第一光致抗蚀剂图案以覆盖P-MOS区域并暴露N-MOS区域。使用第一掩模图案和第一光致抗蚀剂图案作为离子注入掩模将第一杂质离子注入到N-MOS区域中，从而在N-MOS场区域中形成第一杂质层。在这种情况下，第一杂质层的一部分形成为延伸到第一掩模图案的下方。去除第一光致抗蚀剂图案。使用第一和第二掩模图案作为蚀刻掩模蚀刻半导体衬底，从而在N-MOS场区和P-MOS场区中形成沟槽，同时，形成第一杂质图案的第一杂质图案保留在第一掩模图案。然后形成填充沟槽的沟槽隔离层。

10. 发明授权

US06858907B2 Method of fabricating semiconductor device having notched gate 有权
标题翻译：制造具有开槽栅极的半导体器件的方法
公开(公告)号：US06858907B2
公开(公告)日：2005-02-22
申请号：US10114214
申请日：2002-04-02
申请人： Hyuk-Ju Ryu , Young-Gun Ko
发明人： Hyuk-Ju Ryu , Young-Gun Ko
IPC分类号： H01L21/338 , H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78 , H01L21/02
CPC分类号： H01L29/4983 , H01L21/28114 , H01L21/28123 , H01L29/6659 , H01L29/66598 , H01L29/7833
摘要： A semiconductor device includes: a silicon substrate; a source/drain region formed in the substrate including a lightly doped region and an adjacent heavily doped region, the depth of the heavily doped region being greater than the depth of the lightly doped region; a gate oxide layer on the silicon substrate; and a notched gate electrode on the substrate, the notched gate electrode including a notch along an outer side surface of a lower portion such that a top portion of the notched gate electrode is wider than the lower portion, the gate oxide layer extending between the interface of the notched gate electrode and the substrate, and a gate poly oxide layer provided along an outer side surface of the notched gate electrode and along an inner wall of the notch, a portion of the lightly doped region being under the notch.
摘要翻译：半导体器件包括：硅衬底; 形成在所述衬底中的源极/漏极区域，所述源极/漏极区域包括轻掺杂区域和相邻重掺杂区域，所述重掺杂区域的深度大于所述轻掺杂区域的深度; 硅衬底上的栅氧化层; 以及在基板上的缺口栅电极，所述带槽栅电极具有沿着下部的外侧面的切口，使得所述有槽栅电极的顶部比所述下部宽，所述栅极氧化物层在所述界面的栅极电极和衬底，以及沿着切口栅电极的外侧表面并沿着凹口的内壁设置的栅极多氧化物层，所述轻掺杂区域的一部分位于所述凹口下方。

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