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1. 发明授权

US07569456B2 MOS transistor with elevated source and drain structures and method of fabrication thereof 有权
标题翻译：具有升高的源极和漏极结构的MOS晶体管及其制造方法
公开(公告)号：US07569456B2
公开(公告)日：2009-08-04
申请号：US11726229
申请日：2007-03-21
申请人： Young-gun Ko , Chang-bong Oh
发明人： Young-gun Ko , Chang-bong Oh
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L29/665 , H01L29/66545 , H01L29/66621 , H01L29/7834
摘要： A transistor and method of formation thereof includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In doing so, the effective channel length is increased, while limiting dopant diffusion into the channel region. In this manner, performance characteristics of the transistor can be accurately determined by controlling the respective geometries (i.e. depths and widths) of the source/drain extension regions, the source/drain regions, the channel width and an optional trench formed in the underlying substrate. In the various embodiments, the source/drain regions and the source/drain extension regions may extend partially, or fully, through the epitaxial layer, or even into the underlying semiconductor substrate.
摘要翻译：晶体管及其形成方法包括源极和漏极延伸区域，其中掺杂剂到沟道区域的扩散被减轻或消除。这部分地通过将源极和漏极延伸区域提升到形成在下面的衬底上的外延层中来实现。在这样做时，有效沟道长度增加，同时限制掺杂剂扩散到沟道区。以这种方式，可以通过控制源极/漏极延伸区域，源极/漏极区域，沟道宽度和形成在下面的衬底中的可选沟槽的各自的几何形状（即，深度和宽度）来精确地确定晶体管的性能特性。在各种实施例中，源极/漏极区域和源极/漏极延伸区域可以部分地或完全地延伸穿过外延层，或者甚至延伸到下面的半导体衬底中。

2. 发明授权

US08482077B2 Semiconductor devices and methods for fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08482077B2
公开(公告)日：2013-07-09
申请号：US13102860
申请日：2011-05-06
申请人： Jongho Lee , Chang-Bong Oh , Ho Lee , Myungsun Kim
发明人： Jongho Lee , Chang-Bong Oh , Ho Lee , Myungsun Kim
IPC分类号： H01L29/78
CPC分类号： H01L21/823807 , H01L21/28238 , H01L21/823412 , H01L21/823462 , H01L21/823857 , H01L29/513 , H01L29/517
摘要： A semiconductor device includes a substrate including a first region and a second region each having an n-type region and a p-type region, wherein the n-type region in the first region includes a silicon channel, the p-type region in the first region includes a silicon germanium channel, and the n-type region and the p-type region in the second region respectively include a silicon channel. A first gate insulating pattern formed of a thermal oxide layer is disposed on the substrate of the n-type and p-type regions in the second region.
摘要翻译：半导体器件包括：衬底，包括第一区域和第二区域，每个区域具有n型区域和p型区域，其中第一区域中的n型区域包括硅沟道，第一区域包括硅锗沟道，并且第二区域中的n型区域和p型区域分别包括硅沟道。在第二区域中的n型和p型区域的基板上设置由热氧化物层形成的第一栅极绝缘图案。

3. 发明授权

US07838966B2 Semiconductor devices including resistor elements comprising a bridge and base elements and related methods 有权
标题翻译：包括电阻元件的半导体器件包括桥接器和基极元件以及相关方法
公开(公告)号：US07838966B2
公开(公告)日：2010-11-23
申请号：US11825181
申请日：2007-07-05
申请人： Xiao Quan Wang , Chang-Bong Oh , Seung-Hwan Lee
发明人： Xiao Quan Wang , Chang-Bong Oh , Seung-Hwan Lee
IPC分类号： H01L23/62
CPC分类号： H01L27/0802 , H01L28/20
摘要： A semiconductor device may include a resistance pattern including a resistance material on a substrate. The resistance pattern may include first and second spaced apart base elements, a bridge element, and first, second, third, and fourth extension elements. The first and second base elements may be substantially parallel, and the bridge element may be connected between respective center portions of the first and second spaced apart base elements. The first and second extension elements may be connected to opposite ends of the first base element and may extend toward the second base element, and the third and fourth extension elements may be connected to opposite ends of the second base element and may extend toward the first base element. Related methods are also discussed.
摘要翻译：半导体器件可以包括在基板上包括电阻材料的电阻图案。电阻图案可以包括第一和第二间隔开的基本元件，桥接元件以及第一，第二，第三和第四延伸元件。第一和第二基座元件可以是基本上平行的，并且桥接元件可以连接在第一和第二间隔开的基本元件的相应中心部分之间。第一和第二延伸元件可以连接到第一基座元件的相对端并且可以朝向第二基座元件延伸，并且第三和第四延伸元件可以连接到第二基座元件的相对端并且可以朝着第一基座元件基本元素还讨论了相关方法。

4. 发明授权

US07348636B2 CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof 有权
标题翻译： CMOS晶体管具有不同的PMOS和NMOS栅电极结构及其制造方法
公开(公告)号：US07348636B2
公开(公告)日：2008-03-25
申请号：US11030245
申请日：2005-01-06
申请人： Hyuk-Ju Ryu , Young-Wug Kim , Chang-Bong Oh , Hee-Sung Kang
发明人： Hyuk-Ju Ryu , Young-Wug Kim , Chang-Bong Oh , Hee-Sung Kang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L27/092 , H01L21/823842
摘要： In a CMOS semiconductor device using a silicon germanium gate and a method of fabricating the same, a gate insulating layer, a conductive electrode layer that is a seed layer, a silicon germanium electrode layer, and an amorphous conductive electrode layer are sequentially formed on a semiconductor substrate. A photolithographic process is then carried out to remove the silicon germanium electrode layer in the NMOS region, so that the silicon germanium layer is formed only in the PMOS region and is not formed in the NMOS region.
摘要翻译：在使用硅锗栅极的CMOS半导体器件及其制造方法中，栅极绝缘层，作为晶种层的导电电极层，硅锗电极层和非晶导电电极层依次形成在半导体衬底。然后进行光刻工艺以除去NMOS区域中的硅锗电极层，使得硅锗层仅形成在PMOS区域中，并且不形成在NMOS区域中。

5. 发明申请

US20050116297A1 CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof 有权
标题翻译： CMOS晶体管具有不同的PMOS和NMOS栅电极结构及其制造方法
公开(公告)号：US20050116297A1
公开(公告)日：2005-06-02
申请号：US11030245
申请日：2005-01-06
申请人： Hyuk-Ju Ryu , Young-Wug Kim , Chang-Bong Oh , Hee-Sung Kang
发明人： Hyuk-Ju Ryu , Young-Wug Kim , Chang-Bong Oh , Hee-Sung Kang
IPC分类号： H01L21/28 , H01L21/306 , H01L21/3065 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L21/336 , H01L29/76 , H01L31/062 , H01L31/119
CPC分类号： H01L27/092 , H01L21/823842
摘要： In a CMOS semiconductor device using a silicon germanium gate and a method of fabricating the same, a gate insulating layer, a conductive electrode layer that is a seed layer, a silicon germanium electrode layer, and an amorphous conductive electrode layer are sequentially formed on a semiconductor substrate. A photolithographic process is then carried out to remove the silicon germanium electrode layer in the NMOS region, so that the silicon germanium layer is formed only in the PMOS region and is not formed in the NMOS region.
摘要翻译：在使用硅锗栅极的CMOS半导体器件及其制造方法中，栅极绝缘层，作为晶种层的导电电极层，硅锗电极层和非晶导电电极层依次形成在半导体衬底。然后进行光刻工艺以除去NMOS区域中的硅锗电极层，使得硅锗层仅形成在PMOS区域中，并且不形成在NMOS区域中。

6. 发明申请

US20110272736A1 SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110272736A1
公开(公告)日：2011-11-10
申请号：US13102860
申请日：2011-05-06
申请人： JONGHO LEE , Chang-Bong Oh , Ho Lee , Myungsun Kim
发明人： JONGHO LEE , Chang-Bong Oh , Ho Lee , Myungsun Kim
IPC分类号： H01L29/165
CPC分类号： H01L21/823807 , H01L21/28238 , H01L21/823412 , H01L21/823462 , H01L21/823857 , H01L29/513 , H01L29/517
摘要： A semiconductor device includes a substrate including a first region and a second region each having an n-type region and a p-type region, wherein the n-type region in the first region includes a silicon channel, the p-type region in the first region includes a silicon germanium channel, and the n-type region and the p-type region in the second region respectively include a silicon channel. A first gate insulating pattern formed of a thermal oxide layer is disposed on the substrate of the n-type and p-type regions in the second region.
摘要翻译：半导体器件包括：衬底，包括第一区域和第二区域，每个区域具有n型区域和p型区域，其中第一区域中的n型区域包括硅沟道，第一区域包括硅锗沟道，并且第二区域中的n型区域和p型区域分别包括硅沟道。在第二区域中的n型和p型区域的基板上设置由热氧化物层形成的第一栅极绝缘图案。

7. 发明申请

US20080054405A1 Semiconductor devices including resistor elements and related methods 有权
标题翻译：半导体器件包括电阻元件及相关方法
公开(公告)号：US20080054405A1
公开(公告)日：2008-03-06
申请号：US11825181
申请日：2007-07-05
申请人： Xiao Quan Wang , Chang-Bong Oh , Seung-Hwan Lee
发明人： Xiao Quan Wang , Chang-Bong Oh , Seung-Hwan Lee
IPC分类号： H01L29/06 , H01L21/02
CPC分类号： H01L27/0802 , H01L28/20
摘要： A semiconductor device may include a resistance pattern including a resistance material on a substrate. The resistance pattern may include first and second spaced apart base elements, a bridge element, and first, second, third, and fourth extension elements. The first and second base elements may be substantially parallel, and the bridge element may be connected between respective center portions of the first and second spaced apart base elements. The first and second extension elements may be connected to opposite ends of the first base element and may extend toward the second base element, and the third and fourth extension elements may be connected to opposite ends of the second base element and may extend toward the first base element. Related methods are also discussed.
摘要翻译：半导体器件可以包括在基板上包括电阻材料的电阻图案。电阻图案可以包括第一和第二间隔开的基本元件，桥接元件以及第一，第二，第三和第四延伸元件。第一和第二基座元件可以是基本上平行的，并且桥接元件可以连接在第一和第二间隔开的基本元件的相应中心部分之间。第一和第二延伸元件可以连接到第一基座元件的相对端并且可以朝向第二基座元件延伸，并且第三和第四延伸元件可以连接到第二基座元件的相对端并且可以朝着第一基座元件基本元素还讨论了相关方法。

8. 发明授权

US07323420B2 Method for manufacturing multi-thickness gate dielectric layer of semiconductor device 有权
标题翻译：制造半导体器件多层栅极电介质层的方法
公开(公告)号：US07323420B2
公开(公告)日：2008-01-29
申请号：US11652186
申请日：2007-01-11
申请人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
发明人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
IPC分类号： H01L21/302
CPC分类号： H01L29/42368 , H01L21/28194 , H01L21/28202 , H01L21/31116 , H01L21/31604 , H01L21/31616 , H01L21/3185 , H01L27/11 , H01L29/513 , H01L29/517 , H01L29/518
摘要： In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion of the second dielectric layer is selectively removed so as to selectively expose the first dielectric layer under the second dielectric layer. A portion of the exposed first dielectric layer is selectively removed so as to selectively expose the semiconductor substrate under the exposed first dielectric layer. Thereafter, a third dielectric layer having a thinner thickness than the first dielectric layer is formed on the exposed semiconductor substrate. As a result, a gate dielectric layer is formed to include a thick portion formed of the first dielectric layer and remaining second dielectric layer, a medium-thickness portion formed of the remaining first dielectric layer, and a thin portion formed of the third dielectric layer.
摘要翻译：在制造半导体器件的多层栅极电介质层的方法中，在半导体衬底上形成第一介电层。使用与构成第一电介质层上的第一电介质层的材料不同的电介质材料形成第二电介质层。选择性地去除第二电介质层的一部分，以选择性地暴露第二介电层下的第一介电层。选择性地去除暴露的第一介电层的一部分，以便在暴露的第一介电层下选择性地暴露半导体衬底。此后，在暴露的半导体衬底上形成厚度比第一电介质层薄的第三电介质层。结果，形成栅极电介质层，包括由第一电介质层和剩余的第二电介质层形成的厚部，由剩余的第一电介质层形成的中等厚度部分和由第三电介质层形成的薄壁部分。

9. 发明申请

US20070166926A1 MOS transistor with elevated source and drain structures and method of fabrication thereof 有权
公开(公告)号：US20070166926A1
公开(公告)日：2007-07-19
申请号：US11726229
申请日：2007-03-21
申请人： Young-gun Ko , Chang-bong Oh
发明人： Young-gun Ko , Chang-bong Oh
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L29/665 , H01L29/66545 , H01L29/66621 , H01L29/7834
摘要： A transistor and method of formation thereof includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In doing so, the effective channel length is increased, while limiting dopant diffusion into the channel region. In this manner, performance characteristics of the transistor can be accurately determined by controlling the respective geometries (i.e. depths and widths) of the source/drain extension regions, the source/drain regions, the channel width and an optional trench formed in the underlying substrate. In the various embodiments, the source/drain regions and the source/drain extension regions may extend partially, or fully, through the epitaxial layer, or even into the underlying semiconductor substrate.

10. 发明申请

US20070117391A1 Method for manufacturing multi-thickness gate dielectric layer of semiconductor device 有权
标题翻译：制造半导体器件多层栅极电介质层的方法
公开(公告)号：US20070117391A1
公开(公告)日：2007-05-24
申请号：US11652186
申请日：2007-01-11
申请人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
发明人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L29/42368 , H01L21/28194 , H01L21/28202 , H01L21/31116 , H01L21/31604 , H01L21/31616 , H01L21/3185 , H01L27/11 , H01L29/513 , H01L29/517 , H01L29/518
摘要： In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion of the second dielectric layer is selectively removed so as to selectively expose the first dielectric layer under the second dielectric layer. A portion of the exposed first dielectric layer is selectively removed so as to selectively expose the semiconductor substrate under the exposed first dielectric layer. Thereafter, a third dielectric layer having a thinner thickness than the first dielectric layer is formed on the exposed semiconductor substrate. As a result, a gate dielectric layer is formed to include a thick portion formed of the first dielectric layer and remaining second dielectric layer, a medium-thickness portion formed of the remaining first dielectric layer, and a thin portion formed of the third dielectric layer.
摘要翻译：在制造半导体器件的多层栅极电介质层的方法中，在半导体衬底上形成第一介电层。使用与构成第一电介质层上的第一电介质层的材料不同的电介质材料形成第二电介质层。选择性地去除第二电介质层的一部分，以选择性地暴露第二介电层下的第一介电层。选择性地去除暴露的第一介电层的一部分，以便在暴露的第一介电层下选择性地暴露半导体衬底。此后，在暴露的半导体衬底上形成厚度比第一电介质层薄的第三电介质层。结果，形成栅极电介质层，包括由第一电介质层和剩余的第二电介质层形成的厚部，由剩余的第一电介质层形成的中等厚度部分和由第三电介质层形成的薄壁部分。

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