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1. 发明授权

US07179750B2 Method for manufacturing multi-thickness gate dielectric layer of semiconductor device 有权
公开(公告)号：US07179750B2
公开(公告)日：2007-02-20
申请号：US10685738
申请日：2003-10-15
申请人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
发明人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
IPC分类号： H01L21/302
CPC分类号： H01L29/42368 , H01L21/28194 , H01L21/28202 , H01L21/31116 , H01L21/31604 , H01L21/31616 , H01L21/3185 , H01L27/11 , H01L29/513 , H01L29/517 , H01L29/518
摘要： In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion of the second dielectric layer is selectively removed so as to selectively expose the first dielectric layer under the second dielectric layer. A portion of the exposed first dielectric layer is selectively removed so as to selectively expose the semiconductor substrate under the exposed first dielectric layer. Thereafter, a third dielectric layer having a thinner thickness than the first dielectric layer is formed on the exposed semiconductor substrate. As a result, a gate dielectric layer is formed to include a thick portion formed of the first dielectric layer and remaining second dielectric layer, a medium-thickness portion formed of the remaining first dielectric layer, and a thin portion formed of the third dielectric layer.

2. 发明授权

US07323420B2 Method for manufacturing multi-thickness gate dielectric layer of semiconductor device 有权
标题翻译：制造半导体器件多层栅极电介质层的方法
公开(公告)号：US07323420B2
公开(公告)日：2008-01-29
申请号：US11652186
申请日：2007-01-11
申请人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
发明人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
IPC分类号： H01L21/302
CPC分类号： H01L29/42368 , H01L21/28194 , H01L21/28202 , H01L21/31116 , H01L21/31604 , H01L21/31616 , H01L21/3185 , H01L27/11 , H01L29/513 , H01L29/517 , H01L29/518
摘要： In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion of the second dielectric layer is selectively removed so as to selectively expose the first dielectric layer under the second dielectric layer. A portion of the exposed first dielectric layer is selectively removed so as to selectively expose the semiconductor substrate under the exposed first dielectric layer. Thereafter, a third dielectric layer having a thinner thickness than the first dielectric layer is formed on the exposed semiconductor substrate. As a result, a gate dielectric layer is formed to include a thick portion formed of the first dielectric layer and remaining second dielectric layer, a medium-thickness portion formed of the remaining first dielectric layer, and a thin portion formed of the third dielectric layer.
摘要翻译：在制造半导体器件的多层栅极电介质层的方法中，在半导体衬底上形成第一介电层。使用与构成第一电介质层上的第一电介质层的材料不同的电介质材料形成第二电介质层。选择性地去除第二电介质层的一部分，以选择性地暴露第二介电层下的第一介电层。选择性地去除暴露的第一介电层的一部分，以便在暴露的第一介电层下选择性地暴露半导体衬底。此后，在暴露的半导体衬底上形成厚度比第一电介质层薄的第三电介质层。结果，形成栅极电介质层，包括由第一电介质层和剩余的第二电介质层形成的厚部，由剩余的第一电介质层形成的中等厚度部分和由第三电介质层形成的薄壁部分。

3. 发明申请

US20070117391A1 Method for manufacturing multi-thickness gate dielectric layer of semiconductor device 有权
标题翻译：制造半导体器件多层栅极电介质层的方法
公开(公告)号：US20070117391A1
公开(公告)日：2007-05-24
申请号：US11652186
申请日：2007-01-11
申请人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
发明人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L29/42368 , H01L21/28194 , H01L21/28202 , H01L21/31116 , H01L21/31604 , H01L21/31616 , H01L21/3185 , H01L27/11 , H01L29/513 , H01L29/517 , H01L29/518
摘要： In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion of the second dielectric layer is selectively removed so as to selectively expose the first dielectric layer under the second dielectric layer. A portion of the exposed first dielectric layer is selectively removed so as to selectively expose the semiconductor substrate under the exposed first dielectric layer. Thereafter, a third dielectric layer having a thinner thickness than the first dielectric layer is formed on the exposed semiconductor substrate. As a result, a gate dielectric layer is formed to include a thick portion formed of the first dielectric layer and remaining second dielectric layer, a medium-thickness portion formed of the remaining first dielectric layer, and a thin portion formed of the third dielectric layer.
摘要翻译：在制造半导体器件的多层栅极电介质层的方法中，在半导体衬底上形成第一介电层。使用与构成第一电介质层上的第一电介质层的材料不同的电介质材料形成第二电介质层。选择性地去除第二电介质层的一部分，以选择性地暴露第二介电层下的第一介电层。选择性地去除暴露的第一介电层的一部分，以便在暴露的第一介电层下选择性地暴露半导体衬底。此后，在暴露的半导体衬底上形成厚度比第一电介质层薄的第三电介质层。结果，形成栅极电介质层，包括由第一电介质层和剩余的第二电介质层形成的厚部，由剩余的第一电介质层形成的中等厚度部分和由第三电介质层形成的薄壁部分。

4. 发明授权

US07285831B2 CMOS device with improved performance and method of fabricating the same 失效
标题翻译：具有改进性能的CMOS器件及其制造方法
公开(公告)号：US07285831B2
公开(公告)日：2007-10-23
申请号：US11179434
申请日：2005-07-12
申请人： Mu-kyeng Jung , Hee-sung Kang , Hyuk-ju Ryu , Woo-young Chung , Kyung-soo Kim
发明人： Mu-kyeng Jung , Hee-sung Kang , Hyuk-ju Ryu , Woo-young Chung , Kyung-soo Kim
IPC分类号： H01L29/94
CPC分类号： H01L29/7846 , H01L21/823814 , H01L21/82385 , H01L29/7833 , H01L29/7843
摘要： A complementary metal oxide semiconductor (CMOS) device having improved performance includes a first device active region including at least one pair of transistor active regions wherein one transistor active region has a first width and the other transistor active region for forming a contact has a second width, a first gate arranged on the first device active region, a MOS transistor of a first conductivity type including a source/drain region of the first conductivity type formed in the first device active region, a second device active region having a third width greater than the first width, a second gate arranged on the second device active region, and a MOS transistor of a second conductivity type including a source/drain region of the second conductivity type formed in the second device active region.
摘要翻译：具有改进性能的互补金属氧化物半导体（CMOS）器件包括包括至少一对晶体管有源区的第一器件有源区，其中一个晶体管有源区具有第一宽度，而用于形成接触的另一晶体管有源区具有第二宽度布置在第一器件有源区上的第一栅极，第一导电类型的MOS晶体管，包括形成在第一器件有源区中的第一导电类型的源极/漏极区域，第三器件有源区域的第三宽度大于所述第一宽度，布置在所述第二器件有源区上的第二栅极和包括形成在所述第二器件有源区中的所述第二导电类型的源极/漏极区的第二导电类型的MOS晶体管。

5. 发明申请

US20060027876A1 CMOS device with improved performance and method of fabricating the same 失效
标题翻译：具有改进性能的CMOS器件及其制造方法
公开(公告)号：US20060027876A1
公开(公告)日：2006-02-09
申请号：US11179434
申请日：2005-07-12
申请人： Mu-kyeng Jung , Hee-sung Kang , Hyuk-ju Ryu , Woo-young Chung , Kyung-soo Kim
发明人： Mu-kyeng Jung , Hee-sung Kang , Hyuk-ju Ryu , Woo-young Chung , Kyung-soo Kim
IPC分类号： H01L29/76
CPC分类号： H01L29/7846 , H01L21/823814 , H01L21/82385 , H01L29/7833 , H01L29/7843
摘要： A complementary metal oxide semiconductor (CMOS) device having improved performance includes a first device active region including at least one pair of transistor active regions wherein one transistor active region has a first width and the other transistor active region for forming a contact has a second width, a first gate arranged on the first device active region, a MOS transistor of a first conductivity type including a source/drain region of the first conductivity type formed in the first device active region, a second device active region having a third width greater than the first width, a second gate arranged on the second device active region, and a MOS transistor of a second conductivity type including a source/drain region of the second conductivity type formed in the second device active region.
摘要翻译：具有改进性能的互补金属氧化物半导体（CMOS）器件包括包括至少一对晶体管有源区的第一器件有源区，其中一个晶体管有源区具有第一宽度，而用于形成接触的另一晶体管有源区具有第二宽度布置在第一器件有源区上的第一栅极，第一导电类型的MOS晶体管，包括形成在第一器件有源区中的第一导电类型的源极/漏极区域，第三器件有源区域的第三宽度大于所述第一宽度，布置在所述第二器件有源区上的第二栅极和包括形成在所述第二器件有源区中的所述第二导电类型的源极/漏极区的第二导电类型的MOS晶体管。

6. 发明授权

US06833766B2 Adaptive loop gain control circuit for voltage controlled oscillator 失效
标题翻译：用于压控振荡器的自适应环路增益控制电路
公开(公告)号：US06833766B2
公开(公告)日：2004-12-21
申请号：US10410829
申请日：2003-04-09
申请人： Kwi-dong Kim , Jong-kee Kwon , Hee-bum Jung , Kyung-soo Kim
发明人： Kwi-dong Kim , Jong-kee Kwon , Hee-bum Jung , Kyung-soo Kim
IPC分类号： H03L700
CPC分类号： H03L1/00 , H03L7/0995
摘要： There is provided an adaptive loop gain control circuit for a voltage-controlled oscillator (VCO). The adaptive loop gain control circuit for a voltage-controlled oscillator (VCO) includes a detected voltage generating unit which generates a detected voltage signal according to changes in an operating voltage and an operating temperature, and a control circuit unit which outputs an oscillation control current signal according to the detected voltage signal and an input control voltage signal. The adaptive loop gain control circuit for a voltage-controlled oscillator (VCO) compensates for an oscillation control current according to changes in operating voltage and temperature and compensates for the gain of a phase locked loop (PLL) system, thereby ensuring high operating stability in the PLL circuit.
摘要翻译：提供了一种用于压控振荡器（VCO）的自适应环路增益控制电路。用于压控振荡器（VCO）的自适应环路增益控制电路包括：检测电压产生单元，其根据工作电压和工作温度的变化产生检测的电压信号;以及控制电路单元，其输出振荡控制电流信号根据检测到的电压信号和输入控制电压信号。用于压控振荡器（VCO）的自适应环路增益控制电路根据工作电压和温度的变化补偿振荡控制电流，并补偿锁相环（PLL）系统的增益，从而确保在 PLL电路。

7. 发明授权

US5980188A Semiconductor manufacturing device including sensor for sensing mis-loading of a wafer 失效
标题翻译：半导体制造装置包括用于感测晶片错误加载的传感器
公开(公告)号：US5980188A
公开(公告)日：1999-11-09
申请号：US977883
申请日：1997-11-28
申请人： Yong-in Ko , Jae-sang Park , Kyung-soo Kim , Jae-bum Park
发明人： Yong-in Ko , Jae-sang Park , Kyung-soo Kim , Jae-bum Park
IPC分类号： B65G1/00 , B65G43/08 , B65G49/07 , H01L21/66 , H01L21/673 , H01L21/677 , H01L21/68 , G01B11/04
CPC分类号： H01L21/67259 , H01L21/67326 , Y10S414/136 , Y10S414/138
摘要： An apparatus and method for carrying wafers through a multi-step process for producing a semiconductor, without using a cassette, where the apparatus senses whether a wafer is mis-loaded. The apparatus includes a plurality of optical sensors positioned above the wafers for sensing whether a wafer is mis-loaded by transmitting light past circumferential edges of the wafers.
摘要翻译：一种用于在不使用盒的情况下通过用于制造半导体的多步骤工艺来承载晶片的装置和方法，其中该装置感测晶片是否被误装载。该装置包括位于晶片上方的多个光学传感器，用于通过将光透过晶片的圆周边缘传输来检测晶片是否被误加载。

8. 发明授权

US07550347B2 Methods of forming integrated circuit device gate structures 有权
标题翻译：形成集成电路器件门结构的方法
公开(公告)号：US07550347B2
公开(公告)日：2009-06-23
申请号：US11510059
申请日：2006-08-25
申请人： Sam-jong Choi , Yong-kwon Kim , Kyoo-chul Cho , Kyung-soo Kim , Jae-ryong Jung , Tae-soo Kang , Sang-Sig Kim
发明人： Sam-jong Choi , Yong-kwon Kim , Kyoo-chul Cho , Kyung-soo Kim , Jae-ryong Jung , Tae-soo Kang , Sang-Sig Kim
IPC分类号： H01L21/00
CPC分类号： H01L21/28282 , B82Y10/00 , H01L29/42324 , H01L29/42332 , H01L29/792 , H01L29/7923
摘要： Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.
摘要翻译：形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。将元素周期表第4组的选定元素的离子注入到第一电介质层中，以在第一电介质层中形成具有小于约0.5厘米每秒（cm 2 / s）的热扩散率的离子，从而在第一电介质层中形成电荷存储区，在电荷存储区域下的隧道介电层。金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。还提供用于集成电路器件和存储单元的栅极结构。

9. 发明申请

US20070128846A1 Integrated circuit device gate structures and methods of forming the same 有权
标题翻译：集成电路器件栅极结构及其形成方法
公开(公告)号：US20070128846A1
公开(公告)日：2007-06-07
申请号：US11510059
申请日：2006-08-25
申请人： Sam-jong Choi , Yong-kwon Kim , Kyoo-chul Cho , Kyung-soo Kim , Jae-ryong Jung , Tae-soo Kang , Sang-Sig Kim
发明人： Sam-jong Choi , Yong-kwon Kim , Kyoo-chul Cho , Kyung-soo Kim , Jae-ryong Jung , Tae-soo Kang , Sang-Sig Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/28282 , B82Y10/00 , H01L29/42324 , H01L29/42332 , H01L29/792 , H01L29/7923
摘要： Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.
摘要翻译：形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。将元素周期表第4组的选定元素的离子注入到第一介电层中，并且具有小于约0.5厘米每秒（cm 2 / s）的热扩散率，从而形成电荷存储区域，在电荷存储区域下方具有隧道介电层。金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。还提供用于集成电路器件和存储单元的栅极结构。

10. 发明授权

US07194018B2 Apparatus for searching multipath in spread spectrum communications system and method thereof 有权
标题翻译：用于在扩频通信系统中搜索多路径的装置及其方法
公开(公告)号：US07194018B2
公开(公告)日：2007-03-20
申请号：US10211416
申请日：2002-08-01
申请人： Kyung-tae Han , Ik-soo Eo , Hae-bum Jung , Kyung-soo Kim
发明人： Kyung-tae Han , Ik-soo Eo , Hae-bum Jung , Kyung-soo Kim
IPC分类号： H04B1/69
CPC分类号： H04B1/7113 , H04B1/7117
摘要： A multipath searching device includes a radio front-end for converting a received radio signal into a baseband signal and for outputting the baseband signal. A profile calculating unit is included for calculating and outputting the multipath profile of the baseband signal. A first detector determines whether or not the radio signal traveled along a multipath is having a short-delay path by comparing the peak value of the multipath profile with a profile value of a predetermined position time interval before or after the peak of the multipath profile. A path selector receives the multipath profile and the detection result of the first detector, generates time delay information for each path, and separates many paths along which the radio signal traveled. A receiving unit receives the time delay information of the paths, despreads the baseband signal, and combines despread signals.
摘要翻译：多路径搜索装置包括用于将接收的无线电信号转换为基带信号并用于输出基带信号的无线电前端。包括用于计算和输出基带信号的多径分布的简档计算单元。第一检测器通过将多径分布的峰值与多径分布的峰值之前或之后的预定位置时间间隔的轮廓值进行比较来确定沿着多路径行进的无线电信号是否具有短延迟路径。路径选择器接收多路径分布和第一检测器的检测结果，为每个路径生成时间延迟信息，并分离出无线电信号行进的许多路径。接收单元接收路径的时间延迟信息，解扩基带信号，并组合解扩信号。

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