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1. 发明授权

US07179750B2 Method for manufacturing multi-thickness gate dielectric layer of semiconductor device 有权
公开(公告)号：US07179750B2
公开(公告)日：2007-02-20
申请号：US10685738
申请日：2003-10-15
申请人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
发明人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
IPC分类号： H01L21/302
CPC分类号： H01L29/42368 , H01L21/28194 , H01L21/28202 , H01L21/31116 , H01L21/31604 , H01L21/31616 , H01L21/3185 , H01L27/11 , H01L29/513 , H01L29/517 , H01L29/518
摘要： In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion of the second dielectric layer is selectively removed so as to selectively expose the first dielectric layer under the second dielectric layer. A portion of the exposed first dielectric layer is selectively removed so as to selectively expose the semiconductor substrate under the exposed first dielectric layer. Thereafter, a third dielectric layer having a thinner thickness than the first dielectric layer is formed on the exposed semiconductor substrate. As a result, a gate dielectric layer is formed to include a thick portion formed of the first dielectric layer and remaining second dielectric layer, a medium-thickness portion formed of the remaining first dielectric layer, and a thin portion formed of the third dielectric layer.

2. 发明授权

US07323420B2 Method for manufacturing multi-thickness gate dielectric layer of semiconductor device 有权
标题翻译：制造半导体器件多层栅极电介质层的方法
公开(公告)号：US07323420B2
公开(公告)日：2008-01-29
申请号：US11652186
申请日：2007-01-11
申请人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
发明人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
IPC分类号： H01L21/302
CPC分类号： H01L29/42368 , H01L21/28194 , H01L21/28202 , H01L21/31116 , H01L21/31604 , H01L21/31616 , H01L21/3185 , H01L27/11 , H01L29/513 , H01L29/517 , H01L29/518
摘要： In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion of the second dielectric layer is selectively removed so as to selectively expose the first dielectric layer under the second dielectric layer. A portion of the exposed first dielectric layer is selectively removed so as to selectively expose the semiconductor substrate under the exposed first dielectric layer. Thereafter, a third dielectric layer having a thinner thickness than the first dielectric layer is formed on the exposed semiconductor substrate. As a result, a gate dielectric layer is formed to include a thick portion formed of the first dielectric layer and remaining second dielectric layer, a medium-thickness portion formed of the remaining first dielectric layer, and a thin portion formed of the third dielectric layer.
摘要翻译：在制造半导体器件的多层栅极电介质层的方法中，在半导体衬底上形成第一介电层。使用与构成第一电介质层上的第一电介质层的材料不同的电介质材料形成第二电介质层。选择性地去除第二电介质层的一部分，以选择性地暴露第二介电层下的第一介电层。选择性地去除暴露的第一介电层的一部分，以便在暴露的第一介电层下选择性地暴露半导体衬底。此后，在暴露的半导体衬底上形成厚度比第一电介质层薄的第三电介质层。结果，形成栅极电介质层，包括由第一电介质层和剩余的第二电介质层形成的厚部，由剩余的第一电介质层形成的中等厚度部分和由第三电介质层形成的薄壁部分。

3. 发明申请

US20070117391A1 Method for manufacturing multi-thickness gate dielectric layer of semiconductor device 有权
标题翻译：制造半导体器件多层栅极电介质层的方法
公开(公告)号：US20070117391A1
公开(公告)日：2007-05-24
申请号：US11652186
申请日：2007-01-11
申请人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
发明人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L29/42368 , H01L21/28194 , H01L21/28202 , H01L21/31116 , H01L21/31604 , H01L21/31616 , H01L21/3185 , H01L27/11 , H01L29/513 , H01L29/517 , H01L29/518
摘要： In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion of the second dielectric layer is selectively removed so as to selectively expose the first dielectric layer under the second dielectric layer. A portion of the exposed first dielectric layer is selectively removed so as to selectively expose the semiconductor substrate under the exposed first dielectric layer. Thereafter, a third dielectric layer having a thinner thickness than the first dielectric layer is formed on the exposed semiconductor substrate. As a result, a gate dielectric layer is formed to include a thick portion formed of the first dielectric layer and remaining second dielectric layer, a medium-thickness portion formed of the remaining first dielectric layer, and a thin portion formed of the third dielectric layer.
摘要翻译：在制造半导体器件的多层栅极电介质层的方法中，在半导体衬底上形成第一介电层。使用与构成第一电介质层上的第一电介质层的材料不同的电介质材料形成第二电介质层。选择性地去除第二电介质层的一部分，以选择性地暴露第二介电层下的第一介电层。选择性地去除暴露的第一介电层的一部分，以便在暴露的第一介电层下选择性地暴露半导体衬底。此后，在暴露的半导体衬底上形成厚度比第一电介质层薄的第三电介质层。结果，形成栅极电介质层，包括由第一电介质层和剩余的第二电介质层形成的厚部，由剩余的第一电介质层形成的中等厚度部分和由第三电介质层形成的薄壁部分。

4. 发明授权

US6074907A Method of manufacturing capacitor for analog function 失效
标题翻译：制造模拟功能的电容器的方法
公开(公告)号：US6074907A
公开(公告)日：2000-06-13
申请号：US69710
申请日：1998-04-29
申请人： Chang-bong Oh , Young-wug Kim
发明人： Chang-bong Oh , Young-wug Kim
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/70 , H01L21/302 , H01L21/304
CPC分类号： H01L28/60
摘要： A method of manufacturing a capacitor whose top and bottom electrodes have the nearly equal doping concentrations. In the method, a top surface of the capacitor top electrode is polished by a CMP (chemical mechanical polishing) and then doped using the same doping process as the capacitor bottom electrode, so that other elements can be isolated during the doping process. After forming the capacitor bottom electrode, thermal oxidation is performed so that the injected impurity ions of the capacitor bottom electrode are segregated toward a top surface portion thereof. With this method, a doping concentration at the top surface portion of the capacitor bottom electrode becomes higher than that at other portions thereof, and thereby the capacitor top and bottom electrodes may have a nearly same doping concentration at the interface therebetween.
摘要翻译：一种制造其顶电极和底电极具有几乎相等的掺杂浓度的电容器的方法。在该方法中，通过CMP（化学机械抛光）对电容器顶部电极的顶表面进行抛光，然后使用与电容器底部电极相同的掺杂工艺进行掺杂，使得在掺杂过程中可以隔离其它元件。在形成电容器底部电极之后，进行热氧化，使得电容器底部电极的注入的杂质离子朝向其顶面部分偏析。通过这种方法，电容器底部电极的顶表面部分的掺杂浓度变得高于其他部分的掺杂浓度，因此电容器顶部和底部电极在它们之间的界面处可能具有几乎相同的掺杂浓度。

5. 发明授权

US06900503B2 SRAM formed on SOI substrate 有权
标题翻译： SRAM形成在SOI衬底上
公开(公告)号：US06900503B2
公开(公告)日：2005-05-31
申请号：US10649222
申请日：2003-08-26
申请人： Chang-bong Oh , Young-wug Kim
发明人： Chang-bong Oh , Young-wug Kim
IPC分类号： H01L27/08 , G11C11/412 , H01L21/8238 , H01L21/8244 , H01L21/84 , H01L27/092 , H01L27/11 , H01L27/12 , H01L29/786
CPC分类号： H01L27/11 , H01L21/84 , H01L27/1104 , H01L27/1203 , Y10S257/903
摘要： An SRAM capable of reducing the overall area consumed by the circuit and capable of improving the mobility and operational characteristics of a PMOS transistor is provided. The SRAM is formed on an SOI substrate having first and second active areas. A first access NMOS transistor and a first inverter, which is constituted by a first drive NMOS transistor and a first load PMOS transistor, are formed on the first active area of the SOI substrate. A second access NMOS transistor and a second inverter, which is constituted by a first drive NMOS transistor and a first load PMOS transistor, are formed on the second active area of the SOI substrate. Here, the channels of the first and second load PMOS transistors extend so that carriers move in a [110] silicon crystallization growth direction. In each active area, the drain (or source) of an access NMOS transistor, the drain of a drive NMOS transistor, and the drain of a load PMOS transistor contact one another in a shared region. Because the SRAM is formed on the SOI substrate, the size of the resulting chip can be reduced. Also, because the channels of the first and second load PMOS transistors extend so that carriers move in the [110] silicon crystallization growth direction, the mobility of the PMOS transistors is improved.
摘要翻译：提供了能够减小电路消耗的整体面积并能够提高PMOS晶体管的迁移率和操作特性的SRAM。 SRAM形成在具有第一和第二有源区的SOI衬底上。在SOI衬底的第一有源区上形成由第一驱动NMOS晶体管和第一负载PMOS晶体管构成的第一存取NMOS晶体管和第一反相器。在SOI衬底的第二有源区上形成由第一驱动NMOS晶体管和第一负载PMOS晶体管构成的第二存取NMOS晶体管和第二反相器。这里，第一和第二负载PMOS晶体管的沟道延伸使得载流子沿[110]硅结晶生长方向移动。在每个有效区域中，存取NMOS晶体管的漏极（或源极），驱动NMOS晶体管的漏极和负载PMOS晶体管的漏极在共享区域中彼此接触。因为SRAM形成在SOI衬底上，所以可以减小所得到的芯片的尺寸。此外，由于第一和第二负载PMOS晶体管的沟道延伸使得载流子在[110]硅结晶生长方向上移动，所以提高了PMOS晶体管的迁移率。

6. 发明授权

US06794716B2 SOI MOSFET having body contact for preventing floating body effect and method of fabricating the same 有权
标题翻译：具有用于防止浮体效应的身体接触的SOI MOSFET及其制造方法
公开(公告)号：US06794716B2
公开(公告)日：2004-09-21
申请号：US09924787
申请日：2001-08-08
申请人： Sung-bae Park , Jun Kim , Eun-han Kim , Hee-sung Kang , Young-wug Kim
发明人： Sung-bae Park , Jun Kim , Eun-han Kim , Hee-sung Kang , Young-wug Kim
IPC分类号： H01L2701
CPC分类号： H01L29/78615 , H01L29/78612
摘要： An SOI MOSFET having a body contact for preventing the floating body effect is provided. The body contact is a trench perforating a body and a buried oxide layer to a semiconductor substrate. The trench is filled with a conductive material to electrically connect the body to the semiconductor substrate. Impurity ions are implanted into a predetermined region of the semiconductor substrate in contact with the lower portion of the body contact to form an ohmic contact. In the SOI MOSFET, an additional metal interconnection line is not needed to supply power to the body. Also, malfunction of a circuit due to stray capacitance of a contact can be prevented.
摘要翻译：提供了具有用于防止浮体效应的身体接触的SOI MOSFET。身体接触是将半体衬底穿孔的沟槽和掩埋氧化物层。沟槽填充有导电材料以将本体电连接到半导体衬底。将杂质离子注入到与身体接触的下部接触的半导体衬底的预定区域中以形成欧姆接触。在SOI MOSFET中，不需要额外的金属互连线来为电源供电。此外，可以防止由于接触的杂散电容引起的电路故障。

7. 发明授权

US06492260B1 Method of fabricating damascene metal wiring 失效
标题翻译：制造镶嵌金属布线的方法
公开(公告)号：US06492260B1
公开(公告)日：2002-12-10
申请号：US09447466
申请日：1999-11-22
申请人： Young-wug Kim , Kyung-tae Lee
发明人： Young-wug Kim , Kyung-tae Lee
IPC分类号： H01L214763
CPC分类号： H01L21/7684 , H01L21/76834
摘要： A method of forming damascene wiring without dishing and erosion employs a dummy layer to slow or delay polishing in selected regions and thereby prevent dishing and erosion of the damascene wiring. The dummy layer is above wide damascene regions and areas containing closely packed damascene regions. Therefore, non-uniform sheet resistance of the damascene metal wiring and electro-migration due to an increase in the local current density of the metal wiring can be prevented.
摘要翻译：在不进行凹陷和侵蚀的情况下形成镶嵌布线的方法使用虚拟层来减缓或延迟所选区域中的抛光，从而防止镶嵌布线的凹陷和侵蚀。虚拟层位于宽大的镶嵌区域和包含紧密堆积的镶嵌区域的区域之上。因此，可以防止由金属布线的局部电流密度的增加引起的非镶嵌金属布线的非均匀的薄层电阻和电迁移。

8. 发明授权

US5674782A Method for efficiently removing by-products produced in dry-etching 失效
标题翻译：有效去除在干蚀刻中产生的副产物的方法
公开(公告)号：US5674782A
公开(公告)日：1997-10-07
申请号：US611432
申请日：1996-03-04
申请人： Nae-in Lee , Moon-han Park , Young-wug Kim , Kwan-young Oh
发明人： Nae-in Lee , Moon-han Park , Young-wug Kim , Kwan-young Oh
IPC分类号： H01L21/02 , H01L21/28 , H01L21/3213
CPC分类号： H01L21/02071 , H01L21/28061 , H01L21/32135
摘要： A method for efficiently removing by-products produced in dry-etching a fabricated structure of a semiconductor device, particularly, a polycide structure. The method includes the steps of sequentially forming a polysilicon layer and a refractory metal silicide layer to overlie previously fabricated structures on a semiconductor substrate, dry-etching the polysilicon layer and the refractory metal silicide layer to form a patterned polysilicon layer and a patterned refractory metal silicide layer, and thermal treating the resultant structure to remove at least one kind of by-product produced in the dry-etching step at a temperature higher than the boiling point of any by-product.
摘要翻译：一种用于有效地除去在干法蚀刻半导体器件，特别是多晶硅化物结构的制造结构中产生的副产物的方法。该方法包括以下步骤：顺序地形成多晶硅层和难熔金属硅化物层以覆盖半导体衬底上先前制造的结构，干蚀刻多晶硅层和难熔金属硅化物层以形成图案化的多晶硅层和图案化的难熔金属硅化物层，并对所得结构进行热处理，以在高于任何副产物的沸点的温度下除去在干蚀刻步骤中产生的至少一种副产物。

9. 发明授权

US06255697B1 Integrated circuit devices including distributed and isolated dummy conductive regions 有权
标题翻译：集成电路器件包括分布和隔离的虚拟导电区域
公开(公告)号：US06255697B1
公开(公告)日：2001-07-03
申请号：US09343997
申请日：1999-06-30
申请人： Kwang-dong Yoo , Young-wug Kim , Seok-kyun Jung
发明人： Kwang-dong Yoo , Young-wug Kim , Seok-kyun Jung
IPC分类号： H01L2976
CPC分类号： H01L27/1203 , H01L21/76264 , H01L21/76281 , H01L21/76283 , H01L21/76819 , H01L21/76885 , H01L23/528 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： An integrated circuit device is fabricated by forming at least one isolation region in an area of a semiconductor substrate, such as a monolithic semiconductor substrate or a silicon on insulator (SOI) substrate. The at least one isolation region defines at least one active region. A plurality of dummy conductive regions is distributed in the area of the semiconductor substrate, with the dummy conductive regions being constrained to overlie the at least one isolation region. The dummy conductive regions may be formed from a conductive layer that is also used to form, for example, a gate electrode, a capacitor electrode or a wiring pattern. The dummy conductive regions may be formed on an insulation layer, e.g., a gate insulation layer or an interlayer dielectric layer. Preferably, the dummy conductive regions are noncontiguous. In one embodiment, a lattice-shaped isolation region is formed including an array of node regions linked by interconnecting regions and defining an array of dummy active regions. The plurality of dummy conductive regions are formed on the node regions of the lattice-shaped isolation region. In another embodiment, an array of isolation regions is formed, defining a lattice-shaped dummy active region. An array of dummy conductive regions is formed on the array of isolation regions. Related integrated circuit devices are also described.
摘要翻译：通过在诸如单片半导体衬底或绝缘体上硅（SOI））衬底的半导体衬底的区域中形成至少一个隔离区域来制造集成电路器件。所述至少一个隔离区域限定至少一个活性区域。多个虚设导电区域分布在半导体衬底的区域中，其中虚拟导电区域被限制为覆盖至少一个隔离区域。虚拟导电区域可以由也用于形成例如栅电极，电容器电极或布线图案的导电层形成。虚拟导电区域可以形成在绝缘层上，例如栅极绝缘层或层间电介质层。优选地，虚拟导电区域是不连续的。在一个实施例中，形成格子状隔离区域，其包括通过互连区域链接并限定虚拟活动区域阵列的节点区域阵列。多个虚设导电区域形成在格子状隔离区域的节点区域上。在另一个实施例中，形成隔离区域阵列，限定了格状的虚拟有源区域。在隔离区域阵列上形成一个虚拟导电区域阵列。还描述了相关的集成电路器件。

10. 发明授权

US06806157B2 Metal oxide semiconductor field effect transistor for reducing resistance between source and drain and method for fabricating the same 有权
标题翻译：用于降低源极和漏极之间的电阻的金属氧化物半导体场效应晶体管及其制造方法
公开(公告)号：US06806157B2
公开(公告)日：2004-10-19
申请号：US10375437
申请日：2003-02-27
申请人： Jeong-hwan Yang , Young-wug Kim
发明人： Jeong-hwan Yang , Young-wug Kim
IPC分类号： H01L21336
CPC分类号： H01L29/66507 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833 , Y10S257/90
摘要： A MOS field effect transistor for reducing the resistance between a source and a drain includes a gate insulation layer and a gate electrode sequentially formed on a semiconductor substrate includes deep source/drain regions formed in upper portions of the semiconductor substrate at both sides of the gate electrode. Source/drain extension regions are formed in upper portions of the semiconductor substrate extending from the deep source/drain regions toward a channel region below the gate electrode to be thinner than the deep source/drain regions. A first silicide layer having a first thickness is formed on the surface of each of the deep source/drain regions. A second silicide layer having a second thickness thinner than the first thickness of the first silicide layer is formed to extend from the first silicide layer in a predetermined upper portion of each of the source/drain extension regions.
摘要翻译：用于降低源极和漏极之间的电阻的MOS场效应晶体管包括依次形成在半导体衬底上的栅绝缘层和栅电极，包括形成在栅极两侧的半导体衬底的上部的深源极/漏极区电极。源极/漏极延伸区域形成在半导体衬底的从深源极/漏极区域延伸到栅极电极下方的沟道区域的上部，以比深的源极/漏极区域更薄。在每个深源极/漏极区域的表面上形成具有第一厚度的第一硅化物层。形成具有比第一硅化物层的第一厚度薄的第二厚度的第二硅化物层，以在每个源极/漏极延伸区域的预定上部从第一硅化物层延伸。

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