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1. 发明授权

US07008835B2 Method of manufacturing a semiconductor device having a gate structure with low parasitic capacitance 失效
标题翻译：具有具有低寄生电容的栅极结构的半导体器件的制造方法
公开(公告)号：US07008835B2
公开(公告)日：2006-03-07
申请号：US10985246
申请日：2004-11-10
申请人： You-Seung Jin , Jong-Hyon Ahn , Hyuk-Ju Ryu
发明人： You-Seung Jin , Jong-Hyon Ahn , Hyuk-Ju Ryu
IPC分类号： H01L21/336
CPC分类号： H01L29/4925 , H01L21/28035 , H01L21/28044 , H01L21/28052 , H01L21/28114 , H01L21/823425 , H01L21/823437 , H01L21/823443 , H01L21/823468 , H01L29/42376 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/78 , H01L29/7833
摘要： In a method of manufacturing a semiconductor device, a gate insulation layer and a gate electrode are sequentially formed on a substrate on which an active region is defined. A planarized layer is formed on the substrate including the gate electrode. The planarized layer partially removed, and an upper portion of the gate electrode is exposed. A silicon epitaxial layer is selectively formed only on the exposed gate electrode, and the planarized layer is completely removed. A gate spacer is formed along side surfaces of the gate electrode and the silicon epitaxial layer. A source/drain region is formed on a surface portion of the active region corresponding to the gate electrode. Since the silicon epitaxial layer is formed only on the gate region except the source/drain region, the gate resistance is stabilized and the parasitic capacitance between the gate electrode and the source/drain region is reduce.
摘要翻译：在制造半导体器件的方法中，栅极绝缘层和栅电极依次形成在其上限定有源区的衬底上。在包括栅电极的基板上形成平坦化层。平坦化层被部分去除，并且栅电极的上部被暴露。硅外延层仅选择性地形成在暴露的栅电极上，并且平坦化层被完全去除。栅极间隔物沿着栅电极和硅外延层的侧表面形成。源极/漏极区域形成在与栅电极对应的有源区的表面部分上。由于仅在除源极/漏极区域之外的栅极区域上形成硅外延层，所以栅极电阻稳定，并且栅极电极和源极/漏极区域之间的寄生电容减小。

2. 发明申请

US20050112834A1 Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20050112834A1
公开(公告)日：2005-05-26
申请号：US10985246
申请日：2004-11-10
申请人： You-Seung Jin , Jong-Hyon Ahn , Hyuk-Ju Ryu
发明人： You-Seung Jin , Jong-Hyon Ahn , Hyuk-Ju Ryu
IPC分类号： H01L21/00 , H01L21/28 , H01L21/336 , H01L21/8234 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/4925 , H01L21/28035 , H01L21/28044 , H01L21/28052 , H01L21/28114 , H01L21/823425 , H01L21/823437 , H01L21/823443 , H01L21/823468 , H01L29/42376 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/78 , H01L29/7833
摘要： In a method of manufacturing a semiconductor device, a gate insulation layer and a gate electrode are sequentially formed on a substrate on which an active region is defined. A planarized layer is formed on the substrate including the gate electrode. The planarized layer partially removed, and an upper portion of the gate electrode is exposed. A silicon epitaxial layer is selectively formed only on the exposed gate electrode, and the planarized layer is completely removed. A gate spacer is formed along side surfaces of the gate electrode and the silicon epitaxial layer. A source/drain region is formed on a surface portion of the active region corresponding to the gate electrode. Since the silicon epitaxial layer is formed only on the gate region except the source/drain region, the gate resistance is stabilized and the parasitic capacitance between the gate electrode and the source/drain region is reduce.
摘要翻译：在制造半导体器件的方法中，栅极绝缘层和栅电极依次形成在其上限定有源区的衬底上。在包括栅电极的基板上形成平坦化层。平坦化层被部分去除，并且栅电极的上部被暴露。硅外延层仅选择性地形成在暴露的栅电极上，并且平坦化层被完全去除。栅极间隔物沿着栅电极和硅外延层的侧表面形成。源极/漏极区域形成在与栅电极对应的有源区的表面部分上。由于仅在除源极/漏极区域之外的栅极区域上形成硅外延层，所以栅极电阻稳定，并且栅极电极和源极/漏极区域之间的寄生电容减小。

3. 发明申请

US20060099766A1 Method of manufacturing a semiconductor device having a gate structure with low parasitic capacitance 失效
公开(公告)号：US20060099766A1
公开(公告)日：2006-05-11
申请号：US11313631
申请日：2005-12-21
申请人： You-Seung Jin , Jong-Hyon Ahn , Hyuk-Ju Ryu
发明人： You-Seung Jin , Jong-Hyon Ahn , Hyuk-Ju Ryu
IPC分类号： H01L21/336
CPC分类号： H01L29/4925 , H01L21/28035 , H01L21/28044 , H01L21/28052 , H01L21/28114 , H01L21/823425 , H01L21/823437 , H01L21/823443 , H01L21/823468 , H01L29/42376 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/78 , H01L29/7833
摘要： In a method of manufacturing a semiconductor device, a gate insulation layer and a gate electrode are sequentially formed on a substrate on which an active region is defined. A planarized layer is formed on the substrate including the gate electrode. The planarized layer partially removed, and an upper portion of the gate electrode is exposed. A silicon epitaxial layer is selectively formed only on the exposed gate electrode, and the planarized layer is completely removed. A gate spacer is formed along side surfaces of the gate electrode and the silicon epitaxial layer. A source/drain region is formed on a surface portion of the active region corresponding to the gate electrode. Since the silicon epitaxial layer is formed only on the gate region except the source/drain region, the gate resistance is stabilized and the parasitic capacitance between the gate electrode and the source/drain region is reduce.

4. 发明授权

US07332400B2 Method of manufacturing a semiconductor device having a gate structure with low parasitic capacitance 失效
标题翻译：具有具有低寄生电容的栅极结构的半导体器件的制造方法
公开(公告)号：US07332400B2
公开(公告)日：2008-02-19
申请号：US11313631
申请日：2005-12-21
申请人： You-Seung Jin , Jong-Hyon Ahn , Hyuk-Ju Ryu
发明人： You-Seung Jin , Jong-Hyon Ahn , Hyuk-Ju Ryu
IPC分类号： H01L21/336
CPC分类号： H01L29/4925 , H01L21/28035 , H01L21/28044 , H01L21/28052 , H01L21/28114 , H01L21/823425 , H01L21/823437 , H01L21/823443 , H01L21/823468 , H01L29/42376 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/78 , H01L29/7833
摘要： In a method of manufacturing a semiconductor device, a gate insulation layer and a gate electrode are sequentially formed on a substrate on which an active region is defined. A planarized layer is formed on the substrate including the gate electrode. The planarized layer partially removed, and an upper portion of the gate electrode is exposed. A silicon epitaxial layer is selectively formed only on the exposed gate electrode, and the planarized layer is completely removed. A gate spacer is formed along side surfaces of the gate electrode and the silicon epitaxial layer. A source/drain region is formed on a surface portion of the active region corresponding to the gate electrode. Since the silicon epitaxial layer is formed only on the gate region except the source/drain region, the gate resistance is stabilized and the parasitic capacitance between the gate electrode and the source/drain region is reduce.
摘要翻译：在制造半导体器件的方法中，栅极绝缘层和栅电极依次形成在其上限定有源区的衬底上。在包括栅电极的基板上形成平坦化层。平坦化层被部分去除，并且栅电极的上部被暴露。硅外延层仅选择性地形成在暴露的栅电极上，并且平坦化层被完全去除。栅极间隔物沿着栅电极和硅外延层的侧表面形成。源极/漏极区域形成在与栅电极对应的有源区的表面部分上。由于仅在除源极/漏极区域之外的栅极区域上形成硅外延层，所以栅极电阻稳定，并且栅极电极和源极/漏极区域之间的寄生电容减小。

5. 发明授权

US06764910B2 Structure of semiconductor device and method for manufacturing the same 有权
标题翻译：半导体器件的结构及其制造方法
公开(公告)号：US06764910B2
公开(公告)日：2004-07-20
申请号：US10371093
申请日：2003-02-21
申请人： Hyuk-Ju Ryu , Jong-hyon Ahn
发明人： Hyuk-Ju Ryu , Jong-hyon Ahn
IPC分类号： H01L2972
CPC分类号： H01L29/66492 , H01L21/26586 , H01L21/28035 , H01L21/28114 , H01L21/823412 , H01L21/823425 , H01L21/823468 , H01L29/6656
摘要： A semiconductor device and a method for manufacturing the same are provided. The structure of a semiconductor device includes gate electrodes having a T-shaped structure comprised of first and second gate electrodes having low gate resistance and low parasitic capacitance and a halo ion-implanted region in which a short channel effect can be effectively suppressed. The method for manufacturing the device is capable of performing high angle ion implantation without extending gate-to-gate space.
摘要翻译：提供半导体器件及其制造方法。半导体器件的结构包括具有由具有低栅极电阻和低寄生电容的第一和第二栅电极组成的T形结构的栅极电极和可有效抑制短沟道效应的晕圈离子注入区域。该器件的制造方法能够进行高角度离子注入而不延长栅极到栅极空间。

6. 发明授权

US07348636B2 CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof 有权
标题翻译： CMOS晶体管具有不同的PMOS和NMOS栅电极结构及其制造方法
公开(公告)号：US07348636B2
公开(公告)日：2008-03-25
申请号：US11030245
申请日：2005-01-06
申请人： Hyuk-Ju Ryu , Young-Wug Kim , Chang-Bong Oh , Hee-Sung Kang
发明人： Hyuk-Ju Ryu , Young-Wug Kim , Chang-Bong Oh , Hee-Sung Kang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L27/092 , H01L21/823842
摘要： In a CMOS semiconductor device using a silicon germanium gate and a method of fabricating the same, a gate insulating layer, a conductive electrode layer that is a seed layer, a silicon germanium electrode layer, and an amorphous conductive electrode layer are sequentially formed on a semiconductor substrate. A photolithographic process is then carried out to remove the silicon germanium electrode layer in the NMOS region, so that the silicon germanium layer is formed only in the PMOS region and is not formed in the NMOS region.
摘要翻译：在使用硅锗栅极的CMOS半导体器件及其制造方法中，栅极绝缘层，作为晶种层的导电电极层，硅锗电极层和非晶导电电极层依次形成在半导体衬底。然后进行光刻工艺以除去NMOS区域中的硅锗电极层，使得硅锗层仅形成在PMOS区域中，并且不形成在NMOS区域中。

7. 发明申请

US20050116297A1 CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof 有权
标题翻译： CMOS晶体管具有不同的PMOS和NMOS栅电极结构及其制造方法
公开(公告)号：US20050116297A1
公开(公告)日：2005-06-02
申请号：US11030245
申请日：2005-01-06
申请人： Hyuk-Ju Ryu , Young-Wug Kim , Chang-Bong Oh , Hee-Sung Kang
发明人： Hyuk-Ju Ryu , Young-Wug Kim , Chang-Bong Oh , Hee-Sung Kang
IPC分类号： H01L21/28 , H01L21/306 , H01L21/3065 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L21/336 , H01L29/76 , H01L31/062 , H01L31/119
CPC分类号： H01L27/092 , H01L21/823842
摘要： In a CMOS semiconductor device using a silicon germanium gate and a method of fabricating the same, a gate insulating layer, a conductive electrode layer that is a seed layer, a silicon germanium electrode layer, and an amorphous conductive electrode layer are sequentially formed on a semiconductor substrate. A photolithographic process is then carried out to remove the silicon germanium electrode layer in the NMOS region, so that the silicon germanium layer is formed only in the PMOS region and is not formed in the NMOS region.
摘要翻译：在使用硅锗栅极的CMOS半导体器件及其制造方法中，栅极绝缘层，作为晶种层的导电电极层，硅锗电极层和非晶导电电极层依次形成在半导体衬底。然后进行光刻工艺以除去NMOS区域中的硅锗电极层，使得硅锗层仅形成在PMOS区域中，并且不形成在NMOS区域中。

8. 发明申请

US20060240636A1 Trench isolation methods of semiconductor device 审中-公开
标题翻译：半导体器件的沟槽隔离方法
公开(公告)号：US20060240636A1
公开(公告)日：2006-10-26
申请号：US11358454
申请日：2006-02-21
申请人： Hyuk-Ju Ryu , Heon-Jong Shin , Hee-Sung Kang , Choong-Ryul Ryou , Mu-Kyeng Jung , Kyung-Soo Kim
发明人： Hyuk-Ju Ryu , Heon-Jong Shin , Hee-Sung Kang , Choong-Ryul Ryou , Mu-Kyeng Jung , Kyung-Soo Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/76237 , H01L21/76224 , H01L21/823878
摘要： In a trench isolation method, a semiconductor substrate having an N-MOS region and a P-MOS region is prepared. A first mask pattern exposing an N-MOS field region is formed on the N-MOS region, and a second mask pattern exposing a P-MOS field region is formed on the P-MOS region. A first photoresist pattern is formed to cover the P-MOS region and expose the N-MOS region. First impurity ions are implanted into the N-MOS region, using the first mask pattern and the first photoresist pattern as ion implantation masks, thereby forming a first impurity layer in the N-MOS field region. In this case, a portion of the first impurity layer is formed to extend below the first mask pattern. The first photoresist pattern is removed. The semiconductor substrate is etched using the first and second mask patterns as etch masks, thereby forming trenches in the N-MOS field region and the P-MOS field region and concurrently, forming a first impurity pattern of the first impurity layer remaining below the first mask pattern. A trench isolation layer filling the trenches is then formed.
摘要翻译：在沟槽隔离方法中，制备具有N-MOS区和P-MOS区的半导体衬底。在N-MOS区形成露出N-MOS场区的第一掩模图案，在P-MOS区形成露出P-MOS场区的第二掩模图案。形成第一光致抗蚀剂图案以覆盖P-MOS区域并暴露N-MOS区域。使用第一掩模图案和第一光致抗蚀剂图案作为离子注入掩模将第一杂质离子注入到N-MOS区域中，从而在N-MOS场区域中形成第一杂质层。在这种情况下，第一杂质层的一部分形成为延伸到第一掩模图案的下方。去除第一光致抗蚀剂图案。使用第一和第二掩模图案作为蚀刻掩模蚀刻半导体衬底，从而在N-MOS场区和P-MOS场区中形成沟槽，同时，形成第一杂质图案的第一杂质图案保留在第一掩模图案。然后形成填充沟槽的沟槽隔离层。

9. 发明授权

US06858907B2 Method of fabricating semiconductor device having notched gate 有权
标题翻译：制造具有开槽栅极的半导体器件的方法
公开(公告)号：US06858907B2
公开(公告)日：2005-02-22
申请号：US10114214
申请日：2002-04-02
申请人： Hyuk-Ju Ryu , Young-Gun Ko
发明人： Hyuk-Ju Ryu , Young-Gun Ko
IPC分类号： H01L21/338 , H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78 , H01L21/02
CPC分类号： H01L29/4983 , H01L21/28114 , H01L21/28123 , H01L29/6659 , H01L29/66598 , H01L29/7833
摘要： A semiconductor device includes: a silicon substrate; a source/drain region formed in the substrate including a lightly doped region and an adjacent heavily doped region, the depth of the heavily doped region being greater than the depth of the lightly doped region; a gate oxide layer on the silicon substrate; and a notched gate electrode on the substrate, the notched gate electrode including a notch along an outer side surface of a lower portion such that a top portion of the notched gate electrode is wider than the lower portion, the gate oxide layer extending between the interface of the notched gate electrode and the substrate, and a gate poly oxide layer provided along an outer side surface of the notched gate electrode and along an inner wall of the notch, a portion of the lightly doped region being under the notch.
摘要翻译：半导体器件包括：硅衬底; 形成在所述衬底中的源极/漏极区域，所述源极/漏极区域包括轻掺杂区域和相邻重掺杂区域，所述重掺杂区域的深度大于所述轻掺杂区域的深度; 硅衬底上的栅氧化层; 以及在基板上的缺口栅电极，所述带槽栅电极具有沿着下部的外侧面的切口，使得所述有槽栅电极的顶部比所述下部宽，所述栅极氧化物层在所述界面的栅极电极和衬底，以及沿着切口栅电极的外侧表面并沿着凹口的内壁设置的栅极多氧化物层，所述轻掺杂区域的一部分位于所述凹口下方。

10. 发明授权

US06855641B2 CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof 有权
公开(公告)号：US06855641B2
公开(公告)日：2005-02-15
申请号：US10421292
申请日：2003-04-23
申请人： Hyuk-Ju Ryu , Young-Wug Kim , Chang-Bong Oh , Hee-Sung Kang
发明人： Hyuk-Ju Ryu , Young-Wug Kim , Chang-Bong Oh , Hee-Sung Kang
IPC分类号： H01L21/28 , H01L21/306 , H01L21/3065 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L21/31
CPC分类号： H01L27/092 , H01L21/823842
摘要： In a CMOS semiconductor device using a silicon germanium gate and a method of fabricating the same, a gate insulating layer, a conductive electrode layer that is a seed layer, a silicon germanium electrode layer, and an amorphous conductive electrode layer are sequentially formed on a semiconductor substrate. A photolithographic process is then carried out to remove the silicon germanium electrode layer in the NMOS region, so that the silicon germanium layer is formed only in the PMOS region and is not formed in the NMOS region.

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