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1. 发明申请

US20060027876A1 CMOS device with improved performance and method of fabricating the same 失效
标题翻译：具有改进性能的CMOS器件及其制造方法
公开(公告)号：US20060027876A1
公开(公告)日：2006-02-09
申请号：US11179434
申请日：2005-07-12
申请人： Mu-kyeng Jung , Hee-sung Kang , Hyuk-ju Ryu , Woo-young Chung , Kyung-soo Kim
发明人： Mu-kyeng Jung , Hee-sung Kang , Hyuk-ju Ryu , Woo-young Chung , Kyung-soo Kim
IPC分类号： H01L29/76
CPC分类号： H01L29/7846 , H01L21/823814 , H01L21/82385 , H01L29/7833 , H01L29/7843
摘要： A complementary metal oxide semiconductor (CMOS) device having improved performance includes a first device active region including at least one pair of transistor active regions wherein one transistor active region has a first width and the other transistor active region for forming a contact has a second width, a first gate arranged on the first device active region, a MOS transistor of a first conductivity type including a source/drain region of the first conductivity type formed in the first device active region, a second device active region having a third width greater than the first width, a second gate arranged on the second device active region, and a MOS transistor of a second conductivity type including a source/drain region of the second conductivity type formed in the second device active region.
摘要翻译：具有改进性能的互补金属氧化物半导体（CMOS）器件包括包括至少一对晶体管有源区的第一器件有源区，其中一个晶体管有源区具有第一宽度，而用于形成接触的另一晶体管有源区具有第二宽度布置在第一器件有源区上的第一栅极，第一导电类型的MOS晶体管，包括形成在第一器件有源区中的第一导电类型的源极/漏极区域，第三器件有源区域的第三宽度大于所述第一宽度，布置在所述第二器件有源区上的第二栅极和包括形成在所述第二器件有源区中的所述第二导电类型的源极/漏极区的第二导电类型的MOS晶体管。

2. 发明授权

US07285831B2 CMOS device with improved performance and method of fabricating the same 失效
标题翻译：具有改进性能的CMOS器件及其制造方法
公开(公告)号：US07285831B2
公开(公告)日：2007-10-23
申请号：US11179434
申请日：2005-07-12
申请人： Mu-kyeng Jung , Hee-sung Kang , Hyuk-ju Ryu , Woo-young Chung , Kyung-soo Kim
发明人： Mu-kyeng Jung , Hee-sung Kang , Hyuk-ju Ryu , Woo-young Chung , Kyung-soo Kim
IPC分类号： H01L29/94
CPC分类号： H01L29/7846 , H01L21/823814 , H01L21/82385 , H01L29/7833 , H01L29/7843
摘要： A complementary metal oxide semiconductor (CMOS) device having improved performance includes a first device active region including at least one pair of transistor active regions wherein one transistor active region has a first width and the other transistor active region for forming a contact has a second width, a first gate arranged on the first device active region, a MOS transistor of a first conductivity type including a source/drain region of the first conductivity type formed in the first device active region, a second device active region having a third width greater than the first width, a second gate arranged on the second device active region, and a MOS transistor of a second conductivity type including a source/drain region of the second conductivity type formed in the second device active region.
摘要翻译：具有改进性能的互补金属氧化物半导体（CMOS）器件包括包括至少一对晶体管有源区的第一器件有源区，其中一个晶体管有源区具有第一宽度，而用于形成接触的另一晶体管有源区具有第二宽度布置在第一器件有源区上的第一栅极，第一导电类型的MOS晶体管，包括形成在第一器件有源区中的第一导电类型的源极/漏极区域，第三器件有源区域的第三宽度大于所述第一宽度，布置在所述第二器件有源区上的第二栅极和包括形成在所述第二器件有源区中的所述第二导电类型的源极/漏极区的第二导电类型的MOS晶体管。

3. 发明授权

US07179750B2 Method for manufacturing multi-thickness gate dielectric layer of semiconductor device 有权
公开(公告)号：US07179750B2
公开(公告)日：2007-02-20
申请号：US10685738
申请日：2003-10-15
申请人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
发明人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
IPC分类号： H01L21/302
CPC分类号： H01L29/42368 , H01L21/28194 , H01L21/28202 , H01L21/31116 , H01L21/31604 , H01L21/31616 , H01L21/3185 , H01L27/11 , H01L29/513 , H01L29/517 , H01L29/518
摘要： In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion of the second dielectric layer is selectively removed so as to selectively expose the first dielectric layer under the second dielectric layer. A portion of the exposed first dielectric layer is selectively removed so as to selectively expose the semiconductor substrate under the exposed first dielectric layer. Thereafter, a third dielectric layer having a thinner thickness than the first dielectric layer is formed on the exposed semiconductor substrate. As a result, a gate dielectric layer is formed to include a thick portion formed of the first dielectric layer and remaining second dielectric layer, a medium-thickness portion formed of the remaining first dielectric layer, and a thin portion formed of the third dielectric layer.

4. 发明授权

US07323420B2 Method for manufacturing multi-thickness gate dielectric layer of semiconductor device 有权
标题翻译：制造半导体器件多层栅极电介质层的方法
公开(公告)号：US07323420B2
公开(公告)日：2008-01-29
申请号：US11652186
申请日：2007-01-11
申请人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
发明人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
IPC分类号： H01L21/302
CPC分类号： H01L29/42368 , H01L21/28194 , H01L21/28202 , H01L21/31116 , H01L21/31604 , H01L21/31616 , H01L21/3185 , H01L27/11 , H01L29/513 , H01L29/517 , H01L29/518
摘要： In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion of the second dielectric layer is selectively removed so as to selectively expose the first dielectric layer under the second dielectric layer. A portion of the exposed first dielectric layer is selectively removed so as to selectively expose the semiconductor substrate under the exposed first dielectric layer. Thereafter, a third dielectric layer having a thinner thickness than the first dielectric layer is formed on the exposed semiconductor substrate. As a result, a gate dielectric layer is formed to include a thick portion formed of the first dielectric layer and remaining second dielectric layer, a medium-thickness portion formed of the remaining first dielectric layer, and a thin portion formed of the third dielectric layer.
摘要翻译：在制造半导体器件的多层栅极电介质层的方法中，在半导体衬底上形成第一介电层。使用与构成第一电介质层上的第一电介质层的材料不同的电介质材料形成第二电介质层。选择性地去除第二电介质层的一部分，以选择性地暴露第二介电层下的第一介电层。选择性地去除暴露的第一介电层的一部分，以便在暴露的第一介电层下选择性地暴露半导体衬底。此后，在暴露的半导体衬底上形成厚度比第一电介质层薄的第三电介质层。结果，形成栅极电介质层，包括由第一电介质层和剩余的第二电介质层形成的厚部，由剩余的第一电介质层形成的中等厚度部分和由第三电介质层形成的薄壁部分。

5. 发明申请

US20070117391A1 Method for manufacturing multi-thickness gate dielectric layer of semiconductor device 有权
标题翻译：制造半导体器件多层栅极电介质层的方法
公开(公告)号：US20070117391A1
公开(公告)日：2007-05-24
申请号：US11652186
申请日：2007-01-11
申请人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
发明人： Kyung-soo Kim , Young-wug Kim , Chang-bong Oh , Hee-sung Kang , Hyuk-ju Ryu
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L29/42368 , H01L21/28194 , H01L21/28202 , H01L21/31116 , H01L21/31604 , H01L21/31616 , H01L21/3185 , H01L27/11 , H01L29/513 , H01L29/517 , H01L29/518
摘要： In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion of the second dielectric layer is selectively removed so as to selectively expose the first dielectric layer under the second dielectric layer. A portion of the exposed first dielectric layer is selectively removed so as to selectively expose the semiconductor substrate under the exposed first dielectric layer. Thereafter, a third dielectric layer having a thinner thickness than the first dielectric layer is formed on the exposed semiconductor substrate. As a result, a gate dielectric layer is formed to include a thick portion formed of the first dielectric layer and remaining second dielectric layer, a medium-thickness portion formed of the remaining first dielectric layer, and a thin portion formed of the third dielectric layer.
摘要翻译：在制造半导体器件的多层栅极电介质层的方法中，在半导体衬底上形成第一介电层。使用与构成第一电介质层上的第一电介质层的材料不同的电介质材料形成第二电介质层。选择性地去除第二电介质层的一部分，以选择性地暴露第二介电层下的第一介电层。选择性地去除暴露的第一介电层的一部分，以便在暴露的第一介电层下选择性地暴露半导体衬底。此后，在暴露的半导体衬底上形成厚度比第一电介质层薄的第三电介质层。结果，形成栅极电介质层，包括由第一电介质层和剩余的第二电介质层形成的厚部，由剩余的第一电介质层形成的中等厚度部分和由第三电介质层形成的薄壁部分。

6. 发明授权

US06548862B2 Structure of semiconductor device and method for manufacturing the same 失效
公开(公告)号：US06548862B2
公开(公告)日：2003-04-15
申请号：US10144962
申请日：2002-05-14
申请人： Hyuk-ju Ryu , Jong-hyon Ahn
发明人： Hyuk-ju Ryu , Jong-hyon Ahn
IPC分类号： H01L31062
CPC分类号： H01L29/66492 , H01L21/26586 , H01L21/28035 , H01L21/28114 , H01L21/823412 , H01L21/823425 , H01L21/823468 , H01L29/6656
摘要： A semiconductor device and a method for manufacturing the same are provided. The structure of a semiconductor device includes gate electrodes having a T-shaped structure comprised of first and second gate electrodes having low gate resistance and low parasitic capacitance and a halo ion-implanted region in which a short channel effect can be effectively suppressed. The method for manufacturing the device is capable of performing high angle ion implantation without extending gate-to-gate space.

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