专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2014209715A1 FREQUENCY DIVIDER WITH DUTY CYCLE ADJUSTMENT WITHIN FEEDBACK LOOP 审中-公开
标题翻译：频率分频器在反馈环路中进行占空比调整
公开(公告)号：WO2014209715A1
公开(公告)日：2014-12-31
申请号：PCT/US2014/042920
申请日：2014-06-18
申请人： QUALCOMM INCORPORATED
发明人： CHEN, Wu-Hsin , SRIDHARA, Sriramgopal , LIU, Li
IPC分类号： H03K3/017 , H03K5/156 , H03K21/08
CPC分类号： H03L7/18 , H03K3/017 , H03K5/1565 , H03K21/08
摘要： A frequency divider (300) with duty cycle adjustment within a feedback loop is disclosed. In an exemplary design, an apparatus includes at least one divider circuit (310a, 310b) and at least one duty cycle adjustment circuit (320a, 320b) coupled in a feedback loop. The divider circuit(s) receive a clock signal (input Clock) at a first frequency and provide at least one divided signal (Idivp, Idivn) at a second frequency, which is a fraction of the first frequency. The duty cycle adjustment circuit(s) adjust the duty cycle of the at least one divided signal and provide at least one duty cycle adjusted signal (ladjp, ladjn) to the divider circuit(s). The divider circuit(s) may include first and second latches (310a, 310b), and the duty cycle adjustment circuit(s) may include first and second duty cycle adjustment circuits (320a, 320b). The first and second latches and the first and second duty cycle adjustment circuits may be coupled in a feedback loop and may perform divide-by-2.
摘要翻译：公开了一种在反馈环路内进行占空比调整的分频器（300）。在示例性设计中，装置包括耦合在反馈回路中的至少一个除法器电路（310a，310b）和至少一个占空比调整电路（320a，320b）。分频器电路以第一频率接收时钟信号（输入时钟），并以第二频率提供至少一个分频信号（Idivp，Idivn），其为第一频率的一部分。占空比调整电路调整至少一个分频信号的占空比，并向分频器电路提供至少一个占空比调整信号（ladjp，ladjn）。分频器电路可以包括第一和第二锁存器（310a，310b），并且占空比调整电路可以包括第一和第二占空比调整电路（320a，320b）。第一和第二锁存器以及第一和第二占空比调节电路可以耦合在反馈回路中并且可以执行除以2。

2. 发明申请

WO2013185960A3 DIGITALE ABTASTSCHALTUNG FÜR EIN MIT HILFE EINES PRIMÄR-TAKTSIGNALS AUF TAKTAUSFALL ZU ÜBERWACHENES SEKUNDÄR-TAKTSIGNAL 审中-公开
公开(公告)号：WO2013185960A3
公开(公告)日：2013-12-19
申请号：PCT/EP2013/058168
申请日：2013-04-19
申请人： AREVA GMBH
发明人： AUER, Günther , HEINEMANN, Bernd
IPC分类号： H03K21/08 , H03K21/40
摘要： Eine digitale Abtastschaltung (100) für ein mit Hilfe eines Primär-Taktsignals (202) auf Taktausfall zu überwachendes Sekundär-Taktsignal (204) mit einem Flipflop (102), welches - einen Clock-Eingang (108), - einen Data-Eingang (106), - einen Q-Ausgang (110) und - einen Reset-Eingang (112) aufweist, und mit einem n-Bit-Zähler (104), welcher - einen Takt-Eingang (114), - einen Reset-Eingang (128) und - einen Zählwert-Ausgang (116) aufweist, soll einerseits ein Erreichen von metastabilen Zuständen vermeiden und andererseits mehrfache Zustandswechsel des Sekundär-Taktsignals (204) innerhalb einer Zykluszeit erkennen und sich somit zum Betreiben von sicherheitsrelevanten Baugruppen, die auch in Kernkraftwerken eingesetzt werden können, eignen. Dazu sind das Flipflop (102) und der n-Bit-Zähler (104) elektrisch miteinander verschaltet, wobei n ≥ 2 ist, das Primär-Taktsignal (202) am Takt-Eingang (114) des n-Bit-Zählers (104) anliegt das Sekundär-Taktsignal (204) am Clock-Eingang (108) des Flipflops (102) anliegt, ein konstantes Signal am Data-Eingang (106) des Flipflops (102) anliegt, der Q-Ausgang (110) des Flipflops (102) mit dem Reset-Eingang (128) des n-Bit-Zählers (104) verbunden ist, und der Zählwert-Ausgang (116) des n-Bit-Zählers (104) über ein zwischengeschaltetes Logik-Gatter (122) mit dem Reset-Eingang (112) des Flipflops (102) verbunden ist.

3. 发明申请

WO2015112609A1 NON-VOLATILE COUNTER UTILIZING A FERROELECTRIC CAPACITOR 审中-公开
标题翻译：非挥发性计数器利用电磁电容器
公开(公告)号：WO2015112609A1
公开(公告)日：2015-07-30
申请号：PCT/US2015/012260
申请日：2015-01-21
申请人： RADIANT TECHNOLOGIES, INC. , EVANS, Joseph, T.
发明人： EVANS, Joseph, T.
IPC分类号： H03K21/08
CPC分类号： H03K21/08 , G11C11/221 , H03K23/766
摘要： A counter that can include a plurality of count stages is disclosed. Each count stage includes a ferroelectric capacitor characterized by first and second polarization states, a variable impedance element, reset and count ports and a detector. The variable impedance element has an impedance between first and second switch terminals that is determined by a signal on a control terminal, the ferroelectric capacitor being connected between the control terminal and the first switch terminal. A reset signal coupled to the control terminal causes the ferroelectric capacitor to be polarized in the first polarization state. The count port is configured to receive pulses to be counted, the count port being connected to the first switch terminal by a conductive load. The detector generates a count complete signal if a potential on the first terminal exceeds a threshold value while the count port is receiving one of the pulses.
摘要翻译：公开了可以包括多个计数级的计数器。每个计数级包括由第一和第二极化状态表征的铁电电容器，可变阻抗元件，复位和计数端口以及检测器。可变阻抗元件具有由控制端子上的信号确定的第一和第二开关端子之间的阻抗，铁电电容器连接在控制端子和第一开关端子之间。耦合到控制端子的复位信号使铁电电容器在第一偏振状态下被极化。计数端口被配置为接收待计数的脉冲，计数端口通过导电负载连接到第一开关端子。如果计数端口正在接收到其中一个脉冲，则第一端子上的电位超过阈值时，检测器产生计数完成信号。

4. 发明申请

WO2011103103A1 DIFFERENTIAL QUADRATURE DIVIDE-BY-THREE CIRCUIT WITH DUAL FEEDBACK PATH 审中-公开
标题翻译：具有双重反馈路径的差分三角三线电路
公开(公告)号：WO2011103103A1
公开(公告)日：2011-08-25
申请号：PCT/US2011/024942
申请日：2011-02-15
申请人： QUALCOMM Incorporated , TASIC, Aleksandar M. , DENG, Junxiong , QIAO, Dongjiang
发明人： TASIC, Aleksandar M. , DENG, Junxiong , QIAO, Dongjiang
IPC分类号： H03K21/08 , H03K23/66
CPC分类号： H03K21/08 , H03K23/66 , H03L7/1976
摘要： A divide-by-three circuit includes a chain of three dynamic flip-flops and a feedback circuit of combinatorial logic. The divide-by-three circuit receives a clock signal that synchronously clocks each dynamic flip-flop. The feedback circuit supplies a feedback signal onto the first dynamic-flop of the chain. In a first mode, a signal from a slave stage of the first flip-flop and a signal from a slave stage of the second flip-flop are used by the feedback circuit to generate the feedback signal. In a second mode, a signal from a master stage of the first flip-flop and a signal from a master stage of the second flip-flop are used by the feedback circuit to generate the feedback signal. By proper selection of the mode, the frequency range of the overall divider is extended. Combinatorial logic converts thirty-three percent duty cycle signals from the flip-flop chain into fifty percent duty cycle quadrature signals.
摘要翻译：三分之一电路包括三个动态触发器链和组合逻辑的反馈电路。分频电路接收时钟信号，同步地对每个动态触发器进行时钟。反馈电路将反馈信号提供给链的第一动态触发器。在第一模式中，来自第一触发器的从动级的信号和来自第二触发器的从动级的信号由反馈电路用于产生反馈信号。在第二模式中，来自第一触发器的主级的信号和来自第二触发器的主级的信号由反馈电路用于产生反馈信号。通过正确选择该模式，扩展整体分频器的频率范围。组合逻辑将三十三％的占空比信号从触发器链转换为五十％的占空比正交信号。

5. 发明申请

WO2023278083A2 RING OSCILLATOR BASED FREQUENCY DIVIDER 审中-公开
公开(公告)号：WO2023278083A2
公开(公告)日：2023-01-05
申请号：PCT/US2022/031632
申请日：2022-05-31
申请人： QUALCOMM INCORPORATED
发明人： LIM, Younghyun , TANG, Yiwu , PARK, Dongmin , ZHU, Yunliang , KESKIN, Mustafa , CHAO, Yue
IPC分类号： H03K21/08 , H03K23/66 , H03L7/24 , H03L7/193 , H03L7/183 , H03K23/667 , H03L7/0995 , H03L7/191
摘要： Aspects of the disclosure relate to a ring oscillator (RO) frequency divider configured to frequency divide an input clock by a programmable divider ratio to generate an output clock. In this regard, the RO frequency divider receives the input clock, enables each of a ring of N cascaded inverter stages substantially one at a time in response to the input clock; and outputs a second clock from an output of one of the ring of N cascaded inverter stages. In one aspect, each stage includes a p-channel metal oxide semiconductor field effect transistor (PMOS FET) coupled in series with an n-channel metal oxide semiconductor field effect transistor (NMOS FET). In another, each stage includes two PMOS FETs and an NMOS FET.

6. 发明申请

WO2012041917A2 RF DUTY-CYCLE CORRECTION CIRCUIT 审中-公开
标题翻译： RF占空比校正电路
公开(公告)号：WO2012041917A2
公开(公告)日：2012-04-05
申请号：PCT/EP2011/066892
申请日：2011-09-28
申请人： ST-ERICSSON SA , HESEN, Leonardus , FRAMBACH, Johannes , MATEMAN, Paul
发明人： HESEN, Leonardus , FRAMBACH, Johannes , MATEMAN, Paul
IPC分类号： H03K21/08
CPC分类号： H03K21/08 , H03K5/1565
摘要： A duty-cycle correction circuit comprises a plurality of AC-coupled, independently-biased inverter stages connected in series. A periodic signal is applied to an input of the plurality of inverter stages. Each inverter stage comprises an inverter with a resistive element connected in feedback between its output and input nodes. Each inverter stage is AC-coupled to a prior stage via a capacitor. The AC-coupling allows the signal to pass between inverter stages, but DC-isolates each inverter stage from adjacent stages, allowing each stage to maintain an independent DC bias of the signal at that stage. By virtue of the feedback resistive element, each stage defines a transition point between high and low signal states. Due to non-zero rise and fall times of the periodic signal, the independent DC bias of each stage is operative to incrementally shift the transition point of the periodic signal at each stage towards a desired duty-cycle.
摘要翻译：占空比校正电路包括串联连接的多个交流耦合，独立偏置的逆变器级。周期性信号被施加到多个逆变器级的输入。每个逆变器级包括一个逆变器，其输入和输入节点之间的反馈电阻元件连接在一起。每个逆变器级通过电容器交流耦合到前一级。交流耦合允许信号在逆变器级之间通过，但是直流隔离每个逆变器级与相邻级，使得每级在该级保持独立的信号直流偏置。借助于反馈电阻元件，每个级定义高信号状态和低信号状态之间的转换点。由于周期信号的非零上升和下降时间，每一级的独立直流偏置可操作以递增地将每级的周期性信号的转变点移向期望的占空比。

7. 发明申请

WO2012041917A3 RF DUTY-CYCLE CORRECTION CIRCUIT 审中-公开
标题翻译： RF DUTY-CYCLE校正电路
公开(公告)号：WO2012041917A3
公开(公告)日：2012-08-23
申请号：PCT/EP2011066892
申请日：2011-09-28
申请人： ST ERICSSON SA , HESEN LEONARDUS , FRAMBACH JOHANNES , MATEMAN PAUL
发明人： HESEN LEONARDUS , FRAMBACH JOHANNES , MATEMAN PAUL
IPC分类号： H03K21/08 , H03K5/156
CPC分类号： H03K21/08 , H03K5/1565
摘要： A duty-cycle correction circuit comprises a plurality of AC-coupled, independently-biased inverter stages connected in series. A periodic signal is applied to an input of the plurality of inverter stages. Each inverter stage comprises an inverter with a resistive element connected in feedback between its output and input nodes. Each inverter stage is AC-coupled to a prior stage via a capacitor. The AC-coupling allows the signal to pass between inverter stages, but DC-isolates each inverter stage from adjacent stages, allowing each stage to maintain an independent DC bias of the signal at that stage. By virtue of the feedback resistive element, each stage defines a transition point between high and low signal states. Due to non-zero rise and fall times of the periodic signal, the independent DC bias of each stage is operative to incrementally shift the transition point of the periodic signal at each stage towards a desired duty-cycle.
摘要翻译：占空比校正电路包括串联连接的多个AC耦合的独立偏置的反相器级。周期性信号被施加到多个逆变器级的输入端。每个逆变器级包括具有在其输出和输入节点之间反馈的电阻元件的反相器。每个逆变器级通过电容器交流耦合到前一级。 AC耦合允许信号在反相器级之间通过，但是将每个反相器级直接隔离到相邻级，从而允许每级在该级保持信号的独立DC偏置。由于反馈电阻元件，每个级限定了高和低信号状态之间的转变点。由于周期信号的非零上升和下降时间，每个级的独立DC偏置可用于将每个级周期性信号的转变点逐渐移向期望的占空比。

8. 发明申请

WO2008095974A3 A CLOCK CIRCUIT 审中-公开
公开(公告)号：WO2008095974A3
公开(公告)日：2008-08-14
申请号：PCT/EP2008/051492
申请日：2008-02-07
申请人： TEXAS INSTRUMENTS LIMITED , LYTOLLIS, Shaun
发明人： LYTOLLIS, Shaun
IPC分类号： H03K21/08 , H03L7/18
摘要： A clock circuit with a plurality of inputs for a plurality of respective clock signals, the clock signals alternating between a first and a second state. At least one divider circuit is arranged to take an input clock signal and provide an output that is in the first state for a first fixed multiple of the duration the clock signal is in the first state, and in the second state for a second fixed multiple of the duration the clock signal is in the second state. A plurality of delay circuits are arranged to take the output of the divider circuit or circuits and provide a set of outputs each delayed by a fixed duration. A selection circuit is arranged to select the outputs of the delay circuits in sequence. The selection circuit is arranged to select the next output in the sequence at or after the time when the selected output changes from the first state to the second state.

9. 发明申请

WO2003021785A3 PROGRAMMABLE EVEN-NUMBER CLOCK DIVIDER CIRCUIT WITH DUTY CYCLE CORRECTION AND OPTIONAL PHASE SHIFT 审中-公开
公开(公告)号：WO2003021785A3
公开(公告)日：2003-03-13
申请号：PCT/US2002/026279
申请日：2002-08-16
申请人： XILINX, INC.
发明人： NGUYEN, Andy, T.
IPC分类号： H03K21/08
摘要： A clock divider circuit includes a state machine that receives an input clock signal and generates mutually exclusive set and reset control signals. The set and reset control signals are used to control set and reset passgates, respectively, selectively providing the input clock signal to the gate terminals of a pullup and a pulldown on the output node. The set and reset control signals are also provided to a keeper circuit that maintains a value placed on the output node.

10. 发明申请

WO2021150295A1 ANALOG COUNTER WITH PULSED CURRENT SOURCE FOR A DIGITAL PIXEL 审中-公开
公开(公告)号：WO2021150295A1
公开(公告)日：2021-07-29
申请号：PCT/US2020/060827
申请日：2020-11-17
申请人： RAYTHEON COMPANY
发明人： WAHL, Richard E.
IPC分类号： H03M1/34 , H03M1/50 , H03M1/52 , H03M1/60 , H04N5/378 , G01J1/46 , H03K21/02 , H03K21/08 , H03K21/38 , H04N5/37455
摘要： An analog counter circuit for use with a digital pixel includes an input; an output; a first inverter connected to the input that produces on a first inverter output a time delayed inverted signal (RP*) from an input signal received at the input; a second inverter connected to the first inverter output that produces a time delayed signal (RP) at a second inverter output from the input signal and that is delayed relative to RP* and a control switch connected between a source voltage and a floating node. The control switch is controlled by the signal RP* on the first inverter output. The analog counter also includes a feedback capacitor connected between the second inverter output and the floating node; an accumulating capacitor that accumulates at least some of a charge that passes through the control switch; and an injection switch connected between the control switch and the accumulating capacitor.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式