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1. 发明申请

WO2022043033A1 ELECTRONIC DEVICE, PACKAGE AND SEMICONDUCTOR CHIP THEREFORE 审中-公开
公开(公告)号：WO2022043033A1
公开(公告)日：2022-03-03
申请号：PCT/EP2021/072081
申请日：2021-08-06
申请人： HITACHI ENERGY SWITZERLAND AG [CH]/[CH]
发明人： STIASNY, Thomas , WIKSTROEM, Tobias
IPC分类号： H01L21/603 , H01L23/051 , H01L25/10 , H01L2224/03602 , H01L2224/0361 , H01L2224/04 , H01L2224/04042 , H01L2224/05011 , H01L2224/05012 , H01L2224/05551 , H01L2224/05552 , H01L2224/05558 , H01L2224/05624 , H01L2224/0603 , H01L2224/06051 , H01L2224/06181 , H01L2224/48091 , H01L2224/73201 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/72 , H01L24/73 , H01L25/117
摘要： An electronic device (1) comprises a semiconductor chip (2) having an electrical contact metallization (3), and a package (4) having an electrical contact disc (5). The electrical contact metallization (3) and the electrical contact disc (5) are in direct contact on a contact face (45) so that the semiconductor chip (2) is electrically connected with the package (4). At the contact face (45), at least one of the electrical contact metallization (3) and the electrical contact disc (5) comprises a geometric structuring (6) (a surface pattern) fashioned as at least one recessed area. A mean roughness of a top face (50) of the electrical contact disc (5) facing the electrical contact metallization (3) may be between 0.2 pm and 1 pm, wherein, because of the mean roughness, the top face (50) is configured to penetrate an oxide layer (31) of the electrical contact metallization (3) at the contact face (45) (e.g., native oxide on an aluminum metallization (3) ). The electrical contact metallization (3) may be of multilayer fashion and comprise at least one interrupted sub-layer (33) and at least one continuous sub-layer (34), the continuous sub-layer (34) being located at the contact face (45), wherein the at least one interrupted sub-layer (33) and the at least one continuous sub-layer (34) may be of the same material or of different materials, but have different thicknesses. All of the electrical contact metallization (3) and/or of the electrical contact disc (5) may be configured to be on the same electric potential. The geometric structuring (6) may consist of or comprise at least one of the following shapes: circle, spiral, rectangle, triangle, hexagon, honeycomb and may comprise interruptions. The semiconductor chip (2) may comprise a further electrical contact metallization (7) having an even and smooth further contact face (70), wherein, seen in top view, an overall size of the further contact face (70) is smaller than that of the electrical contact metallization (3) by at least a factor of 1.5 and by at most a factor of 5, and wherein, because of the geometric structuring (6), at the contact face (45) an effective size of the electrical contact metallization (3) is the same as the overall size of the further contact face (70), with a tolerance of at most a factor of 1.2, wherein the electrical contact metallization (3) and the further electrical contact metallization (7) may be located at opposite main sides of the semiconductor chip (2) and the semiconductor chip (2) is configured to be electrically contacted with a contact force of at least 0.3 kN/cm and of at most 2 kN/cm. The package (4) may comprise an electrically insulating jacket (41) and an electrical metal contact plate (42), wherein the semiconductor chip (2) and the electrical contact disc (5) as well as the metal plate (42) are arranged in the jacket (41) and are aligned in parallel with each other, wherein, seen in top view onto the contact face (45), sizes of the semiconductor chip (2) and the electrical contact disc (5) differ from each other by at most a factor of 1.3, and wherein the electrical contact disc (5) is located between the semiconductor chip (2) and the contact plate (42). The semiconductor chip (2), the electrical contact disc (5) and the optional contact plate (42) can be of circular shape seen in top view. The electronic device (1) may be a press pack power semiconductor device. The pressure at a given contact force is increased in the electronic device (1) by reducing the overall contact area, that is, a contact face (45) between the electrical contact metallization (3) of the semiconductor chip (2) and the electrical contact disc (5) of the package (4), to form a reliable and stable dry interface electric contact and avoid 'too low pressure1 effects, for example: for an anode side metallization of an IGCT or of an GTO, as the clamping force is typically limited for by the mechanical stability of the cathode side metallization which is in total significantly lower in contact area and more fragile due to the segmentation of a high metal stack; for a metallization of a free-floating side of a bonded diode used at low clamping forces, for example, when clamped with an IGCT - for a free-floating anode side, the probability of electromigration may be higher; or for an anode and cathode side metallization of a free-floating diode or of a free-floating plus diode clamped at relatively low pressures.

2. 发明申请

WO2021150346A1 METHODS FOR MAKING DOUBLE-SIDED SEMICONDUCTOR DEVICES AND RELATED DEVICES, ASSEMBLIES, PACKAGES AND SYSTEMS 审中-公开
公开(公告)号：WO2021150346A1
公开(公告)日：2021-07-29
申请号：PCT/US2020/066913
申请日：2020-12-23
申请人： MICRON TECHNOLOGY, INC.
发明人： CHUN, Hyunsuk
IPC分类号： H01L21/822 , H01L25/065 , H01L27/06 , H01L23/48 , H01L21/76831 , H01L21/8221 , H01L2224/03002 , H01L2224/0346 , H01L2224/03849 , H01L2224/0401 , H01L2224/05567 , H01L2224/0557 , H01L2224/06181 , H01L2224/08145 , H01L2224/11002 , H01L2224/1146 , H01L2224/11849 , H01L2224/131 , H01L2224/16145 , H01L2224/17181 , H01L2224/32145 , H01L2224/73204 , H01L2224/80013 , H01L2224/80895 , H01L2224/80896 , H01L2224/92125 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L23/481 , H01L23/5384 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/80 , H01L25/0657 , H01L25/50 , H01L27/0694
摘要： Semiconductor devices may include a die (102) including a semiconductor material. The die may include a first active surface (108) including first integrated circuitry (114) on a first side of the die and a second active surface (110) including second integrated circuitry (122) on a second, opposite side of the die. In some embodiments, the die may include two die portions: a first die portion including the first active surface and a second die portion including the second active surface. The first die portion and the second die portion may be joined together with the first active surface facing away from the second active surface.

3. 发明申请

WO2022124895A2 INTEGRATED CIRCUIT COMPRISING A SUBSTRATE, A DIE AND AN IMPROVED DIE ATTACHMENT LAYER, AS WELL AS CORRESPONDING METHOD OF DIE BONDING 审中-公开
公开(公告)号：WO2022124895A2
公开(公告)日：2022-06-16
申请号：PCT/NL2021/050747
申请日：2021-12-08
申请人： STICHTING CHIP INTEGRATION TECHNOLOGY CENTRE
发明人： NAKKA, John Suman
IPC分类号： H01L21/603 , H01L21/60 , H01L23/488 , H01L2224/11312 , H01L2224/13012 , H01L2224/13013 , H01L2224/13017 , H01L2224/1319 , H01L2224/1329 , H01L2224/13339 , H01L2224/13344 , H01L2224/14131 , H01L2224/14132 , H01L2224/14135 , H01L2224/16052 , H01L2224/16058 , H01L2224/27312 , H01L2224/2732 , H01L2224/27334 , H01L2224/279 , H01L2224/29012 , H01L2224/29013 , H01L2224/29015 , H01L2224/29017 , H01L2224/29018 , H01L2224/29078 , H01L2224/2919 , H01L2224/2929 , H01L2224/29294 , H01L2224/29339 , H01L2224/29344 , H01L2224/30131 , H01L2224/30132 , H01L2224/30135 , H01L2224/30136 , H01L2224/30177 , H01L2224/30505 , H01L2224/3201 , H01L2224/32013 , H01L2224/32014 , H01L2224/32052 , H01L2224/32056 , H01L2224/32058 , H01L2224/32227 , H01L2224/32245 , H01L2224/3301 , H01L2224/3312 , H01L2224/73103 , H01L2224/73204 , H01L2224/81192 , H01L2224/81862 , H01L2224/8314 , H01L2224/83192 , H01L2224/83204 , H01L2224/8384 , H01L2224/83862 , H01L2224/9212 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/33 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2924/10253 , H01L2924/10272 , H01L2924/3025 , H01L2924/351 , H01L2924/3512
摘要： An integrated circuit (IC) (30) is attached to a substrate (10) through an improved die attachment layer (20), whereby an IC-package is formed. The die attachment layer (20) comprises at least one first region (21) comprising a first attachment material and at least one second region (22) comprising a second attachment material different from the first attachment material, wherein the at least one first region (21) is located centrally on the substrate (10), wherein the at least one second region (22) is located eccentrically, such as at a side, at a part of a side, or at a corner, wherein the at least one first region (21) comprises at least one metal (e.g., sintered silver) and the at least one second region (22) comprises a die-attach material selected from heat assisted attach materials, pressure-based attach materials, pressure-less attach materials, thermohardening attach materials, such as epoxy resins, curing attach materials, polymer based attach materials, resin based attach materials, fibres, nanoparticles, and combinations thereof, in particular, wherein the at least one second region (22) comprises particles of dielectric material embedded in a matrix of polymeric material. A thermal expansion coefficient (TCE3) of the at least one first region (21) and a thermal expansion coefficient (TCE4) of the at least one second region (22) may be between a thermal expansion coefficient (TCE1) of the substrate (10) and a thermal expansion coefficient (TCE2) of the die (30). The thermal expansion coefficient (TCE4) of the at least one second region (22) may be between the thermal expansion coefficient (TCE3) of the at least one first region (21) and the thermal expansion coefficient (TCE1) of the substrate (10) or between the thermal expansion coefficient (TCE3) of the at least one first region (21) and the thermal expansion coefficient (TCE2) of the die (30). The elastic modulus (EM1) of the at least one first region (21) may be higher than the elastic modulus (EM2) of the at least one second region (22), wherein, preferably, the elastic modulus (EM1) of the at least one first region (21) is lower than an elastic modulus of the die (30) and wherein, preferably, the elastic modulus (EM2) of the at least one second region (22) is higher than an elastic modulus of the substrate (10), wherein the elastic moduli are each a Young's modulus, a bulk modulus, viscoelastic modulus, and/or a volumetric modulus. The attachment layer (20) may extend up to a side of the die (30), preferably forming a fillet (27). The attachment layer may comprise a cavity (28) for receiving the die (30), preferably a cavity (28) adapted to outer dimensions of the die (30). The die (30) may be a power IC or, alternatively, the integrated circuit may relate to a photonics application, with an improved heat flow from die (30) to the substrate (10), or may relate to an IC requiring precise temperature control thereof, such as a VCSEL circuit. In the manufacturing method, i.e., method of die bonding, the at least one first region (21) may be provided in the form of at least one central bar-shaped volume, optionally with one or more side branches, preferably towards every substrate corner and optionally at each longitudinal side of the substrate (10). The die (30) may be attached to the substrate (10) by applying pressure, by applying heat, by applying curing, by sintering, by diffusion, or by a combination thereof. After attaching the die (30), the first region (21) is spread out over the central region of the substrate (10), whereas the second regions (22) are slightly increased in surface are size and are positioned at the sides and corners.

4. 发明申请

WO2021201990A1 MULTIPLE CHIP MODULE WITH LID AND STIFFENER RING 审中-公开
公开(公告)号：WO2021201990A1
公开(公告)日：2021-10-07
申请号：PCT/US2021/017445
申请日：2021-02-10
申请人： APPLE INC.
发明人： CHEN, Wei , ZHAO, Jie-Hua , ZHAI, Jun , CHANG, Po-Hao , LIN, Hsien-Che , KE, Ying-Chieh , HU, Kunzhong
IPC分类号： H01L23/04 , H01L23/16 , H01L23/367 , H01L25/065 , H01L2224/131 , H01L2224/16227 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2224/83385 , H01L2224/92125 , H01L23/24 , H01L23/3675 , H01L23/42 , H01L23/562 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/83 , H01L24/92 , H01L25/0655 , H01L25/18 , H01L2924/15311 , H01L2924/1615 , H01L2924/16151 , H01L2924/16153 , H01L2924/16251 , H01L2924/164 , H01L2924/19105 , H01L2924/3511
摘要： Multiple chip module (MCM) structures are described. In an embodiment, a module includes a first and second components on the top side of a module substrate, a stiffener structure mounted on the top side of the module substrate, and a lid mounted on the stiffener structure and covering the first component and the second component. The stiffener is joined to the lid within a trench formed in a roof of the lid.

5. 发明申请

WO2021201969A1 PROCESS FOR REMOVING BOND FILM FROM CAVITIES IN PRINTED CIRCUIT BOARDS 审中-公开
公开(公告)号：WO2021201969A1
公开(公告)日：2021-10-07
申请号：PCT/US2021/016294
申请日：2021-02-03
申请人： RAYTHEON COMPANY
发明人： BENEDICT, James E. , DANELLO, Paul A. , PEVZNER, Mikhail , SIKINA, Thomas V. , SOUTHWORTH, Andrew R.
IPC分类号： H05K3/40 , H01L2224/11602 , H01L2224/45147 , H01L2224/73207 , H01L24/11 , H01L24/45 , H01L24/73 , H05K2201/10287 , H05K2203/0257 , H05K2203/166 , H05K3/26 , H05K3/4007 , H05K3/4046 , H05K3/465 , H05K3/4679
摘要： A process of fabricating an electromagnetic circuit includes providing a first sheet of dielectric material including a top surface having at least one conductive trace and depositing a solder bump on the at least one conductive trace. The process further includes applying a second sheet of dielectric material to the first sheet of dielectric material with bond film sandwiched in between, the second sheet of dielectric material having a through-hole providing access to the solder bump. The process further includes bonding the first and second dielectric materials to one another and removing bond film resin from the solder bump. The process further includes machining the solder bump by the drilling or milling process to achieve a desired amount of solder in the solder bump.

6. 发明申请

WO2021122987A1 INTEGRATED CIRCUIT PACKAGES TO MINIMIZE STRESS ON A SEMICONDUCTOR DIE 审中-公开
公开(公告)号：WO2021122987A1
公开(公告)日：2021-06-24
申请号：PCT/EP2020/086760
申请日：2020-12-17
申请人： ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
发明人： LAKSHMANAN, Ramji Sitaraman , STENSON, Bernard , FITZGERALD, Padraig Liam , KIERSE, Oliver , TWOHIG, Michael James , FLYNN, Michael John , O'SULLIVAN, Laurence Brendan
IPC分类号： H01L21/52 , H01L23/04 , H01L2224/04 , H01L2224/0401 , H01L2224/04042 , H01L2224/056 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/2405 , H01L2224/24227 , H01L2224/245 , H01L2224/2919 , H01L2224/29294 , H01L2224/32013 , H01L2224/32014 , H01L2224/32225 , H01L2224/32237 , H01L2224/33183 , H01L2224/40225 , H01L2224/48225 , H01L2224/48227 , H01L2224/48463 , H01L2224/73253 , H01L2224/73265 , H01L2224/81207 , H01L2224/82002 , H01L2224/82106 , H01L2224/83192 , H01L2224/83862 , H01L2224/83868 , H01L2224/83871 , H01L2224/83874 , H01L2224/85002 , H01L2224/85005 , H01L2224/85801 , H01L2224/9205 , H01L23/041 , H01L23/06 , H01L23/13 , H01L23/20 , H01L23/49811 , H01L23/49833 , H01L23/49838 , H01L23/562 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/85 , H01L24/92 , H01L2924/15153 , H01L2924/15311 , H01L2924/16152 , H01L2924/16196 , H01L2924/163
摘要： An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.

7. 发明申请

WO2022271237A1 QUASI-MONOLITHIC HIERARCHICAL INTEGRATION ARCHITECTURE 审中-公开
公开(公告)号：WO2022271237A1
公开(公告)日：2022-12-29
申请号：PCT/US2022/021671
申请日：2022-03-24
申请人： INTEL CORPORATION
发明人： ELSHERBINI, Adel A. , LIFF, Shawna , SWAN, Johanna M. , SEBOT, Julien
IPC分类号： H01L25/065 , H01L25/18 , H01L23/00 , H01L23/538 , H01L23/48 , H01L21/568 , H01L21/6835 , H01L2221/68345 , H01L2221/68354 , H01L2221/68359 , H01L2224/16225 , H01L2224/24147 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/73209 , H01L2224/73217 , H01L2224/73253 , H01L2224/82005 , H01L23/16 , H01L23/3128 , H01L23/562 , H01L24/16 , H01L24/19 , H01L24/24 , H01L24/27 , H01L24/32 , H01L24/73 , H01L24/83 , H01L25/0652 , H01L2924/37001
摘要： A microelectronic assembly is provided, comprising: a first integrated circuit (IC) die at a first level, a second IC die at a second level, and a third IC die at a third level, the second level being in between the first level and the third level. A first interface between the first level and the second level is electrically coupled with high-density interconnects of a first pitch and a second interface between the second level and the third level is electrically coupled with interconnects of a second pitch. In some embodiments, at least one of the first IC die, second IC die, and third IC die comprises another microelectronic assembly. In other embodiments, at least one of the first IC die, second IC die, and third IC die comprises a semiconductor die.

8. 发明申请

WO2022182938A2 INTEGRATED CIRCUIT PACKAGE COMPRISING A SUBSTRATE STACK AND METHOD OF ASSEMBLY USING A TEMPORARY RIGID CARRIER 审中-公开
公开(公告)号：WO2022182938A2
公开(公告)日：2022-09-01
申请号：PCT/US2022/017817
申请日：2022-02-25
申请人： MARVELL ASIA PTE LTD , GRAF, Richard , ENGLAND, Luke , NAYINI, Manish , PATEL, Janak G.
发明人： GRAF, Richard , ENGLAND, Luke , NAYINI, Manish , PATEL, Janak G.
IPC分类号： H01L21/683 , H01L23/36 , H01L23/538 , H01L21/67 , H01L21/6835 , H01L2221/68381 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81005 , H01L2224/81191 , H01L2224/92225 , H01L23/3675 , H01L23/49816 , H01L23/49822 , H01L23/49833 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/3511
摘要： A method for assembling at least one stacked substrate package, each stacked substrate package includes binding a laminated base substrate (104), configured to route interconnections between circuitry on a first surface of the laminated base substrate and circuitry on a second surface of the laminated base substrate, to a surface of a rigid carrier (102) to prevent warping of the laminated base substrate (104). Each base substrate is coupled to at least one dielectric build-up substrate (106), which is configured to route integrated interconnections between a top surface and a bottom surface of the dielectric build-up substrate, to the laminated base substrate (104). At least one integrated circuit die (108) is coupled to the at least one dielectric build-up substrate (106), and then the carrier (102) is released from the laminated base substrate (104) to form an assembled stacked substrate package. Also, multiple stacked substrate packages may be assembled in parallel on one carrier.

9. 发明申请

WO2022015637A1 NEGATIVE FILLET FOR MOUNTING AN INTEGRATED DEVICE DIE TO A CARRIER 审中-公开
公开(公告)号：WO2022015637A1
公开(公告)日：2022-01-20
申请号：PCT/US2021/041251
申请日：2021-07-12
申请人： ANALOG DEVICES, INC.
发明人： VENKATADRI, Vikram , BOLOGNIA, David Frank
IPC分类号： H01L25/16 , H01L23/31 , H01L23/12 , H01L23/16 , H01L23/495 , H01L2224/26175 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L23/3157 , H01L24/32 , H01L24/73 , H01L24/92
摘要： An electronic module includes a package substrate, an integrated device die, a dam structure, and a mounting compound. The integrated device die can have an upper side, a lower side, and an outer side edge. The dam structure can have first and second sidewalls opposing each other. The second sidewall can be nearer to the outer side edge than the first sidewall. The first sidewall can be laterally positioned between a center of the lower side of the integrated device die and the outer side edge. The dam structure can be disposed between a portion of the package substrate and a portion of the lower side of the integrated device die. The mounting compound can be disposed between the lower side of the integrated device die and the package substrate. The dam structure can be positioned between the mounting compound and the outer side edge of the integrated device die.

10. 发明申请

WO2021262368A1 INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING SPLIT, DOUBLE-SIDED METALLIZATION STRUCTURES TO FACILITATE A SEMICONDUCTOR DIE ("DIE") MODULE EMPLOYING STACKED DICE, AND RELATED FABRICATION METHODS 审中-公开
公开(公告)号：WO2021262368A1
公开(公告)日：2021-12-30
申请号：PCT/US2021/033915
申请日：2021-05-24
申请人： QUALCOMM INCORPORATED
发明人： WE, Hong Bok , HSU, Marcus , PATIL, Aniket
IPC分类号： H01L25/065 , H01L25/16 , H01L25/00 , H01L23/498 , H01L23/538 , H01L23/00 , H01L2224/08145 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73251 , H01L2224/80006 , H01L2224/80013 , H01L2224/80203 , H01L2224/80896 , H01L2224/81193 , H01L2224/81203 , H01L2224/83192 , H01L2224/9222 , H01L2225/06517 , H01L2225/06558 , H01L2225/06572 , H01L23/49816 , H01L23/5385 , H01L23/562 , H01L24/73 , H01L24/80 , H01L24/81 , H01L24/92 , H01L25/0652 , H01L25/50 , H01L2924/15331 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H01L2924/3511
摘要： Integrated circuit (IC) packages employing split, double-sided IC metallization structures to facilitate a semiconductor die module employing stacked dice, and related fabrication methods are disclosed. Multiple IC dice in the IC package are stacked and bonded together in a back-to-back, top and bottom IC die configuration in an IC die module, which can minimize the height of the IC package. The metallization structure is split between separate top and bottom metallization structures adjacent to respective top and bottom surfaces of the IC die module to facilitate die-to-die and external electrical connections to the dice. The top and bottom metallization structures can be double-sided by exposing substrate interconnects on respective inner and outer surfaces for respective die and external electrical interconnections. In other aspects, a compression bond is included between the IC dice mounted together in a back-to-back configuration to further minimize the overall height of the IC package.

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