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1. 发明申请

WO2015069184A1 A GUARD STRUCTURE FOR SIGNAL ISOLATION 审中-公开
公开(公告)号：WO2015069184A1
公开(公告)日：2015-05-14
申请号：PCT/SG2014/000470
申请日：2014-10-07
申请人： THALES SOLUTIONS ASIA PTE LTD. , CNRS - CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (EPST) , NANYANG TECHNOLOGICAL UNIVERSITY
发明人： TAN, Dunlin , YU, Jong Jen , HEE, David , TAY, Beng Kang , BAILLARGEAT, Dominique
IPC分类号： H01L23/552 , H01L23/04 , H01L23/498 , H01L23/66 , H01L25/065 , H01L25/16 , H05K9/00 , B82Y10/00 , H01L2223/6616 , H01L2223/6683 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/32165 , H01L2224/32225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06548 , H01L2225/06572 , H01L23/3677 , H01L23/373 , H01L23/49827 , H01L23/49838 , H01L23/49877 , H01L23/5384 , H01L23/5385 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L29/0676 , H01L29/413 , H01L2924/00014 , H01L2924/01006 , H01L2924/14 , H01L2924/1421 , H01L2924/1423 , H01L2924/157 , H01L2924/3025 , H05K9/0022
摘要： A method of fabricating an electrical guard structure for providing signal isolation is provided. The method includes providing a substrate having a mounting surface comprising a first area for hosting at least one electronic component. The method further comprises synthesizing a plurality of thread-like structures over the substrate to collectively form one or more electrically conductive projections extending transverse to the mounting surface. The one or more electrically conductive projections include one or more wall-like structures which are elongate parallel to the mounting surface. The electrically conductive projections can be transferred to another surface such as a major surface of a second substrate. There are further provided a support structure and a guard structure having the wall-like electrically conductive projections which are electrically grounded when in use to provide signal isolation.

2. 发明申请

WO2021202074A1 MULTI LEVEL RADIO FREQUENCY (RF) INTEGRATED CIRCUIT COMPONENTS INCLUDING PASSIVE DEVICES 审中-公开
公开(公告)号：WO2021202074A1
公开(公告)日：2021-10-07
申请号：PCT/US2021/021845
申请日：2021-03-11
申请人： CREE, INC.
发明人： WILSON, Richard , CHIDURALA, Madhu
IPC分类号： H01L23/66 , H03F1/56 , H01L2223/6611 , H01L2223/6655 , H01L2223/6672 , H01L2223/6683 , H01L2224/08145 , H01L2224/08225 , H01L2224/16145 , H01L2224/48137 , H01L2224/48157 , H01L2224/48195 , H01L2224/73253 , H01L2224/73265 , H01L23/04 , H01L23/057 , H01L23/4334 , H01L23/49531 , H01L23/49811 , H01L23/49827 , H01L24/08 , H01L24/48 , H01L25/18 , H01L2924/19107
摘要： A multi-level radio frequency (RF) integrated circuit component includes an upper level including at least one inductor, and a lower level including at least one conductive element that provides electrical connection to the at least one inductor. The lower level separates the at least one inductor from a lower surface that is configured to be attached to a conductive pad. Related integrated circuit device packages are also discussed.

3. 发明申请

WO2021122987A1 INTEGRATED CIRCUIT PACKAGES TO MINIMIZE STRESS ON A SEMICONDUCTOR DIE 审中-公开
公开(公告)号：WO2021122987A1
公开(公告)日：2021-06-24
申请号：PCT/EP2020/086760
申请日：2020-12-17
申请人： ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
发明人： LAKSHMANAN, Ramji Sitaraman , STENSON, Bernard , FITZGERALD, Padraig Liam , KIERSE, Oliver , TWOHIG, Michael James , FLYNN, Michael John , O'SULLIVAN, Laurence Brendan
IPC分类号： H01L21/52 , H01L23/04 , H01L2224/04 , H01L2224/0401 , H01L2224/04042 , H01L2224/056 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/2405 , H01L2224/24227 , H01L2224/245 , H01L2224/2919 , H01L2224/29294 , H01L2224/32013 , H01L2224/32014 , H01L2224/32225 , H01L2224/32237 , H01L2224/33183 , H01L2224/40225 , H01L2224/48225 , H01L2224/48227 , H01L2224/48463 , H01L2224/73253 , H01L2224/73265 , H01L2224/81207 , H01L2224/82002 , H01L2224/82106 , H01L2224/83192 , H01L2224/83862 , H01L2224/83868 , H01L2224/83871 , H01L2224/83874 , H01L2224/85002 , H01L2224/85005 , H01L2224/85801 , H01L2224/9205 , H01L23/041 , H01L23/06 , H01L23/13 , H01L23/20 , H01L23/49811 , H01L23/49833 , H01L23/49838 , H01L23/562 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/85 , H01L24/92 , H01L2924/15153 , H01L2924/15311 , H01L2924/16152 , H01L2924/16196 , H01L2924/163
摘要： An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.

4. 发明申请

WO2022239696A1 半導体装置审中-公开
公开(公告)号：WO2022239696A1
公开(公告)日：2022-11-17
申请号：PCT/JP2022/019513
申请日：2022-05-02
申请人：ローム株式会社
发明人：神田　沢水
IPC分类号： H01L21/60 , H01L23/48 , H01L25/07 , H01L25/18 , H01L2224/0603 , H01L2224/32245 , H01L2224/40245 , H01L2224/48247 , H01L2224/73221 , H01L2224/73265 , H01L2924/181
摘要：半導体装置は、第１電極を有する半導体素子と、前記第１電極に対向する第１接合部を有する導通部材と、前記第１電極と前記第１接合部との間に介在する接合層と、前記第１電極および前記第１接合部のいずれかに接合された規制体とを備える。前記半導体素子の厚さ方向に対して直交する方向において、前記規制体は、前記接合層に対向している。

5. 发明申请

WO2021199553A1 POWER MODULE ASSEMBLY, PROCESS FOR MANUFACTURING POWER MODULE ASSEMBLY, AND POWER MODULE 审中-公开
公开(公告)号：WO2021199553A1
公开(公告)日：2021-10-07
申请号：PCT/JP2020/049310
申请日：2020-12-28
申请人： MITSUBISHI ELECTRIC CORPORATION , MITSUBISHI ELECTRIC R&D CENTRE EUROPE B.V.
发明人： BRANDELERO, Julio , VOYER, Nicolas
IPC分类号： H01L23/488 , H01L21/60 , H01L2224/2732 , H01L2224/27334 , H01L2224/279 , H01L2224/29011 , H01L2224/29076 , H01L2224/2919 , H01L2224/2929 , H01L2224/29294 , H01L2224/29311 , H01L2224/29339 , H01L2224/29347 , H01L2224/32012 , H01L2224/32014 , H01L2224/32227 , H01L2224/48227 , H01L2224/73265 , H01L2224/83121 , H01L2224/83192 , H01L2224/83815 , H01L2224/8384 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/83 , H01L2924/181 , H01L2924/351 , H01L2924/3512
摘要： A power module assembly comprises a power die (5) attached to a substrate (1) through a joint layer (41) comprising solid pads (4, 4') of metal alloy material connecting electrically and thermally said power die (5) to said substrate (1), wherein said solid pads (4, 4') are located within cells (200, 201, 202) of a grid (2, 2') made of an elastic material and having cell walls (20) extending between the surface of the substrate (1) and the surface of the die (5) facing each other. A process for manufacturing the power module assembly comprises: providing an elastic grid (2, 2') having a length and a width corresponding to the length and width of the semiconductor die (5) to attach; placing and attaching said elastic grid (2, 2') on the substrate (1); placing a stencil (3) forming a frame with a shape adapted to a contour of the semiconductor die (5) on the substrate (1) around the grid (2, 2') and applying paste (9) with a screen printing technique in the area defined by the stencil (3); removing the stencil (3); placing the power semiconductor die (5) on top of the paste (9); applying pressure on the die (5) to compress the assembly made of the die (5), the grid (2, 2') and paste (9) and the substrate (1); heating (10) the assembly either to melt the metal particles of the paste (9) or to sinter the particles; and cooling the assembly to provide solid pads (4, 4') embedded in said grid (2, 2'). The grid (2, 2') acts as an elastic barrier, preventing crack propagation within the joint layer (41) while providing little thermal resistance. The grid (2,2 ') may be a honeycomb shaped (2) or square shaped (21) lattice. A grid cell (200, 201, 202) size may be at least ten times bigger than a grid wall (20) width. The width of walls (20) of the grid cells (200,201, 202) may be larger than half of the thickness of the joint layer (41). The grid material may be such that the walls (20) of the grid (2, 2') contract with an increase of temperature, helping applying a high pressure on the paste (9) during the heating process phase and allowing the solid paste (4, 4') to expand in the hot areas without extra constraint during the operation of the power semiconductor die (5), leaving room to the rest of the joint layer (41) to expand under high temperature, relaxing the stress. The grid (2, 2') may be a polyimide grid, in particular, made out of a single- or double-faced adhesive polyimide tape. The grid (21) may comprise peripheral cells (201) of a reduced width with respect to central cells (202) of the grid (21), limiting propagation of cracks so that the cracks cannot grow from the sides or corners more than the width of the reduced width cells (201) while inner cells (202) may be larger to reduce the degradation of the overall thermal resistance. The cells (200, 201,202) of the grid (2, 2') may be shaped through laser cutting. The elastic grid (2, 2') may be formed as a tape with adhesive on both sides and be glued on both the substrate (1) and the die (5). The elastic grid (2, 2') may be placed and attached on the substrate (1) with a screen printing technique using an ink charged with high thermal conductive particles.

6. 发明申请

WO2021140572A1 半導体装置および電力変換装置审中-公开
公开(公告)号：WO2021140572A1
公开(公告)日：2021-07-15
申请号：PCT/JP2020/000192
申请日：2020-01-07
申请人：三菱電機株式会社
发明人：堀口　剛司 , 椋木　康滋
IPC分类号： H01L23/58 , H01L25/07 , H01L21/60 , H01L2224/48091 , H01L2224/49111 , H01L2224/73265 , H01L2924/19107
摘要：半導体装置（１００）は、第１電極（１１）と第２電極（１２）とを有する半導体素子（１）と、第１電極（１１）と接合部を介して電気的に接続された第１導電体（７）と、第１方向（Ａ）において第１導電体（７）と絶縁体（８）を挟むように積層された第２導電体（９）と、第２導電体（９）上に配置されかつ第２導電体（９）と電気的に接続されている第１端子（３）と、第２導電体（９）上に配置されている第２端子（４）と、第２電極（１２）と第２端子（４）とを電気的に接続する複数の配線部材（５）とを備える。

7. 发明申请

WO2022267163A1 滤波器射频模组封装结构及其制作方法审中-公开
公开(公告)号：WO2022267163A1
公开(公告)日：2022-12-29
申请号：PCT/CN2021/108557
申请日：2021-07-27
申请人：广东省科学院半导体研究所
发明人：燕英强 , 胡川 , 向迅 , 郑伟 , 陈志涛 , 陈志宽
IPC分类号： H01L23/66 , H01L2224/16225 , H01L2224/16235 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L25/072 , H01L2924/181 , H01Q1/2283
摘要：一种滤波器射频模组封装结构(010)及其制作方法，涉及半导体领域。滤波器射频模组封装结构(010)的第一滤波器芯片(200)包括芯片主体(210)和墙体结构(220)，墙体结构(220)连接于芯片主体(210)的功能面上；墙体结构(220)、功能面以及基板(100)共同围成封闭的腔体(230)，或者，墙体结构(220)和功能面共同围成封闭的腔体(230)；包封材料(500)包裹第一滤波器芯片(200)。通过令墙体结构(220)和芯片主体(210)形成封闭的腔体(230)，或者令墙体结构(220)、芯片主体(210)和基板(100)之间共同围成封闭的腔体(230)，可以减少胶膜的使用，避免包封材料(500)体积过大；同时也能够避免包封材料(500)进入到腔体(230)内影响芯片的功能。

8. 发明申请

WO2022002464A1 LEISTUNGSMODUL MIT MINDESTENS DREI LEISTUNGSEINHEITEN 审中-公开
公开(公告)号：WO2022002464A1
公开(公告)日：2022-01-06
申请号：PCT/EP2021/061669
申请日：2021-05-04
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： SCHMENGER, Jens , KÖGLER, Roman , LUFT, Alexander , NAMYSLO, Lutz , ROPPELT, Bernd , SCHWINN, Thomas
IPC分类号： H01L23/467 , H01L23/373 , H01L25/07 , H01L21/48 , H01L23/498 , H01L23/538 , H01L21/4882 , H01L2224/06181 , H01L2224/29111 , H01L2224/2919 , H01L2224/32227 , H01L2224/40227 , H01L2224/45014 , H01L2224/45015 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/8384 , H01L23/3735 , H01L23/49811 , H01L23/5385 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/40 , H01L24/48 , H01L25/072 , H01L25/115 , H01L2924/1203 , H01L2924/1304 , H01L2924/19107
摘要： Die Erfindung betrifft ein Leistungsmodul (2) mit mindestens zwei Leistungseinheiten (4), welche jeweils mindestens einen Leistungshalbleiter (6) und ein Substrat (8) umfassen. Um den erforderlichen Bauraum des Leistungsmoduls zu verringern und eine Entwärmung zu verbessern, wird vorgeschlagen, dass der jeweils mindestens eine Leistungshalbleiter (6), insbesondere stoffschlüssig, mit dem jeweiligen Substrat (8) verbunden ist, wobei die Substrate (8) der mindestens zwei Leistungseinheiten (4) jeweils unmittelbar stoffschlüssig mit einer Oberfläche (24) eines gemeinsamen Kühlkörpers (26) verbunden sind.

9. 发明申请

WO2021262538A1 RADIO FREQUENCY TRANSISTOR AMPLIFIER PACKAGE 审中-公开
公开(公告)号：WO2021262538A1
公开(公告)日：2021-12-30
申请号：PCT/US2021/037978
申请日：2021-06-18
申请人： CREE, INC.
发明人： KOMPOSCH, Alexander , MU, Qianli , WANG, Kun , WOO, Eng Wah
IPC分类号： H01L23/66 , H01L23/495 , H01L2223/6611 , H01L2223/6655 , H01L2223/6683 , H01L2223/6688 , H01L2224/48247 , H01L2224/49111 , H01L2224/49175 , H01L2224/73265 , H01L23/49541 , H01L23/49562 , H01L23/49575 , H01L2924/00014
摘要： A radio frequency (RF) transistor amplifier package includes a submount, and first and second leads extending from a first side of the submount. The first and second leads are configured to provide RF signal connections to one or more transistor dies on a surface of the submount. At least one rivet is attached to the surface of the submount between the first and second leads on the first side. One or more corners of the first side of the submount may be free of rivets. Related devices and associated RF leads and non-RF leads are also discussed.

10. 发明申请

WO2021202038A1 SEMICONDUCTOR DEVICES WITH REDISTRIBUTION STRUCTURES CONFIGURED FOR SWITCHABLE ROUTING 审中-公开
公开(公告)号：WO2021202038A1
公开(公告)日：2021-10-07
申请号：PCT/US2021/020549
申请日：2021-03-02
申请人： MICRON TECHNOLOGY, INC.
发明人： JENSEN, Travis, M. , HEMBREE, David, R.
IPC分类号： H01L25/065 , H01L23/485 , H01L23/525 , H01L21/60 , H01L2224/0235 , H01L2224/02375 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/05548 , H01L2224/131 , H01L2224/16145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73207 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06527 , H01L2225/06586 , H01L24/02 , H01L25/0657 , H01L25/50 , H01L2924/15311
摘要： Semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a first semiconductor die including a first redistribution structure and a second semiconductor die including a second redistribution structure. The first and second semiconductor dies can be mounted on a package substrate such that the first and second redistribution structures are aligned with each other. In some embodiments, an interconnect structure can be positioned between the first and second semiconductor dies to electrically couple the first and second redistribution structures to each other. The first and second redistribution structures can be configured such that signal routing between the first and second semiconductor dies can be altered based on the location of the interconnect structure.

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