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1. 发明申请

WO2021200057A2 DEVICE AND METHOD FOR INCREASING THE RELIABILITY OF A POWER MODULE 审中-公开
公开(公告)号：WO2021200057A2
公开(公告)日：2021-10-07
申请号：PCT/JP2021/010262
申请日：2021-03-08
申请人： MITSUBISHI ELECTRIC CORPORATION , MITSUBISHI ELECTRIC R&D CENTRE EUROPE B.V.
发明人： BRANDELERO, Julio Cezar , MOLLOV, Stefan
IPC分类号： H01L23/49 , H01L25/07 , H01L2224/05624 , H01L2224/45014 , H01L2224/45124 , H01L2224/45139 , H01L2224/45147 , H01L2224/4847 , H01L2224/4851 , H01L2224/49111 , H01L2224/85948 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/85 , H01L25/072 , H01L2924/00014 , H01L2924/10253 , H01L2924/13055 , H01L2924/13091 , H01L2924/3512 , H01L2924/35121 , H01L2924/37001 , H01L2924/386
摘要： The present invention concerns a method and a device for increasing the reliability of a power module composed of plural power semiconductors that are connected in parallel, the power semiconductors being connected to the external pins of the package of the power module through metallic connections. The invention: - selects one power semiconductor among the power semiconductors connected in parallel according to a criterion, - applies a same input pattern to the not selected power semiconductors connected in parallel, - increases the temperature of the selected power semiconductor in order to reach a target temperature of the power semiconductor during a time duration in order to achieve and interface grain homogenisation of the metallic connections of the selected power semiconductor, - applies the same input pattern to the selected power semiconductor after the time duration.

2. 发明申请

WO2015069184A1 A GUARD STRUCTURE FOR SIGNAL ISOLATION 审中-公开
公开(公告)号：WO2015069184A1
公开(公告)日：2015-05-14
申请号：PCT/SG2014/000470
申请日：2014-10-07
申请人： THALES SOLUTIONS ASIA PTE LTD. , CNRS - CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (EPST) , NANYANG TECHNOLOGICAL UNIVERSITY
发明人： TAN, Dunlin , YU, Jong Jen , HEE, David , TAY, Beng Kang , BAILLARGEAT, Dominique
IPC分类号： H01L23/552 , H01L23/04 , H01L23/498 , H01L23/66 , H01L25/065 , H01L25/16 , H05K9/00 , B82Y10/00 , H01L2223/6616 , H01L2223/6683 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/32165 , H01L2224/32225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06548 , H01L2225/06572 , H01L23/3677 , H01L23/373 , H01L23/49827 , H01L23/49838 , H01L23/49877 , H01L23/5384 , H01L23/5385 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L29/0676 , H01L29/413 , H01L2924/00014 , H01L2924/01006 , H01L2924/14 , H01L2924/1421 , H01L2924/1423 , H01L2924/157 , H01L2924/3025 , H05K9/0022
摘要： A method of fabricating an electrical guard structure for providing signal isolation is provided. The method includes providing a substrate having a mounting surface comprising a first area for hosting at least one electronic component. The method further comprises synthesizing a plurality of thread-like structures over the substrate to collectively form one or more electrically conductive projections extending transverse to the mounting surface. The one or more electrically conductive projections include one or more wall-like structures which are elongate parallel to the mounting surface. The electrically conductive projections can be transferred to another surface such as a major surface of a second substrate. There are further provided a support structure and a guard structure having the wall-like electrically conductive projections which are electrically grounded when in use to provide signal isolation.

3. 发明申请

WO2022209029A1 METHOD FOR IMPROVING THE MICROSTRUCTURE OF THE CONNECTION PORTION OF A BOND WIRE AS WELL AS THE RESULTING DEVICE 审中-公开
公开(公告)号：WO2022209029A1
公开(公告)日：2022-10-06
申请号：PCT/JP2021/045431
申请日：2021-12-03
申请人： MITSUBISHI ELECTRIC CORPORATION , MITSUBISHI ELECTRIC R&D CENTRE EUROPE B.V.
发明人： PICHON, Pierre-Yves , BRANDELERO, Julio , OUHAB, Merouane , DEGRENNE, Nicolas
IPC分类号： H01L21/607 , H01L23/49 , B23K20/00 , B23K20/004 , H01L2224/04042 , H01L2224/05014 , H01L2224/05015 , H01L2224/056 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/45147 , H01L2224/48227 , H01L2224/48247 , H01L2224/48458 , H01L2224/4851 , H01L2224/78315 , H01L2224/78901 , H01L2224/85205 , H01L2224/8593 , H01L2224/85947 , H01L2224/85948 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/85
摘要： The invention relates to producing a semiconductor chip-metal wire bond, by performing the steps of bonding a wire having a metal body to the semiconductor chip so as to connect the wire to the semiconductor chip, the bond metal having a polycrystalline microstructure, and deforming a bonding region of the metal body in contact with to the semiconductor chip, the deformed bonding region being characterized by a relative cross section area change given by (AA), where Af is a final cross section area and A0 is an initial cross section area, the deformation involving an increase of a dislocation density in the microstructure of at least a portion of the bonding region.

4. 发明申请

WO2022043033A1 ELECTRONIC DEVICE, PACKAGE AND SEMICONDUCTOR CHIP THEREFORE 审中-公开
公开(公告)号：WO2022043033A1
公开(公告)日：2022-03-03
申请号：PCT/EP2021/072081
申请日：2021-08-06
申请人： HITACHI ENERGY SWITZERLAND AG [CH]/[CH]
发明人： STIASNY, Thomas , WIKSTROEM, Tobias
IPC分类号： H01L21/603 , H01L23/051 , H01L25/10 , H01L2224/03602 , H01L2224/0361 , H01L2224/04 , H01L2224/04042 , H01L2224/05011 , H01L2224/05012 , H01L2224/05551 , H01L2224/05552 , H01L2224/05558 , H01L2224/05624 , H01L2224/0603 , H01L2224/06051 , H01L2224/06181 , H01L2224/48091 , H01L2224/73201 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/72 , H01L24/73 , H01L25/117
摘要： An electronic device (1) comprises a semiconductor chip (2) having an electrical contact metallization (3), and a package (4) having an electrical contact disc (5). The electrical contact metallization (3) and the electrical contact disc (5) are in direct contact on a contact face (45) so that the semiconductor chip (2) is electrically connected with the package (4). At the contact face (45), at least one of the electrical contact metallization (3) and the electrical contact disc (5) comprises a geometric structuring (6) (a surface pattern) fashioned as at least one recessed area. A mean roughness of a top face (50) of the electrical contact disc (5) facing the electrical contact metallization (3) may be between 0.2 pm and 1 pm, wherein, because of the mean roughness, the top face (50) is configured to penetrate an oxide layer (31) of the electrical contact metallization (3) at the contact face (45) (e.g., native oxide on an aluminum metallization (3) ). The electrical contact metallization (3) may be of multilayer fashion and comprise at least one interrupted sub-layer (33) and at least one continuous sub-layer (34), the continuous sub-layer (34) being located at the contact face (45), wherein the at least one interrupted sub-layer (33) and the at least one continuous sub-layer (34) may be of the same material or of different materials, but have different thicknesses. All of the electrical contact metallization (3) and/or of the electrical contact disc (5) may be configured to be on the same electric potential. The geometric structuring (6) may consist of or comprise at least one of the following shapes: circle, spiral, rectangle, triangle, hexagon, honeycomb and may comprise interruptions. The semiconductor chip (2) may comprise a further electrical contact metallization (7) having an even and smooth further contact face (70), wherein, seen in top view, an overall size of the further contact face (70) is smaller than that of the electrical contact metallization (3) by at least a factor of 1.5 and by at most a factor of 5, and wherein, because of the geometric structuring (6), at the contact face (45) an effective size of the electrical contact metallization (3) is the same as the overall size of the further contact face (70), with a tolerance of at most a factor of 1.2, wherein the electrical contact metallization (3) and the further electrical contact metallization (7) may be located at opposite main sides of the semiconductor chip (2) and the semiconductor chip (2) is configured to be electrically contacted with a contact force of at least 0.3 kN/cm and of at most 2 kN/cm. The package (4) may comprise an electrically insulating jacket (41) and an electrical metal contact plate (42), wherein the semiconductor chip (2) and the electrical contact disc (5) as well as the metal plate (42) are arranged in the jacket (41) and are aligned in parallel with each other, wherein, seen in top view onto the contact face (45), sizes of the semiconductor chip (2) and the electrical contact disc (5) differ from each other by at most a factor of 1.3, and wherein the electrical contact disc (5) is located between the semiconductor chip (2) and the contact plate (42). The semiconductor chip (2), the electrical contact disc (5) and the optional contact plate (42) can be of circular shape seen in top view. The electronic device (1) may be a press pack power semiconductor device. The pressure at a given contact force is increased in the electronic device (1) by reducing the overall contact area, that is, a contact face (45) between the electrical contact metallization (3) of the semiconductor chip (2) and the electrical contact disc (5) of the package (4), to form a reliable and stable dry interface electric contact and avoid 'too low pressure1 effects, for example: for an anode side metallization of an IGCT or of an GTO, as the clamping force is typically limited for by the mechanical stability of the cathode side metallization which is in total significantly lower in contact area and more fragile due to the segmentation of a high metal stack; for a metallization of a free-floating side of a bonded diode used at low clamping forces, for example, when clamped with an IGCT - for a free-floating anode side, the probability of electromigration may be higher; or for an anode and cathode side metallization of a free-floating diode or of a free-floating plus diode clamped at relatively low pressures.

5. 发明申请

WO2021130110A1 POWER MODULE WITH IMPROVED ELECTRICAL AND THERMAL CHARACTERISTICS 审中-公开
公开(公告)号：WO2021130110A1
公开(公告)日：2021-07-01
申请号：PCT/EP2020/086965
申请日：2020-12-18
申请人： DANFOSS SILICON POWER GMBH
发明人： BERGMANN, Jörg , STRÖBEL-MAIER, Henning
IPC分类号： H01L23/66 , H01L23/498 , H01L23/538 , H01L23/00 , H01L25/07 , H02M7/00 , H01L23/3735 , H01L23/49811 , H01L23/49844 , H01L23/5386 , H01L24/48 , H01L24/49 , H01L25/072 , H02M7/003
摘要： A power module (1) comprising a group of at least three rectangular electrical power components (11, 12, 13, 14, 23, 24, 25, 26) arranged on a substrate (2), wherein in that at least one side (31) of at least one of the rectangular electrical power components (11, 14) is not orthogonal or parallel to a line (3) that passes through the geometric centres of the remaining rectangular electrical power components (12, 13) of the group.

6. 发明申请

WO2022212619A1 ISOLATED TEMPERATURE SENSOR DEVICE PACKAGE 审中-公开
公开(公告)号：WO2022212619A1
公开(公告)日：2022-10-06
申请号：PCT/US2022/022710
申请日：2022-03-31
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： TUNCER, Enis
IPC分类号： G01K1/08 , H01L21/4821 , H01L21/565 , H01L2224/48175 , H01L23/3107 , H01L23/34 , H01L23/49513 , H01L23/49558 , H01L23/49568 , H01L23/49586 , H01L24/48
摘要： In a described example, an apparatus (401) includes: a package substrate (403) having a die pad (409) configured for mounting a semiconductor die, a first lead (411) connected to the die pad, and a second lead (405) spaced from and electrically isolated from the die pad; a spacer dielectric (413) mounted on the die pad; a semiconductor die (310) including a temperature sensor mounted on the spacer dielectric; electrical connections (417) coupling the semiconductor die to the second lead; and mold compound (419) covering the semiconductor die, the die pad, the electrical connections, and a portion of the package substrate, with portions of the first lead (411) and portions of the second lead (405) exposed from the mold compound to form terminals for a packaged temperature sensor device.

7. 发明申请

WO2021202074A1 MULTI LEVEL RADIO FREQUENCY (RF) INTEGRATED CIRCUIT COMPONENTS INCLUDING PASSIVE DEVICES 审中-公开
公开(公告)号：WO2021202074A1
公开(公告)日：2021-10-07
申请号：PCT/US2021/021845
申请日：2021-03-11
申请人： CREE, INC.
发明人： WILSON, Richard , CHIDURALA, Madhu
IPC分类号： H01L23/66 , H03F1/56 , H01L2223/6611 , H01L2223/6655 , H01L2223/6672 , H01L2223/6683 , H01L2224/08145 , H01L2224/08225 , H01L2224/16145 , H01L2224/48137 , H01L2224/48157 , H01L2224/48195 , H01L2224/73253 , H01L2224/73265 , H01L23/04 , H01L23/057 , H01L23/4334 , H01L23/49531 , H01L23/49811 , H01L23/49827 , H01L24/08 , H01L24/48 , H01L25/18 , H01L2924/19107
摘要： A multi-level radio frequency (RF) integrated circuit component includes an upper level including at least one inductor, and a lower level including at least one conductive element that provides electrical connection to the at least one inductor. The lower level separates the at least one inductor from a lower surface that is configured to be attached to a conductive pad. Related integrated circuit device packages are also discussed.

8. 发明申请

WO2021122987A1 INTEGRATED CIRCUIT PACKAGES TO MINIMIZE STRESS ON A SEMICONDUCTOR DIE 审中-公开
公开(公告)号：WO2021122987A1
公开(公告)日：2021-06-24
申请号：PCT/EP2020/086760
申请日：2020-12-17
申请人： ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
发明人： LAKSHMANAN, Ramji Sitaraman , STENSON, Bernard , FITZGERALD, Padraig Liam , KIERSE, Oliver , TWOHIG, Michael James , FLYNN, Michael John , O'SULLIVAN, Laurence Brendan
IPC分类号： H01L21/52 , H01L23/04 , H01L2224/04 , H01L2224/0401 , H01L2224/04042 , H01L2224/056 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/2405 , H01L2224/24227 , H01L2224/245 , H01L2224/2919 , H01L2224/29294 , H01L2224/32013 , H01L2224/32014 , H01L2224/32225 , H01L2224/32237 , H01L2224/33183 , H01L2224/40225 , H01L2224/48225 , H01L2224/48227 , H01L2224/48463 , H01L2224/73253 , H01L2224/73265 , H01L2224/81207 , H01L2224/82002 , H01L2224/82106 , H01L2224/83192 , H01L2224/83862 , H01L2224/83868 , H01L2224/83871 , H01L2224/83874 , H01L2224/85002 , H01L2224/85005 , H01L2224/85801 , H01L2224/9205 , H01L23/041 , H01L23/06 , H01L23/13 , H01L23/20 , H01L23/49811 , H01L23/49833 , H01L23/49838 , H01L23/562 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/85 , H01L24/92 , H01L2924/15153 , H01L2924/15311 , H01L2924/16152 , H01L2924/16196 , H01L2924/163
摘要： An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.

9. 发明申请

WO2022002464A1 LEISTUNGSMODUL MIT MINDESTENS DREI LEISTUNGSEINHEITEN 审中-公开
公开(公告)号：WO2022002464A1
公开(公告)日：2022-01-06
申请号：PCT/EP2021/061669
申请日：2021-05-04
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： SCHMENGER, Jens , KÖGLER, Roman , LUFT, Alexander , NAMYSLO, Lutz , ROPPELT, Bernd , SCHWINN, Thomas
IPC分类号： H01L23/467 , H01L23/373 , H01L25/07 , H01L21/48 , H01L23/498 , H01L23/538 , H01L21/4882 , H01L2224/06181 , H01L2224/29111 , H01L2224/2919 , H01L2224/32227 , H01L2224/40227 , H01L2224/45014 , H01L2224/45015 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/8384 , H01L23/3735 , H01L23/49811 , H01L23/5385 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/40 , H01L24/48 , H01L25/072 , H01L25/115 , H01L2924/1203 , H01L2924/1304 , H01L2924/19107
摘要： Die Erfindung betrifft ein Leistungsmodul (2) mit mindestens zwei Leistungseinheiten (4), welche jeweils mindestens einen Leistungshalbleiter (6) und ein Substrat (8) umfassen. Um den erforderlichen Bauraum des Leistungsmoduls zu verringern und eine Entwärmung zu verbessern, wird vorgeschlagen, dass der jeweils mindestens eine Leistungshalbleiter (6), insbesondere stoffschlüssig, mit dem jeweiligen Substrat (8) verbunden ist, wobei die Substrate (8) der mindestens zwei Leistungseinheiten (4) jeweils unmittelbar stoffschlüssig mit einer Oberfläche (24) eines gemeinsamen Kühlkörpers (26) verbunden sind.

10. 发明申请

WO2021244703A2 DRAHTBONDVORRICHTUNG UND BETRIEBSVERFAHREN HIERFÜR 审中-公开
公开(公告)号：WO2021244703A2
公开(公告)日：2021-12-09
申请号：PCT/DE2021/100457
申请日：2021-05-26
申请人： HESSE GMBH
发明人： WALTHER, Frank
IPC分类号： H01L21/607 , B23K20/10 , H01L2224/45147 , H01L2224/48221 , H01L2224/48225 , H01L2224/48472 , H01L2224/78252 , H01L2224/78343 , H01L2224/7855 , H01L2224/78611 , H01L2224/78824 , H01L2224/78841 , H01L2224/789 , H01L2224/85205 , H01L2224/85206 , H01L2224/859 , H01L2224/85986 , H01L24/45 , H01L24/48 , H01L24/78 , H01L24/85
摘要： Die Erfindung betrifft eine Bondvorrichtung mit einem in eine Höhenrichtung verfahrbaren Bondkopf umfassend ein Bondwerkzeug (8) mit einer zur Anlage an ein Bondgut (23) ausgebildeten Werkzeugspitze (9), umfassend einen Transducer (3), an dem das Bondwerkzeug (8) auswechselbar gehalten ist und der eingerichtet ist zur Anregung des Bondwerkzeugs (8) zu Ultraschallschwingungen, umfassend eine Heizeinrichtung (13) zur jedenfalls lokalen Erwärmung des Bondwerkzeugs und umfassend einen Träger (22), an dem die Heizeinrichtung (13) sowie der Transducer (3) mit dem Bondwerkzeug (8) gehalten sind, wobei der Transducer (3) mit dem Bondwerkzeug (8) relativ beweglich zu der Heizeinrichtung (13) an dem Träger (22) gehalten ist derart, dass in einer Heizstellung eine Werkzeugkontaktfläche (11) des Bondwerkzeugs (8) an eine Heizkontaktfläche (14) der Heizeinrichtung (13) angelegt ist und dass in einer Bondstellung das Bondwerkzeug (8) beabstandet zu der Heizkontaktfläche (14) der Heizeinrichtung (13) vorgesehen ist. Ferner betrifft die Erfindung ein Betriebsverfahren für diese Bondvorrichtung.

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