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1. 发明申请

WO2015189150A3 FEEDBACK DELAY REDUCTION IN FORCE FEEDBACK DEVICES 审中-公开
标题翻译：反馈延迟减少在力反馈设备
公开(公告)号：WO2015189150A3
公开(公告)日：2016-02-04
申请号：PCT/EP2015062711
申请日：2015-06-08
申请人： BOSCH GMBH ROBERT
发明人： BALACHANDRAN GANESH , PETKOV VLADIMIR
IPC分类号： H03M3/00
CPC分类号： H04R3/00 , H03M3/37 , H03M3/406 , H03M3/422 , H03M3/452 , H03M3/454 , H04R2201/003
摘要： A feedback circuit provides a feedback signal to a transducer. The feedback circuit includes an ADC that generates digital representations of a feedback signal, digital controller that identifies adjustments for the feedback, and DAC that generates an analog output of the adjusted feedback signal. The digital controller performs speculative computation to identify adjustments for the feedback signal output for each output value from the ADC prior to receiving the output from the ADC. The ADC and DAC include sigma-delta modulators that operate with a zero clock cycle delay in a forward path. The ADC, digital controller, and DAC generate adjustments to the feedback output signal with reduced delay that reduce phase lag and improve phase margin to maintain stability in the transducer.
摘要翻译：反馈电路向换能器提供反馈信号。反馈电路包括产生反馈信号的数字表示的ADC，识别反馈的调节的数字控制器以及产生经调整的反馈信号的模拟输出的DAC。在接收ADC的输出之前，数字控制器执行推测计算以识别来自ADC的每个输出值的反馈信号输出的调整。 ADC和DAC包括在正向通路中以零时钟周期延迟运行的Σ-Δ调制器。 ADC，数字控制器和DAC通过减小延迟来产生对反馈输出信号的调整，从而减少相位滞后并提高相位裕度，以保持传感器的稳定性。

2. 发明申请

WO2014149358A1 INTERLEAVED MULTIPATH DIGITAL POWER AMPLIFICATION 审中-公开
标题翻译：交互式多路数字功率放大
公开(公告)号：WO2014149358A1
公开(公告)日：2014-09-25
申请号：PCT/US2014/017651
申请日：2014-02-21
申请人： LSI Technologies Inc.
发明人： KISS, Peter , ABDELLI, Said, E. , LATURELL, Donald, R. , WILSON, Ross, S. , MACDONALD, James, F.
IPC分类号： H04L27/02 , H03M3/00 , H03F3/217 , H03H17/00 , H03H17/02
CPC分类号： H03M9/00 , H03F3/217 , H03F2200/331 , H03H17/0018 , H03H17/0273 , H03H17/028 , H03M3/30 , H03M3/37 , H03M3/47 , H04L25/02 , H04L27/02
摘要： In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit- stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit- stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit- stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit- stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects.
摘要翻译：在一个实施例中，射频发射机的功率放大系统包括数字信号源，该数字信号源向交织的比特流发生器提供数字输入信号，该数字信号源将数字切换信号输出到开关功率放大器。交错比特流发生器具有八路交织架构，有助于降低交错比特流发生器的有效时钟速率要求。交错比特流生成器包括用于接收数字输入信号并且将八个分数延迟的数字输出信号输出到比特流生成阵列的分数延迟滤波器阵列，其适于将八个对应的比特流输出到串行化器块，将八个比特流组合成数字切换信号。可以调整交错信号的相对相位以实现某些期望的效果。

3. 发明申请

WO01071922A2 EXCESS DELAY COMPENSATION IN A DELTA SIGMA MODULATOR ANALOG-TO-DIGITAL CONVERTER 审中-公开
标题翻译： DELTA SIGMA调制器模拟数字转换器中的更多延迟补偿
公开(公告)号：WO01071922A2
公开(公告)日：2001-09-27
申请号：PCT/US2001/008936
申请日：2001-03-21
IPC分类号： H03M3/02 , H03M3/04
CPC分类号： H03M3/37 , H03M3/406 , H03M3/424 , H03M3/454
摘要： A high-performance delta sigma analog-to-digital converter (90). The high-performance delta sigma analog-to-digital converter (90) includes a first mechanism (12, 52, 38, 16, 92) for converting an input analog signal (26) to a digital output signal (44). The first mechanism (12, 52, 38, 16, 92) is characterized by a transfer function that is altered relative to an ideal transfer function. A second mechanism (86, 88, 92) compensates for the alteration in the transfer function via a single additional digital-to-analog converter (88). In a specific embodiment, the alteration includes an additional pole and an additional zero induced by feedback delays in the first mechanism (12, 52, 38, 16, 92). The feedback delays include signal dependent jitter delay and feedback digital-to-analog converter cell switching delays. The second mechanism (86, 88, 92) includes an additional latch (86) that compensates for the signal dependent jitter delay. The first mechanism (12, 52, 38, 16, 92) includes a resonator (12, 52) and a quantizer (16). The second mechanism (86, 88, 92) includes a feedback path (92) from an output of the quantizer (16) to the resonator (52). The feedback path (92) includes a first latch (18) positioned between an output of the quantizer (16) and the additional digital-to-analog converter (88). The additional latch (86) is positioned at an output of the first latch (18) and eliminates signal dependent jitter delay in the analog-to-digital converter (90). The additional feedback digital-to-analog converter (88) is a non-return-to-zero digital-to-analog converter, an output of which is connected to the resonator.
摘要翻译：高性能Σ-Σ模数转换器（90）。高性能Δ西格玛模数转换器（90）包括用于将输入模拟信号（26）转换为数字输出信号（44）的第一机构（12,52,38,16,92）。第一机构（12,52,38,16,92）的特征在于相对于理想传递函数改变的传递函数。第二机构（86,88,92）通过单个附加数模转换器（88）补偿传递函数的变化。在具体实施例中，改变包括附加极点和由第一机构（12,52,38,16,92）中的反馈延迟引起的附加零点。反馈延迟包括信号相关的抖动延迟和反馈数模转换器单元切换延迟。第二机构（86,88,92）包括补偿信号相关抖动延迟的附加锁存器（86）。第一机构（12,52,38,16,92）包括谐振器（12,52）和量化器（16）。第二机构（86,88,92）包括从量化器（16）的输出到谐振器（52）的反馈路径（92）。反馈路径（92）包括位于量化器（16）的输出端和附加数模转换器（88）之间的第一锁存器（18）。附加锁存器（86）位于第一锁存器（18）的输出处，并且消除了模数转换器（90）中与信号相关的抖动延迟。额外的反馈数模转换器（88）是一个非归零数字模拟转换器，其输出端连接到谐振器。

4. 发明申请

WO00025428A1 DELAY COMPENSATION FOR ANALOG-TO-DIGITAL CONVERTER IN SIGMA-DELTA MODULATORS 审中-公开
标题翻译： SIGMA-DELTA调制器中模拟数字转换器的延迟补偿
公开(公告)号：WO00025428A1
公开(公告)日：2000-05-04
申请号：PCT/FR1999/002579
申请日：1999-10-22
IPC分类号： H03M3/02
CPC分类号： H03M3/37 , H03M3/458
摘要： The invention concerns the field of sigma-delta modulators. More particularly it concerns a sigma-delta modulator presenting a propagation delay DELTA t between an analog-to-digital converter (40) input and a digital-to-analog (60) output, and comprising a subtractor located in a direct chain between an amplifying unit (10) and the analog-to-digital converter (40), the amplifying unit (10) output being connected to a first direct input of the subtractor (20), an output of the subtractor (20) being connected to the analog-to-digital converter (40) input; the modulator (100) further comprises a compensating filter (70) located between the subtractor (20) output and a second inverting input of the subtractor (20); when considering a pulse response (RI) of the modulator (100) at the subtractor (20) output, for a pulse sent to the subtractor (20) output, comprising a first part (P1) covering a first interval (l1) of time 0; T [with T > DELTA t and a second part (P2) covering a second interval of time (l2) of time [T; INFINITY [, the compensating filter (70) is designed to contribute to the first part (P1), the amplifying unit (10) is designed to contribute to the second part (P2) only. The sigma-delta modulator can be used in a radar processing chain.
摘要翻译：本发明涉及Σ-Δ调制器领域。更具体地说，它涉及一种Σ-Δ调制器，其呈现模数转换器（40）输入和数模（60）输出之间的传播延迟DELTA t，并且包括位于直接链放大单元（10）和模数转换器（40），放大单元（10）输出连接到减法器（20）的第一直接输入端，减法器（20）的输出端连接到模数转换器（40）输入; 调制器（100）还包括位于减法器（20）输出和减法器（20）的第二反相输入之间的补偿滤波器（70）。当考虑在减法器（20）输出时调制器（100）的脉冲响应（RI），对于发送到减法器（20）输出的脉冲，包括覆盖时间的第一间隔（l1）的第一部分（P1） 0; T [与T> DELTA t和第二部分（P2）覆盖时间的第二时间间隔（l2）[T; INFINITY [，补偿滤波器70被设计成有助于第一部分（P1），放大单元（10）被设计成只对第二部分（P2）贡献。 Σ-Δ调制器可用于雷达处理链。

5. 发明申请

WO2016004122A1 ASYNCHRONOUS ELECTRICAL CIRCUITRY TECHNIQUES FOR PRODUCING STATIONARY CARRIER SIGNAL 审中-公开
标题翻译：用于制作静态载波信号的异步电路技术
公开(公告)号：WO2016004122A1
公开(公告)日：2016-01-07
申请号：PCT/US2015/038690
申请日：2015-06-30
申请人： INDICE SEMICONDUCTOR INC.
发明人： HAMOND, James , BATTEN, Robert
IPC分类号： H04J7/00
CPC分类号： H03M3/50 , H03M3/32 , H03M3/37 , H03M3/39 , H03M3/402 , H03M3/43 , H03M3/458
摘要： Asynchronous electrical circuitry (400, 500, 600, 700, 800, 900) produces a stationary carrier signal (470, 470') and encodes a system input signal (460, 460') amplitude into output signal time-sequence information by establishing at a digitizer (410, 510, 610, 710, 810, 910) an operating point value (416, 516, 616, 716, 816, 916) as an average amplitude of the system input signal. It applies to the digitizer a multicomponent digitizer-input signal (470, 470') corresponding to a sum of a passband signal component and a feedback signal component to produce a pulse-width modulated digitizer output signal (480, 480') representing the system input signal. An asynchronous time delay (t(s)) is introduced to produce the pulse-width modulated system output signal (y(s)). The circuitry performs digital to analog conversion (DAC) to the pulse-width modulated system output signal to produce a DAC output signal (490, 490'). The DAC output signal or its summation with the passband signal component is integrated to produce the feedback signal component. Additional, multiple-order embodiments include sequential feedback paths or carrier-shaping functions.
摘要翻译：异步电路（400,500,600,700,800,900）产生固定载波信号（470,470'），并将系统输入信号（460,460'）振幅编码成输出信号时间序列信息，通过在数字转换器（410,510,610,710,810,910），作为系统输入信号的平均幅度的操作点值（416,516,616,716,816,916）。数字转换器适用于对应于通带信号分量和反馈信号分量之和的多分量数字转换器输入信号（470,470'），以产生表示系统的脉宽调制数字转换器输出信号（480,480'）输入信号。引入异步时间延迟（t（s））以产生脉宽调制系统输出信号（y（s））。电路对脉冲宽度调制的系统输出信号执行数模转换（DAC）以产生DAC输出信号（490,490'）。 DAC输出信号或其与通带信号分量的求和被积分以产生反馈信号分量。另外，多阶实施例包括顺序反馈路径或载波整形功能。

6. 发明申请

WO2015112513A1 METHOD AND APPARATUS FOR EXCESS LOOP DELAY COMPENSATION IN DELTA-SIGMA MODULATOR 审中-公开
标题翻译：在DELTA-SIGMA调制器中进行循环延迟补偿的方法和装置
公开(公告)号：WO2015112513A1
公开(公告)日：2015-07-30
申请号：PCT/US2015/012098
申请日：2015-01-20
申请人： MEDIATEK SINGAPORE PTE. LTD. , LO, Chi-Lun , HO, Stacy
发明人： LO, Chi-Lun , HO, Stacy
IPC分类号： H03M3/00
CPC分类号： H03M3/422 , H03M3/37 , H03M3/424 , H03M3/50
摘要： A delta-sigma modulator includes a signal subtraction circuit, a loop filter, a quantizer, a digital-to-analog converter (DAC), and a control circuit. The signal subtraction circuit subtracts an analog feedback signal from an analog input signal to generate a difference signal. The loop filter performs a filtering operation upon the difference signal to generate a filtered signal. The quantizer quantizes the filtered signal into a digital output signal, wherein at least one inherent circuit characteristic of the quantizer are adjusted in response to a digital code input. The DAC generates the analog feedback signal according to the digital output signal. The control circuit generates the digital code input to the quantizer for setting an excess loop delay (ELD) compensation.
摘要翻译： Δ-Σ调制器包括信号减法电路，环路滤波器，量化器，数模转换器（DAC）和控制电路。信号减法电路从模拟输入信号中减去模拟反馈信号，生成差分信号。环路滤波器对差分信号执行滤波操作以产生滤波信号。量化器将经滤波的信号量化为数字输出信号，其中响应于数字代码输入调整量化器的至少一个固有电路特性。 DAC根据数字输出信号产生模拟反馈信号。控制电路产生输入到量化器的数字代码，用于设定多余的循环延迟（ELD）补偿。

7. 发明申请

WO0118972A3 CIRCUIT ARRANGEMENT FOR GENERATING IN-PHASE INPUT SIGNALS FOR A 1-BIT DIGITAL-ANALOG CONVERTER 审中-公开
标题翻译：电路，用于生成相位相同的输入信号，1位数字模拟转换器
公开(公告)号：WO0118972A3
公开(公告)日：2001-10-11
申请号：PCT/DE0003111
申请日：2000-09-07
申请人： SIEMENS AG , KLING HELMUT
发明人： KLING HELMUT
IPC分类号： H03M3/02
CPC分类号： H03M3/37 , H03M3/502
摘要： The invention relates to a circuit arrangement for generating in-phase input signals for a 1-bit digital-analog converter. The 1-bit digital-analog converter has at least one pair of differential inputs and corresponding outputs, switch units, pulse-shaping units and decoupling units to decouple said outputs, switch units and pulse-shaping units. According to the invention, a transparent D-type flip-flop, comprising corresponding differential inputs and outputs for generating in-phase input signals for the 1-bit digital-analog converter is provided upstream of the differential inputs.
摘要翻译：本发明涉及一种电路装置，用于对1位数字 - 模拟转换器产生的同相输入信号。的1位数字 - 模拟转换器在这种情况下具有至少一对的差分输入和相应的输出，开关单元，脉冲整形单元和切换单元的输出，和脉冲形状单元解耦Entkoppelungseinheiten。根据本发明的上游差分输入透明D触发器与相应的差分输入和输出，用于产生同相输入到1位数字 - 模拟转换器被设置。

8. 发明申请

WO99040680A1 METHOD AND APPARATUS FOR COMPENSATING FOR DELAYS IN MODULATOR LOOPS 审中-公开
标题翻译：用于补偿调制器机架中延迟的方法和装置
公开(公告)号：WO99040680A1
公开(公告)日：1999-08-12
申请号：PCT/US1999/002458
申请日：1999-02-05
IPC分类号： H03K7/08 , H03C1/06 , H03F3/217 , H04B1/04 , H03K7/00 , H01Q11/12 , H03F1/02 , H04B1/10
CPC分类号： H03F3/217 , H03C1/06 , H03K7/08 , H03M3/37 , H03M3/432
摘要： A modulator loop (700) designed to operate in a frequency range of interest is described. The loop (704) includes a loop output terminal and a switching stage, the output of which is coupled to the loop output terminal. The switching stage (704) has a first delay associated therewith. The output of a modulator stage is coupled to the input of the switching stage. A first feedback path is coupled between the loop output terminal and the feedback input of the modulator stage. A feedback filter is coupled between the output of the modulator stage and the feedback input of the modulator stage which compensates for the first delay. The feedback filter (708) is operable to transmit frequencies outside the frequency range of interest and attenuate frequencies in the frequency range of interest.
摘要翻译：描述了被设计为在感兴趣的频率范围内操作的调制器环路（700）。环路（704）包括环路输出端子和开关级，其输出端耦合到环路输出端子。切换级（704）具有与其相关联的第一延迟。调制器级的输出耦合到开关级的输入端。第一反馈路径耦合在环路输出端子和调制器级的反馈输入端之间。反馈滤波器耦合在调制器级的输出和补偿第一延迟的调制器级的反馈输入之间。反馈滤波器（708）可操作以在感兴趣的频率范围之外传输频率并衰减感兴趣的频率范围内的频率。

9. 发明申请

WO2018063568A1 DELTA SIGMA ANALOG-TO-DIGITAL CONVERTER, RADIO FRONT-END, RADIO RECEIVER, MOBILE TERMINAL AND BASE STATION 审中-公开
标题翻译： DELTA SIGMA模拟 - 数字转换器，无线电前端，无线电接收器，移动终端和基站
公开(公告)号：WO2018063568A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/047500
申请日：2017-08-18
申请人： INTEL IP CORPORATION
发明人： KOSTACK, Robert , NAEINI, Ashkan
IPC分类号： H03M3/00
CPC分类号： H03M3/402 , H03F3/195 , H03F3/3022 , H03F3/45 , H03F3/45381 , H03F3/45475 , H03F3/45645 , H03F2200/294 , H03F2200/411 , H03F2203/45418 , H03F2203/45628 , H03F2203/45632 , H03F2203/45686 , H03F2203/45701 , H03F2203/45702 , H03M3/37 , H03M3/454
摘要： Examples provide a delta sigma analog-to-digital converter, a radio front-end, a radio receiver, a mobile terminal and a base station. The delta sigma analog-to-digital converter (100) is suitable for a differential radio frequency current signal. The delta sigma analog to digital converter includes an integrator (110) with a differential input for a differential current signal, and a differential output for a differential voltage signal. The delta sigma analog to digital converter further includes a quantizer (120) with a differential input for the differential voltage signal and a differential output for a digitalized signal. The delta sigma analog to digital converter further includes two or more digital-to-analog converters (130), each with a differential input for the digitalized signal and a differential output for a differential feedback current signal, resulting in two or more separate differential feedback current signals. The differential current signal is based on the two or more separate differential feedback current signals and the differential radio frequency current signal.
摘要翻译：示例提供了Δ-Σ模数转换器，无线电前端，无线电接收器，移动终端和基站。 Δ-Σ模数转换器（100）适用于差分射频电流信号。 Δ-Σ模数转换器包括具有用于差分电流信号的差分输入和用于差分电压信号的差分输出的积分器（110）。 Δ-Σ模数转换器还包括量化器（120），其具有用于差分电压信号的差分输入和用于数字化信号的差分输出。 Δ-Σ模数转换器还包括两个或更多数字 - 模拟转换器（130），每个转换器具有用于数字化信号的差分输入和用于差分反馈电流信号的差分输出，从而产生两个或更多个单独的差分反馈电流信号。差分电流信号基于两个或更多个单独的差分反馈电流信号和差分射频电流信号。

10. 发明申请

WO2016088317A1 デルタシグマ変調器と変調方法および送信装置と送信方法审中-公开
标题翻译： DELTA-SIGMA调制器和调制方法，传输设备和传输方法
公开(公告)号：WO2016088317A1
公开(公告)日：2016-06-09
申请号：PCT/JP2015/005754
申请日：2015-11-18
申请人：日本電気株式会社
发明人：谷尾　真明 , 堀　真一
IPC分类号： H04L27/36 , H03F1/06 , H03F3/217 , H03F3/24 , H03M3/02
CPC分类号： H03M7/304 , G06F7/602 , H03F3/2171 , H03F3/24 , H03F3/245 , H03L7/0816 , H03L7/1976 , H03M3/02 , H03M3/37 , H03M3/502 , H03M7/3011 , H03M7/3015 , H04B14/062 , H04L27/36
摘要：本発明は、増幅器におけるゼロカレントスイッチング特性を保つデルタシグマ変調を一定クロックで実現することで、電力効率が高くかつ設計コストが低い送信装置を提供することを目的とする。本発明のデルタシグマ変調器は、位相信号からパルス位相信号を生成するパルス位相信号生成部と、振幅信号を一定クロックでデルタシグマ変調したパルス振幅信号を生成するデルタシグマ変調部と、前記位相信号に基づいて制御信号を出力する位相振り分け部と、前記制御信号に基づいて前記パルス振幅信号を遅延する遅延切替部と、前記遅延された前記パルス振幅信号と前記パルス位相信号とを掛け合わせたパルス列を出力する混合部と、を有する。
摘要翻译：本发明的目的是提供一种高功率效率和低设计成本的传输设备，其通过以恒定时钟实现在放大器中保持零电流开关特性的Δ-Σ调制。该Δ-Σ调制器包括：脉冲相位信号产生单元，用于从相位信号产生脉冲相位信号; Δ-Σ调制单元，用于产生通过用恒定时钟调制幅度信号的Δ-sigma获得的脉冲幅度信号; 相位分配单元，用于基于相位信号输出控制信号; 延迟切换单元，用于根据控制信号延迟脉冲幅度信号; 以及混合单元，用于输出通过将延迟的脉冲幅度信号和脉冲相位信号相乘而获得的脉冲串。

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