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1. 发明申请

WO2008121525A2 VARIABLE RATE ANALOG-TO-DIGITAL CONVERTER 审中-公开
标题翻译：可变速率模拟数字转换器
公开(公告)号：WO2008121525A2
公开(公告)日：2008-10-09
申请号：PCT/US2008/056723
申请日：2008-03-12
申请人： OLYMPUS COMMUNICATION TECHNOLOGY OF AMERICA, INC. , SHORT, Robert, Townsend , HEIDARI-BATENI, Ghobad , LISENBEE, Layne
发明人： SHORT, Robert, Townsend , HEIDARI-BATENI, Ghobad , LISENBEE, Layne
IPC分类号： H04M3/22
CPC分类号： H03M1/002 , H03M1/12 , H03M1/124 , H03M1/126
摘要： According to various embodiments of the invention a variable rate analog-to-digital converter can be used in conjunction with an anti-aliasing filter to allow the use of lower sampling rates, and accordingly, generally lower power consumption. For example, a lower sampling rate can be used when it is determined that no undesirable signals are present and a higher sampling period can be used when an undesirable signal is present. Determining the presence of an undesired signal can be based on signal-to-noise ratio, over- sampling, bit error rate, using a detector, etc. An undesirable signal can be any signal that is close in frequency to a signal of interest or signals farther away in frequency that has a relatively high amplitude. Sampling rate can be varied in a binary fashion, stepwise, continuously, etc.
摘要翻译：根据本发明的各种实施例，可变速率模数转换器可以与抗混叠滤波器一起使用，以允许使用较低的采样率，并因此通常降低功耗。例如，当确定不存在不期望的信号时可以使用更低的采样率，并且当存在不期望的信号时可以使用较高的采样周期。确定不需要的信号的存在可以基于信噪比，过采样，误码率，使用检测器等。不期望的信号可以是与感兴趣的信号频率接近的任何信号，或者信号在具有相对较高幅度的频率上更远。采样率可以二进制变化，逐步，连续等。

2. 发明申请

WO2014130297A1 SYSTEM AND METHOD FOR RECONSTRUCTION OF SPARSE FREQUENCY SPECTRUM FROM AMBIGUOUS UNDER-SAMPLED TIME DOMAIN DATA 审中-公开
标题翻译：用于重建无效时间域数据的稀疏频谱的系统和方法
公开(公告)号：WO2014130297A1
公开(公告)日：2014-08-28
申请号：PCT/US2014/015848
申请日：2014-02-11
申请人： RAYTHEON COMPANY
发明人： NGUYEN, Tuan, V. , BROVKO, Oleg , KIM, Alison , NGUYEN, Trung, T.
IPC分类号： H03M1/12 , H03M7/30
CPC分类号： H03M1/12 , H03M1/126
摘要： System and method for converting a high bandwidth analog signal to a digital signal including: receiving the high bandwidth analog signal; splitting the high bandwidth analog signal to M parallel channels; delaying the split signal in each channel with N* T delays, respectively; sampling each M delayed signals by M relatively prime sampling rate, wherein the sampling rate for each M delayed signal is smaller than the Nyquist frequency of the high bandwidth analog signal; upsampling each M sampled signal, wherein the upsampling rate for each M sampled signal satisfies the Nyquist frequency of the high bandwidth analog signal; combining the M up sampled signals into a combined signal; and reconstructing the combined signal to generate a digital signal representing the high bandwidth analog signal.
摘要翻译：用于将高带宽模拟信号转换为数字信号的系统和方法，包括：接收高带宽模拟信号; 将高带宽模拟信号分解为M个并行通道; 分别以N * T延迟延迟每个信道中的分离信号; 对每个M个延迟信号进行采样M相对主采样率，其中每个M延迟信号的采样率小于高带宽模拟信号的奈奎斯特频率; 对每个M采样信号进行上采样，其中每个M采样信号的上采样率满足高带宽模拟信号的奈奎斯特频率; 将M个上采样信号组合成组合信号; 以及重构所述组合信号以产生表示所述高带宽模拟信号的数字信号。

3. 发明申请

WO2016027002A1 METHODS AND APPARATUS FOR AN IMPROVED ANALOG TO DIGITAL CONVERTER 审中-公开
标题翻译：改进型数字转换器的方法和设备
公开(公告)号：WO2016027002A1
公开(公告)日：2016-02-25
申请号：PCT/FI2015/050520
申请日：2015-08-11
申请人： NOKIA TECHNOLOGIES OY
发明人： DANNEELS, Hans
IPC分类号： H03M3/02 , H03M3/04
CPC分类号： H03M3/46 , H03M1/00 , H03M1/007 , H03M1/0695 , H03M1/12 , H03M1/126 , H03M1/365 , H03M1/44
摘要： An improved analog to digital converter comprises at least one delta sigma analog to digital converter stage and a succession of pipelined analog to digital converter stages. The pipelined analog to digital converter stages may have a sampling rate determined separately from that of the at least one delta-sigma analog to digital converter stage. The sampling rate of the at least one delta sigma analog to digital converter stage may be an oversampling rate. The sampling rate of the at least one delta-sigma analog to digital converter stages and the pipeline stages may be adjusted by adjusting their sampling frequency and the number of effective pipeline stages may be adjusted -for example, by adjusting a sampling frequency input at each stage. The effective number of pipeline stages may be adjusted, for example, based on the precision needed to process the current signal.
摘要翻译：改进的模数转换器包括至少一个Δ-Σ模数转换器级和一系列流水线模数转换器级。流水线模数转换器级可以具有与至少一个delta-sigma模数转换器级的采样率分开确定的采样率。至少一个Δ-Σ模数转换器级的采样率可以是过采样率。可以通过调整其采样频率来调整至少一个Δ-Σ模数转换器级和流水线级的采样率，并且可以调整有效流水线级的数量，例如通过调整每个阶段。可以例如基于处理电流信号所需的精度来调整有效数量的流水线级。

4. 发明申请

WO2008121525A3 VARIABLE RATE ANALOG-TO-DIGITAL CONVERTER 审中-公开
标题翻译：可变速率模拟数字转换器
公开(公告)号：WO2008121525A3
公开(公告)日：2009-01-08
申请号：PCT/US2008056723
申请日：2008-03-12
申请人： OLYMPUS COMM TECHNOLOGY OF AME , SHORT ROBERT TOWNSEND , HEIDARI-BATENI GHOBAD , LISENBEE LAYNE
发明人： SHORT ROBERT TOWNSEND , HEIDARI-BATENI GHOBAD , LISENBEE LAYNE
IPC分类号： H04M3/22
CPC分类号： H03M1/002 , H03M1/12 , H03M1/124 , H03M1/126
摘要： According to various embodiments of the invention a variable rate analog-to-digital converter can be used in conjunction with an anti-aliasing filter to allow the use of lower sampling rates, and accordingly, generally lower power consumption. For example, a lower sampling rate can be used when it is determined that no undesirable signals are present and a higher sampling period can be used when an undesirable signal is present. Determining the presence of an undesired signal can be based on signal-to-noise ratio, over- sampling, bit error rate, using a detector, etc. An undesirable signal can be any signal that is close in frequency to a signal of interest or signals farther away in frequency that has a relatively high amplitude. Sampling rate can be varied in a binary fashion, stepwise, continuously, etc.
摘要翻译：根据本发明的各种实施例，可变速率模数转换器可以与抗混叠滤波器一起使用，以允许使用较低的采样率，并因此通常降低功耗。例如，当确定不存在不期望的信号时可以使用更低的采样率，并且当存在不期望的信号时可以使用较高的采样周期。确定不需要的信号的存在可以基于信噪比，过采样，误码率，使用检测器等。不期望的信号可以是与感兴趣的信号频率接近的任何信号，或者信号在具有相对较高幅度的频率上更远。采样率可以二进制变化，逐步，连续等。

5. 发明申请

WO2015175706A1 CONFIGURING SIGNAL-PROCESSING SYSTEMS 审中-公开
标题翻译：配置信号处理系统
公开(公告)号：WO2015175706A1
公开(公告)日：2015-11-19
申请号：PCT/US2015/030640
申请日：2015-05-13
申请人： LINEAR TECHNOLOGY CORPORATION
发明人： GANDE, Manideep , STEENSGAARD-MADSEN, Jesper
IPC分类号： G08B21/00
CPC分类号： G11C27/024 , G06F17/5031 , G06F17/5054 , G06F2217/84 , H03M1/12 , H03M1/1255 , H03M1/126 , H03M5/02 , Y02T10/82
摘要： A configurable signal-processing circuit may provide a plurality of selectable signal-processing operations. The configurable signal-processing circuit may have a configuration circuit that provides a configuration code that selects a first signal-processing operation from the plurality of selectable signal-processing operations based on a timing pattern for evaluating an input signal and outputting an output signal.
摘要翻译：可配置信号处理电路可以提供多个可选择的信号处理操作。可配置信号处理电路可以具有配置电路，该配置电路基于用于评估输入信号并输出输出信号的定时模式，提供从多个可选信号处理操作中选择第一信号处理操作的配置码。

6. 发明申请

WO2012151021A2 AN APPARATUS, SYSTEM, AND METHOD FOR VOLTAGE SWING AND DUTY CYCLE ADJUSTMENT 审中-公开
标题翻译：一种用于电压摆幅和占空比调整的装置，系统和方法
公开(公告)号：WO2012151021A2
公开(公告)日：2012-11-08
申请号：PCT/US2012/031970
申请日：2012-04-03
申请人： INTEL CORPORATION , ROYTMAN, Eduard , XU, Jian , SHAH, Rahul R. , MUNSHI, Kambiz R. , BEDARD, Ronald L. , NAGARAJAN, Mahalingam
发明人： ROYTMAN, Eduard , XU, Jian , SHAH, Rahul R. , MUNSHI, Kambiz R. , BEDARD, Ronald L. , NAGARAJAN, Mahalingam
IPC分类号： H03K5/156 , G06F1/10
CPC分类号： H03K5/086 , H03K5/1565 , H03M1/004 , H03M1/126 , H03M1/50
摘要： Described herein are an apparatus, system, and method for compensating voltage swing and duty cycle of a signal on an input-output (I/O) pad of a processor by adjusting the voltage swing and duty cycle of the signal. The apparatus comprises a driver to transmit a signal on an I/O pad, the signal on the I/O pad having a voltage swing and a duty cycle; and an adjustment unit, coupled to the driver, to receive the signal from the I/O pad transmitted by the driver and to generate voltage swing and duty cycle control signals for adjusting the voltage swing and duty cycle of the signal on the I/O pad respectively. Described herein is also an analog-to-digital (A2D) converter for measuring and/or calibrating various signal attributes including current, voltage, and time.
摘要翻译：这里描述了一种用于通过调整信号的电压摆幅和占空比来补偿处理器的输入输出（I / O）焊盘上的信号的电压摆幅和占空比的装置，系统和方法。该装置包括用于在I / O焊盘上传输信号的驱动器，I / O焊盘上的信号具有电压摆幅和占空比; 以及耦合到驱动器的调节单元，用于接收由驱动器发送的I / O焊盘的信号，并产生用于调节I / O上信号的电压摆幅和占空比的电压摆幅和占空比控制信号垫分别。这里描述的也是用于测量和/或校准包括电流，电压和时间的各种信号属性的模数（A2D）转换器。

7. 发明申请

WO2014135686A1 EFFICIENT TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER 审中-公开
标题翻译：高效的时间模拟数字转换器
公开(公告)号：WO2014135686A1
公开(公告)日：2014-09-12
申请号：PCT/EP2014/054469
申请日：2014-03-07
申请人： ANACATUM DESIGN AB
发明人： SUNDBLAD, Rolf , HJALMARSON, Emil
IPC分类号： H03M1/12
CPC分类号： H03M1/1255 , H03M1/121 , H03M1/1215 , H03M1/126
摘要： A time-interleaved analog-to-digital converter for conversion of an analog input signal to a digital output signal having a sample rate R is disclosed. The time-interleaved analog-to-digital converter comprises an array of an integer number N of constituent analog-to-digital converters, an integer number N of sample-and-hold units, one or more digital output processing units, and a timing circuit. Each constituent analog-to-digital converter is adapted to operate based on an analog-to-digital converter operation clock to provide a digital signal at the digital output. Each sample-and-hold unit is connected to the input of a respective constituent analog-to-digital converter and is adapted to operate based on a respective one of a number M of timing signals, wherein no timing signal is used to clock two or more of the sample-and-hold units. The digital output processing units are adapted to provide a sample of the digital output of a constituent analog-to-digital converter as a sample of the digital output signal based on the respective one of the M timing signals. The timing circuit is adapted to generate the analog-to-digital converter operation clock signal and the M timing signals each timing signal having a period of M/R, wherein M is less or equal to N.
摘要翻译：公开了一种用于将模拟输入信号转换为具有采样率R的数字输出信号的时间交织的模拟 - 数字转换器。时间交织的模数转换器包括整数N个组成模数转换器，整数N个采样保持单元，一个或多个数字输出处理单元和定时电路。每个组成模数转换器适于基于模拟 - 数字转换器操作时钟进行操作，以在数字输出端提供数字信号。每个采样保持单元连接到相应的组成模数转换器的输入，并且适于基于M个定时信号中的相应一个进行操作，其中不使用定时信号来计时两个或更多的采样和持有单位。数字输出处理单元适于基于M个定时信号中的相应一个，提供组成模数转换器的数字输出的样本作为数字输出信号的采样。定时电路适于产生模数转换器操作时钟信号，并且M个定时信号具有每个具有M / R周期的定时信号，其中M小于或等于N.

8. 发明申请

WO2014036503A1 ASYNCHRONOUS ANALOG-TO-DIGITAL CONVERTER HAVING RATE CONTROL 审中-公开
标题翻译：具有速率控制的异步模数转换器
公开(公告)号：WO2014036503A1
公开(公告)日：2014-03-06
申请号：PCT/US2013/057691
申请日：2013-08-30
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： GOPINATHAN, Venugopal , DASGUPTA, Udayan , THIAGARAJAN, Ganesan
IPC分类号： H03M1/12
CPC分类号： H03M1/12 , H03M1/10 , H03M1/125 , H03M1/126 , H03M1/127 , H03M1/18 , H03M1/181
摘要： An apparatus is provided. A comparison circuit (204) is configured to receive an analog signal (AIN). A reference circuit (205) is coupled to the comparison circuit and is configured to provide a plurality of reference signals to the comparison circuit. A conversion circuit (212) is coupled to the comparison circuit and is configured to detect a change in the output of the comparison circuit. A time-to-digital converter (TDC)(210) is coupled to the comparison circuit. A timer (208) is coupled to the comparison circuit. A rate control circuit (218) is coupled to the conversion circuit. An output circuit (216) is coupled to the rate control circuit and the TDC, where the output circuit is configured to output at least one of a synchronous digital representation of the analog signal and an asynchronous digital representation of the analog signal.
摘要翻译：提供了一种装置。比较电路（204）被配置为接收模拟信号（AIN）。参考电路（205）耦合到比较电路，并且被配置为向比较电路提供多个参考信号。转换电路（212）耦合到比较电路，并被配置为检测比较电路的输出的变化。时间数字转换器（TDC）（210）耦合到比较电路。定时器208耦合到比较电路。速率控制电路（218）耦合到转换电路。输出电路（216）耦合到速率控制电路和TDC，其中输出电路被配置为输出模拟信号的同步数字表示和模拟信号的异步数字表示中的至少一个。

9. 发明申请

WO2012151021A3 AN APPARATUS, SYSTEM, AND METHOD FOR VOLTAGE SWING AND DUTY CYCLE ADJUSTMENT 审中-公开
标题翻译：一种用于电压摆幅和占空比调整的装置，系统和方法
公开(公告)号：WO2012151021A3
公开(公告)日：2013-04-04
申请号：PCT/US2012031970
申请日：2012-04-03
申请人： INTEL CORP , ROYTMAN EDUARD , XU JIAN , SHAH RAHUL R , MUNSHI KAMBIZ R , BEDARD RONALD L , NAGARAJAN MAHALINGAM
发明人： ROYTMAN EDUARD , XU JIAN , SHAH RAHUL R , MUNSHI KAMBIZ R , BEDARD RONALD L , NAGARAJAN MAHALINGAM
IPC分类号： H03K5/156 , G06F1/10
CPC分类号： H03K5/086 , H03K5/1565 , H03M1/004 , H03M1/126 , H03M1/50
摘要： Described herein are an apparatus, system, and method for compensating voltage swing and duty cycle of a signal on an input-output (I/O) pad of a processor by adjusting the voltage swing and duty cycle of the signal. The apparatus comprises a driver to transmit a signal on an I/O pad, the signal on the I/O pad having a voltage swing and a duty cycle; and an adjustment unit, coupled to the driver, to receive the signal from the I/O pad transmitted by the driver and to generate voltage swing and duty cycle control signals for adjusting the voltage swing and duty cycle of the signal on the I/O pad respectively. Described herein is also an analog-to-digital (A2D) converter for measuring and/or calibrating various signal attributes including current, voltage, and time.
摘要翻译：这里描述了一种用于通过调整信号的电压摆幅和占空比来补偿处理器的输入输出（I / O）焊盘上的信号的电压摆幅和占空比的装置，系统和方法。该装置包括用于在I / O焊盘上传输信号的驱动器，I / O焊盘上的信号具有电压摆幅和占空比; 以及耦合到驱动器的调节单元，用于接收由驱动器发送的I / O焊盘的信号，并产生用于调节I / O上信号的电压摆幅和占空比的电压摆幅和占空比控制信号垫分别。这里描述的也是用于测量和/或校准包括电流，电压和时间的各种信号属性的模数（A2D）转换器。

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