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1. 发明申请

WO2013006188A1 METHODS AND APPARATUS FOR IN-PIXEL FILTERING IN FOCAL PLANE ARRAYS 审中-公开
标题翻译：方法和装置在正片平面阵列中进行像素内滤波
公开(公告)号：WO2013006188A1
公开(公告)日：2013-01-10
申请号：PCT/US2011/050889
申请日：2011-09-08
申请人： SCHULTZ, Kenneth I. , TYRRELL, Brian M. , KELLY, Michael W. , COLONERO, Curtis B. , CANDELL, Lawrence M. , MOONEY, Daniel B.
发明人： SCHULTZ, Kenneth I. , TYRRELL, Brian M. , KELLY, Michael W. , COLONERO, Curtis B. , CANDELL, Lawrence M. , MOONEY, Daniel B.
IPC分类号： H04L9/30
CPC分类号： H03K21/023 , G11C19/00 , H03K23/548 , H03M1/001 , H03M1/004 , H03M1/123 , H03M1/60
摘要： Digital focal plane arrays (DFPAs) with multiple counters per unit cell can be used to convert analog signals to digital data and to filter the digital data. Exemplary DFPAs include two-dimensional arrays of unit cells, where each unit cell is coupled to a corresponding photodetector in a photodetector array. Each unit cell converts photocurrent from its photodetector to a digital pulse train that is coupled to multiple counters in the unit cell. Each counter in each unit cell can be independently controlled to filter the pulse train by counting up or down and/or by transferring data as desired. For example, a unit cell may perform in-phase/quadrature filtering of homodyne- or heterodyne-detected photocurrent with two counters: a first counter toggled between increment and decrement modes with an in-phase signal and a second counter toggled between increment and decrement modes with a quadrature signal.
摘要翻译：每单位单元具有多个计数器的数字焦平面阵列（DFPA）可用于将模拟信号转换为数字数据并对数字数据进行滤波。示例性的DFPA包括单位单元的二维阵列，其中每个单位单元耦合到光电检测器阵列中的对应的光电检测器。每个单元电池将来自其光电检测器的光电流转换成耦合到单元电池中的多个计数器的数字脉冲串。可以独立地控制每个单位单元中的每个计数器，以通过向上或向下计数和/或通过根据需要传送数据来对脉冲序列进行滤波。例如，单元可以使用两个计数器来执行与差分检波和外差检测的光电流的同相/正交滤波：在增量和递减模式之间切换的第一计数器，其中同相信号和在增量和减量之间切换的第二计数器具有正交信号的模式。

2. 发明申请

WO2007088706A1 アナログ/ディジタル変換装置审中-公开
标题翻译：模拟/数字转换器
公开(公告)号：WO2007088706A1
公开(公告)日：2007-08-09
申请号：PCT/JP2007/000042
申请日：2007-01-31
申请人：株式会社東芝 , 楊重山 , 尾崎裕史 , 安井和也 , 伴将史
发明人：楊重山 , 尾崎裕史 , 安井和也 , 伴将史
IPC分类号： H03M1/12 , G06F3/05
CPC分类号： H03M1/004 , H03M1/1225
摘要：　スキャンモードで複数のアナログ信号を連続してディジタル信号に変換する場合に、変換するアナログ信号の順番を設定する変換順序設定レジスタ(12)と、この変換順序設定レジスタ(12)に設定された順番に従って複数のアナログ信号(AI0)～(AIn-1)の中から順次1つのアナログ信号(AI)を選択するマルチプレクサ(1)と、このマルチプレクサ(1)で選択されたアナログ信号(AI)をディジタル信号(DO)に変換するA/D変換器(2)と、複数のリザルトレジスタ(RR0)～(RRn-1)を有し、A/D変換器(2)で変換されたディジタル信号(DO)を変換された順番にその記憶領域に格納する変換結果レジスタ(3)と、それらの複数のリザルトレジスタ(RR0)～(RRn-1)にそれぞれ対応するリザルトレジスタ(BRR0)～(BRRn-1)を有するバックアップレジスタ(21)を設ける。
摘要翻译：在多个模拟信号以扫描模式连续转换为数字信号的情况下，模/数转换器设置有转换顺序设置寄存器（12），用于设置要转换的模拟信号的转换顺序，多路复用器（1），用于从由转换顺序设置寄存器（12）设置的转换顺序中的多个模拟信号（AI0） - （AIn-1）中连续地选择一个模拟信号（AI），A / D转换器）用于将由多路复用器（1）选择的模拟信号（AI）转换成数字信号（D0），多个结果寄存器（PR0） - （PRn-1），用于存储数字信号的转换结果寄存器信号（D0）以A / D转换器（2）转换为其存储区域中的转换顺序，以及具有对应于多个存储器的结果寄存器（BPR0） - （BPRn-1））的备份寄存器（21）结果寄存器（PR0） - （PRn-1）。

3. 发明申请

WO1991009470A1 ANALOG TO DIGITAL CONVERSION WITH NOISE REDUCTION 审中-公开
标题翻译：模拟数字转换与噪声减少
公开(公告)号：WO1991009470A1
公开(公告)日：1991-06-27
申请号：PCT/US1990007503
申请日：1990-12-14
申请人： BOEHRINGER MANNHEIM CORPORATION
发明人： BOEHRINGER MANNHEIM CORPORATION , PARKS, Robert, A.
IPC分类号： H03M01/52
CPC分类号： H03M1/0658 , H03M1/004 , H03M1/52
摘要： An analog-to-digital converter (10) employs a capacitor circuit (12) for integrating a sample of an input signal (20) during a predetermined interval of time and, thereafter, the capacitor (42) is discharged at a predetermined rate until the integration voltage is equal to that of a reference. The discharge time serves as a measure of the amplitude of the input signal. A measurement interval is established which is equal to an integral number of cycles of each of the possible values of frequency of the A.C. excitation. The signal integration interval has a duration less than or approximately equal to the shortest period of the A.C. excitation, this being the period of the highest frequency A.C. excitation. The signal integration is repeated periodically at each third half-cycle of the highest frequency excitation so that the total integration time experienced during positive half cycles is equal to that experienced during negative half cycles of any of the plurality of excitation frequencies. This cancels the effect of noise due to signal polarity.

4. 发明申请

WO2016155825A1 SIGMA-DELTA MODULATOR ARRANGEMENT, METHOD AND CONTROL APPARATUS FOR CALIBRATING A CONTINUOUS-TIME SIGMA-DELTA MODULATOR 审中-公开
标题翻译：用于校准连续时间信号调制器的SIGMA-DELTA调制器布置，方法和控制装置
公开(公告)号：WO2016155825A1
公开(公告)日：2016-10-06
申请号：PCT/EP2015/057246
申请日：2015-04-01
申请人： EPCOS AG
发明人： MARKER-VILLUMSEN, Niels
IPC分类号： H03M3/00 , H03M1/00
CPC分类号： H03M3/382 , H03M1/004 , H03M3/39 , H03M3/422 , H03M3/458
摘要： The sigma-delta modulator arrangement (100)comprises a continuous-time sigma-delta modulator (CT_SDM)with at least one modulator stage, a digital integrator(Int_d)and a given number of switches(Sw1,…,Sw8). The switches (Sw1,…,Sw8) are arranged and configured to convert the continuous-time sigma- delta modulator (CT_SDM)into a first order incremental sigma- delta analog-to-digital converter (INC_ADC) comprising the digital integrator(Int_d). At least a first modulator stage (M_1)of the continuous-time sigma-delta-modulator, which is coupled with an input of the continuous-time sigma-delta modulator (CT_SDM), comprises at least one tuning element for adjusting an input signal and/or a feedback signal which are supplied to the first modulator stage.
摘要翻译： Σ-Δ调制器装置（100）包括具有至少一个调制器级，数字积分器（Int_d）和给定数量的开关（Sw1，...，Sw8）的连续时间Σ-Δ调制器（CT_SDM）。开关（Sw1，...，Sw8）被布置和配置成将连续时间Σ-Δ调制器（CT_SDM）转换成包括数字积分器（Int_d）的一阶增量Σ-Δ模数转换器（INC_ADC）。与连续时间Σ-Δ调制器（CT_SDM）的输入耦合的连续时间Σ-Δ调制器的至少第一调制器级（M_1）包括至少一个调谐元件，用于调整输入信号和/或提供给第一调制器级的反馈信号。

5. 发明申请

WO2011106052A1 DECISION FEEDBACK EQUALIZER 审中-公开
标题翻译：决策反馈均衡器
公开(公告)号：WO2011106052A1
公开(公告)日：2011-09-01
申请号：PCT/US2010/058088
申请日：2010-11-24
申请人： RAMBUS INC. , LEIBOWITZ, Brian , KIM, Jaeha
发明人： LEIBOWITZ, Brian , KIM, Jaeha
IPC分类号： H04L27/01 , H03K7/02
CPC分类号： H04L25/03057 , H03M1/004 , H03M1/123 , H03M1/1245 , H03M1/362 , H04L25/03146 , H04L25/03885 , H04L2025/03363 , H04L2025/03369
摘要： A decision- feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.
摘要翻译：在相同符号时间内，判决反馈均衡器（DFE）对M个参考采样模拟输入信号以产生M个推测采样。在DFE中选择逻辑然后解码先前为先前符号时间分辨的N个比特，以选择M个推测样本之一作为当前分辨比特。然后将当前解析的位存储为最近以前解析的位，以准备下一个符号时间。选择逻辑可以是可编程的，以适应过程，环境和系统变化。

6. 发明申请

WO2005055428A8 READ-ONLY SERIAL INTERFACE WITH VERSATILE MODE PROGRAMMING 审中-公开
标题翻译：具有独立模式编程的只读串行接口
公开(公告)号：WO2005055428A8
公开(公告)日：2005-08-25
申请号：PCT/US2004037402
申请日：2004-11-10
申请人： ANALOG DEVICES INC , BYRNE MICHAEL , O'BYRNE NICOLA , PRICE COLIN , HUMMERSTON DEREK
发明人： BYRNE MICHAEL , O'BYRNE NICOLA , PRICE COLIN , HUMMERSTON DEREK
IPC分类号： G06F1/32 , H03M1/00 , H03M1/12 , H03M1/42 , H03M1/46 , H03M1/70 , H04M1/73
CPC分类号： H03M1/004 , G06F1/3209 , H03M1/002 , H03M1/46 , H03M1/462 , H03M1/70 , H04W52/0287 , Y02D70/00 , Y02D70/12 , Y02D70/122
摘要： A method for placing a device in a selected mode of operation. The method comprises the steps of initializing a device select signal (307) into a first logic state, asserting the device select signal in a second logic state, and returning the device select signal to the first logic state within a first user-controlled time window. A device is also described that includes means for detecting logic state transitions at a device select input and a clock input (306), and means for changing operating mode of the device in response to a predetermined number of logic state transitions at the clock input, occurring between logic state transitions at the device select input. The selected operating mode may be a reduced power consumption mode, for example, or another operating mode of the device, such as a daisy-chain mode of operation, or a mode that accommodates programming of analog input range.
摘要翻译：一种用于将设备放置在所选择的操作模式中的方法。该方法包括以下步骤：将设备选择信号（307）初始化为第一逻辑状态，在第二逻辑状态中断言设备选择信号，并在第一用户控制的时间窗口内将设备选择信号返回到第一逻辑状态。还描述了一种装置，其包括用于检测设备选择输入和时钟输入（306）处的逻辑状态转换的装置，以及用于响应于时钟输入处的预定数量的逻辑状态转换来改变设备的工作模式的装置，发生在设备选择输入的逻辑状态转换之间。所选择的操作模式可以是诸如菊花链操作模式的降低的功耗模式，例如或设备的另一操作模式，或者适应模拟输入范围的编程的模式。

7. 发明申请

WO2016089384A1 UNIVERSAL INPUT AND OUTPUT INTERFACE 审中-公开
标题翻译：通用输入和输出接口
公开(公告)号：WO2016089384A1
公开(公告)日：2016-06-09
申请号：PCT/US2014/068302
申请日：2014-12-03
申请人： GENERAL ELECTRIC COMPANY
发明人： LOVELL, Alan Carroll , HENDERSON, Bruce
IPC分类号： F42D1/045 , H04L27/00
CPC分类号： H03M1/004 , G01K7/021 , G01K7/16 , H03C3/00 , H04L27/10 , H04Q9/00
摘要： Provided is programmable circuit for interfacing with a field device. The circuit includes only one analog-to-digital converter (ADC) configured to receive from the field device one from the group including a current signal and a voltage signal The received one signal has frequency shift keying tones (FSK) superimposed thereon, the ADC being configured to extract information from the received one signal and the FSK tones simultaneously. Also included is only one digital-to-analog converter configured to drive an output signal to the field device, the output signal (i) including one from the group including a current signal and a voltage signal and (ii) being summed with an FSK-modulated signal.
摘要翻译：提供了用于与现场设备接口的可编程电路。该电路仅包括一个模拟 - 数字转换器（ADC），其被配置为从现场设备接收包括电流信号和电压信号的组中的一个。所接收的一个信号具有叠加在其上的频移键控音（FSK），ADC 被配置为从所接收的一个信号和FSK音调同时提取信息。还包括仅一个数模转换器，被配置为驱动对现场设备的输出信号，输出信号（i）包括来自包括电流信号和电压信号的组中的一个，以及（ii）与FSK相加调制信号。

8. 发明申请

WO2012151021A2 AN APPARATUS, SYSTEM, AND METHOD FOR VOLTAGE SWING AND DUTY CYCLE ADJUSTMENT 审中-公开
标题翻译：一种用于电压摆幅和占空比调整的装置，系统和方法
公开(公告)号：WO2012151021A2
公开(公告)日：2012-11-08
申请号：PCT/US2012/031970
申请日：2012-04-03
申请人： INTEL CORPORATION , ROYTMAN, Eduard , XU, Jian , SHAH, Rahul R. , MUNSHI, Kambiz R. , BEDARD, Ronald L. , NAGARAJAN, Mahalingam
发明人： ROYTMAN, Eduard , XU, Jian , SHAH, Rahul R. , MUNSHI, Kambiz R. , BEDARD, Ronald L. , NAGARAJAN, Mahalingam
IPC分类号： H03K5/156 , G06F1/10
CPC分类号： H03K5/086 , H03K5/1565 , H03M1/004 , H03M1/126 , H03M1/50
摘要： Described herein are an apparatus, system, and method for compensating voltage swing and duty cycle of a signal on an input-output (I/O) pad of a processor by adjusting the voltage swing and duty cycle of the signal. The apparatus comprises a driver to transmit a signal on an I/O pad, the signal on the I/O pad having a voltage swing and a duty cycle; and an adjustment unit, coupled to the driver, to receive the signal from the I/O pad transmitted by the driver and to generate voltage swing and duty cycle control signals for adjusting the voltage swing and duty cycle of the signal on the I/O pad respectively. Described herein is also an analog-to-digital (A2D) converter for measuring and/or calibrating various signal attributes including current, voltage, and time.
摘要翻译：这里描述了一种用于通过调整信号的电压摆幅和占空比来补偿处理器的输入输出（I / O）焊盘上的信号的电压摆幅和占空比的装置，系统和方法。该装置包括用于在I / O焊盘上传输信号的驱动器，I / O焊盘上的信号具有电压摆幅和占空比; 以及耦合到驱动器的调节单元，用于接收由驱动器发送的I / O焊盘的信号，并产生用于调节I / O上信号的电压摆幅和占空比的电压摆幅和占空比控制信号垫分别。这里描述的也是用于测量和/或校准包括电流，电压和时间的各种信号属性的模数（A2D）转换器。

9. 发明申请

WO2008072134A1 A HIGH EFFICIENCY MODULATING RF AMPLIFIER 审中-公开
标题翻译：高效率调制射频放大器
公开(公告)号：WO2008072134A1
公开(公告)日：2008-06-19
申请号：PCT/IB2007/054928
申请日：2007-12-05
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN ZEIJL, Paulus, T., M. , COLLADOS ASENSIO, Manel
发明人： VAN ZEIJL, Paulus, T., M. , COLLADOS ASENSIO, Manel
IPC分类号： H03F1/02 , H03M1/74
CPC分类号： H03M1/004 , H03F1/0227 , H03M1/745
摘要： A high efficiency modulating RF amplifier (10) for amplitude modulating a signal defined by a phase information signal (1) and an envelope signal (2) comprises a power supply (30) arranged to provide an operating voltage under control of the envelope signal (2). The power supply (30) comprises a plurality of power supply stages (40) and a plurality of supply switches (50) coupled between the plurality of power supply stages (40) and the modulator (20). The power supply (30) is arranged to select one of the power supply stages (40) to provide the operating voltage under control of the envelope signal (2). The high efficiency modulator RF amplifier further comprises a modulator (20) for receiving the phase information signal (1), the envelope signal (2) and the operating voltage. The modulator (20) is arranged to provide an output signal of which an amplitude is modulated under control of the envelope signal (2).
摘要翻译：用于对由相位信息信号（1）和包络信号（2）定义的信号进行幅度调制的高效率调制RF放大器（10）包括电源（30），其布置成在包络信号（ 2）。电源（30）包括多个电源级（40）和耦合在多个电源级（40）和调制器（20）之间的多个电源开关（50）。电源（30）被布置成选择一个电源级（40），以在包络信号（2）的控制下提供工作电压。高效率调制器RF放大器还包括用于接收相位信息信号（1），包络信号（2）和工作电压的调制器（20）。调制器（20）被布置成提供在包络信号（2）的控制下幅度被调制的输出信号。

10. 发明申请

WO2013012462A1 AN INTEGRATED CIRCUIT ENABLING THE COMMUNICATION OF DATA AND A METHOD OF COMMUNICATING DATA IN INTEGRATED CIRCUIT 审中-公开
标题翻译：使用数据通信的集成电路和在一体化电路中通信数据的方法
公开(公告)号：WO2013012462A1
公开(公告)日：2013-01-24
申请号：PCT/US2012/031656
申请日：2012-03-30
申请人： XILINX, INC. , COLLINS, Anthony, J.
发明人： COLLINS, Anthony, J.
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H01L2924/15192 , H01L2924/15311 , H03M1/004
摘要： An integrated circuit enabling the communication of data is described. The integrated circuit comprises an input/output port (604); a plurality of data converter circuits (802); and programmable interconnect circuits (804) coupled between the input/output port and the plurality of data converter circuits, the programmable interconnect circuits enabling a connection of the plurality of data converter circuits to the input/output port of the integrated circuit. A method of enabling the communication of data in an integrated circuit is also described.
摘要翻译：描述了能够进行数据通信的集成电路。集成电路包括输入/输出端口（604）; 多个数据转换器电路（802）; 以及耦合在所述输入/输出端口和所述多个数据转换器电路之间的可编程互连电路（804），所述可编程互连电路使得能够将所述多个数据转换器电路连接到所述集成电路的输入/输出端口。还描述了能够进行集成电路中的数据通信的方法。

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