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1. 发明申请

WO2011106052A1 DECISION FEEDBACK EQUALIZER 审中-公开
标题翻译：决策反馈均衡器
公开(公告)号：WO2011106052A1
公开(公告)日：2011-09-01
申请号：PCT/US2010/058088
申请日：2010-11-24
申请人： RAMBUS INC. , LEIBOWITZ, Brian , KIM, Jaeha
发明人： LEIBOWITZ, Brian , KIM, Jaeha
IPC分类号： H04L27/01 , H03K7/02
CPC分类号： H04L25/03057 , H03M1/004 , H03M1/123 , H03M1/1245 , H03M1/362 , H04L25/03146 , H04L25/03885 , H04L2025/03363 , H04L2025/03369
摘要： A decision- feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.
摘要翻译：在相同符号时间内，判决反馈均衡器（DFE）对M个参考采样模拟输入信号以产生M个推测采样。在DFE中选择逻辑然后解码先前为先前符号时间分辨的N个比特，以选择M个推测样本之一作为当前分辨比特。然后将当前解析的位存储为最近以前解析的位，以准备下一个符号时间。选择逻辑可以是可编程的，以适应过程，环境和系统变化。

2. 发明申请

WO00065772A2 PHY CONTROL MODULE FOR A MULTI-PAIR GIGABIT TRANSCEIVER 审中-公开
标题翻译：多对数字收发器的PHY控制模块
公开(公告)号：WO00065772A2
公开(公告)日：2000-11-02
申请号：PCT/US2000/011123
申请日：2000-04-24
IPC分类号： G01R31/30 , G01R31/317 , G01R31/3185 , H04B3/23 , H04B3/32 , H04L1/00 , H04L1/24 , H04L7/00 , H04L7/02 , H04L7/033 , H04L25/03 , H04L25/06 , H04L25/14 , H04L25/49 , H04L25/497 , H04L12/00
CPC分类号： H04L7/0062 , G01R31/3008 , G01R31/31715 , G01R31/318594 , H04B3/23 , H04B3/32 , H04L1/0054 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/0349 , H04L2025/03503 , H04L2025/03617
摘要： A method for controlling operation of a multi-pair gigabit transceiver. The multi-pair gigabit transceiver comprises a Physical Layer Control module (PHY Control), a Physical Coding Sublayer module (PCS) and a Digital Signal Processing module (DSP). The PHY Control receives user-defined inputs from the Serial Management module and status signals and diagnostics signals from the DSP and the PCS and generates control signals, responsive to the user-defined inputs, the status signals and diagnostics signals, to the DSP and the PCS.
摘要翻译：一种用于控制多对千兆位收发器的操作的方法。多对千兆位收发器包括物理层控制模块（PHY Control），物理编码子层模块（PCS）和数字信号处理模块（DSP）。 PHY控制接收来自串行管理模块的用户定义的输入以及来自DSP和PCS的状态信号和诊断信号，并根据用户定义的输入，状态信号和诊断信号产生控制信号到DSP和 PCS。

3. 发明申请

WO00028691A2 MULTI-PAIR GIGABIT ETHERNET TRANSCEIVER 审中-公开
标题翻译：多对数字万用表以太网收发器
公开(公告)号：WO00028691A2
公开(公告)日：2000-05-18
申请号：PCT/US1999/026493
申请日：1999-11-09
IPC分类号： G01R31/30 , G01R31/317 , G01R31/3185 , H04B3/23 , H04B3/32 , H04L1/00 , H04L1/24 , H04L7/02 , H04L7/033 , H04L25/03 , H04L25/06 , H04L25/14 , H04L25/49 , H04L25/497
CPC分类号： H04L7/0062 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318594 , H04B3/23 , H04B3/32 , H04L1/0054 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages: a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
摘要翻译：公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段：第一阶段补偿由解调器中的发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二阶段补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

4. 发明申请

WO00019655A1 TIMING RECOVERY FOR A HIGH SPEED DIGITAL DATA COMMUNICATION SYSTEM BASED ON ADAPTIVE EQUALIZER IMPULSE RESPONSE CHARACTERISTICS 审中-公开
标题翻译：基于自适应均衡器冲突响应特性的高速数字数据通信系统的时序恢复
公开(公告)号：WO00019655A1
公开(公告)日：2000-04-06
申请号：PCT/US1999/022458
申请日：1999-09-28
IPC分类号： H04L7/02 , H04L25/03 , H04L25/49
CPC分类号： H04L7/0058 , H04L25/03019 , H04L25/4927 , H04L2025/03363 , H04L2025/03477 , H04L2025/0349
摘要： A preferred timing recovery scheme is particularly suitable for a high speed digital data communication system that employs T-spaced equalization in the receiving device, where echo cancellation occurs after equalization. The timing recovery technique is based upon an analysis of the impulse response of the equalizer structure (e.g., a structure having a feed forward equalizer and a decision feedback equalizer). The filter tap coefficients of the equalizer elements are analyzed and the sampling phase is adjusted such that a cost function associated with the performance of the equalizer structure is substantially optimized. The sampling phase of the receiver is adjusted in response to a control signal generated as a result of the timing recovery techniques.
摘要翻译：优选的定时恢复方案特别适用于在接收设备中采用T间隔均衡的高速数字数据通信系统，其中均衡后发生回波消除。定时恢复技术基于均衡器结构的脉冲响应的分析（例如，具有前馈均衡器和判决反馈均衡器的结构）。分析均衡器元件的滤波器抽头系数，并调整采样相位，使得与均衡器结构的性能相关联的成本函数被大大优化。响应于由定时恢复技术产生的控制信号来调整接收机的采样相位。

5. 发明申请

WO2017203535A1 DYNAMIC COEFFICIENT STORAGE EQUALIZER 审中-公开
标题翻译：动态系数存储均衡器
公开(公告)号：WO2017203535A1
公开(公告)日：2017-11-30
申请号：PCT/IN2016/050153
申请日：2016-05-24
申请人： THOTAKA TEKHNOLOGIES INDIA PRIVATE LTD
发明人： SARIPALLI, Lakshmi Mohan , VENKATACHALAM, Balaji
IPC分类号： H04L25/00 , H04L27/00
CPC分类号： H04L25/03019 , H04L25/03057 , H04L2025/03363 , H04L2025/03426 , H04L2025/03636
摘要： The present invention is a multilevel equalizer bearing dual equalizer units for performing equalization operations before and after the combination of multipath signals. The Pre-Combining Equalizer functions on the basis of the Least Mean Square (LMS) Criterion and the Linear Predictive Filtering method by use of the Bit Error Rate (BER) code of the final output, which minimizes the errors caused by multipath delays and Inter-Symbol Interferences (ISI). The post-combining equalizer effectively reduces the errors that are induced as a result of imperfect combining. Such a system can suitably function by the employment of Forward Error Correction (FEC) having lower code rate that can be effective for obtaining higher bandwidth.
摘要翻译：本发明是一种具有双均衡器单元的多级均衡器，用于在多路径信号组合之前和之后执行均衡操作。基于最小均方（LMS）准则和线性预测滤波方法的预组合均衡器功能通过使用最终输出的误码率（BER）码，其最小化由多径延迟和Inter引起的误差 - 符号干扰（ISI）。后合并均衡器有效地减少了由于不完美合并而导致的错误。这样的系统可以通过使用具有较低码率的前向纠错（FEC）来适当地起作用，这可以有效地获得较高的带宽。

6. 发明申请

WO2010149714A2 ELECTRONIC DISPERSION COMPENSATION SYSTEM AND METHOD 审中-公开
标题翻译：电子分散补偿系统及方法
公开(公告)号：WO2010149714A2
公开(公告)日：2010-12-29
申请号：PCT/EP2010058936
申请日：2010-06-23
申请人： UNIV COLLEGE CORK NAT UNIV IE , ZHAO JIAN , MCCARTHY MARY
发明人： ZHAO JIAN , MCCARTHY MARY
IPC分类号： H04B10/69
CPC分类号： H04L27/223 , H04B10/6971 , H04L25/03019 , H04L25/03178 , H04L2025/03363
摘要： The invention provides a system and method, for an optical communication network to compensate impairments in the network, using electronic dispersion compensation, said system comprising optical means comprising two or more optical-to-electrical converters for generating at least two electrical signals, comprising amplitude and instantaneous frequency of a received distorted optical signal, and an electrical circuit adapted to perform a full-field reconstruction of the received distorted optical signal using said electrical signals. The system is characterised by a dispersive transmission line circuit with compensation parameters updated at a selected rate to process said full- field reconstructed signal and compensate for coarse chromatic dispersion; and an adaptive electronic equalization circuit with compensation parameters updated at a rate faster than those in the said dispersive transmission line circuit to provide a fine impairment compensation of said reconstructed signals. The system and method of the invention achieves low-cost long-distance transmission, up to 2000km, while maintaining the fast-adaptive compensation capability and provide a method for transparent long-haul and metro-optical networks.
摘要翻译：本发明提供一种系统和方法，用于光通信网络使用电子色散补偿来补偿网络中的损伤，所述系统包括光学装置，该光学装置包括用于产生至少两个电信号的两个或更多个光电转换器，包括振幅和接收失真的光信号的瞬时频率，以及适于使用所述电信号执行所接收的失真光信号的全场重构的电路。该系统的特征在于具有以选定速率更新的补偿参数的色散传输线电路，以处理所述全场重构信号并补偿粗糙色散; 以及自适应电子均衡电路，其补偿参数以比所述色散传输线电路中更快的速率更新，以提供所述重构信号的精细损伤补偿。本发明的系统和方法实现了高达2000km的低成本长距离传输，同时保持了快速自适应补偿能力，为透明的长途和城域光网络提供了一种方法。

7. 发明申请

WO2003028234A1 SYSTEM AND METHOD FOR EMBEDDING A SUB-CHANNEL IN A BLOCK CODED DATA STREAM 审中-公开
标题翻译：用于嵌入块编码数据流中的子信道的系统和方法
公开(公告)号：WO2003028234A1
公开(公告)日：2003-04-03
申请号：PCT/US2002/026643
申请日：2002-08-19
申请人： STONICK, John, T. , GORECKI, James , SEARLES, Shawn , CHECK, William, S., Jr. , LEFFERTS, Robert, B.
发明人： STONICK, John, T. , GORECKI, James , SEARLES, Shawn , CHECK, William, S., Jr. , LEFFERTS, Robert, B.
IPC分类号： H04B1/38
CPC分类号： H04L1/0057 , H04L25/03038 , H04L25/03343 , H04L25/03885 , H04L2025/03363 , H04L2025/03815
摘要： The present invention relates in general to a method, apparatus, and article of manufacture for providing high-speed digital communications (101, 102) through a communications channel (100). In one aspect, the present invention employs a variable rate back channel, incorporated within an existing communication that does not increase or adversely impact the transmission rate of data on the communication channel.
摘要翻译：本发明一般涉及通过通信信道（100）提供高速数字通信（101,102）的方法，设备和制品。一方面，本发明采用并入现有通信中的可变速率反向信道，其不增加或不利地影响通信信道上的数据传输速率。

8. 发明申请

WO00029860A3 DYNAMIC REGISTER WITH IDDQ TESTING CAPABILITY 审中-公开
标题翻译：具有IDDQ测试能力的动态寄存器
公开(公告)号：WO00029860A3
公开(公告)日：2002-05-30
申请号：PCT/US1999/027057
申请日：1999-11-12
IPC分类号： G01R31/30 , G01R31/317 , G01R31/3185 , H04B3/23 , H04B3/32 , H04L1/00 , H04L1/24 , H04L7/02 , H04L7/033 , H04L25/03 , H04L25/06 , H04L25/14 , H04L25/49 , H04L25/497
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3012 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/32 , H04L1/0054 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： The present invention is a method and a system for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating voltage during a steady state of a clock signal. The circuit includes a transmission gate which has input and output terminals, and operates in response to a clock signal. The node is located proximal to the output terminal of the transmission gate. The method includes the operations of driving the node with an input signal when the transmission gate is open during a first steady state of the clock signal and pulling the node to a fixed voltage when the transmission gate is closed during a second steady state of the clock signal.
摘要翻译：本发明是一种用于控制电路节点处的电压的方法和系统，使得节点在时钟信号的稳定状态期间被防止具有未知的浮动电压。该电路包括具有输入和输出端的传输门，并响应时钟信号而工作。节点位于传输门的输出端附近。该方法包括在时钟信号的第一稳定状态期间传输门打开时驱动节点的操作，并且在时钟的第二稳定状态期间传输门关闭时将节点拉至固定电压信号。

9. 发明申请

WO0065772A3 PHY CONTROL MODULE FOR A MULTI-PAIR GIGABIT TRANSCEIVER 审中-公开
标题翻译：多对数字收发器的PHY控制模块
公开(公告)号：WO0065772A3
公开(公告)日：2002-01-03
申请号：PCT/US0011123
申请日：2000-04-24
申请人： BROADCOM CORP , AGAZZI OSCAR E
发明人： AGAZZI OSCAR E
IPC分类号： G01R31/30 , G01R31/317 , G01R31/3185 , H04B3/23 , H04B3/32 , H04L1/00 , H04L1/24 , H04L7/00 , H04L7/02 , H04L7/033 , H04L25/03 , H04L25/06 , H04L25/14 , H04L25/49 , H04L25/497
CPC分类号： H04L7/0062 , G01R31/3008 , G01R31/31715 , G01R31/318594 , H04B3/23 , H04B3/32 , H04L1/0054 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/0349 , H04L2025/03503 , H04L2025/03617
摘要： A method for controlling operation of a multi-pair gigabit transceiver. The multi-pair gigabit transceiver comprises a Physical Layer Control module (PHY Control), a Physical Coding Sublayer module (PCS) and a Digital Signal Processing module (DSP). The PHY Control receives user-defined inputs from the Serial Management module and status signals and diagnostics signals from the DSP and the PCS and generates control signals, responsive to the user-defined inputs, the status signals and diagnostics signals, to the DSP and the PCS.
摘要翻译：一种用于控制多对千兆位收发器的操作的方法。多对千兆位收发器包括物理层控制模块（PHY Control），物理编码子层模块（PCS）和数字信号处理模块（DSP）。 PHY控制接收来自串行管理模块的用户定义的输入以及来自DSP和PCS的状态信号和诊断信号，并根据用户定义的输入，状态信号和诊断信号产生控制信号到DSP和 PCS。

10. 发明申请

WO00062470A1 UNIVERSAL SYNCHRONOUS NETWORK SYSTEM FOR INTERNET PROCESSOR AND WEB OPERATING ENVIRONMENT 审中-公开
标题翻译：用于互联网处理器和网络操作环境的通用同步网络系统
公开(公告)号：WO00062470A1
公开(公告)日：2000-10-19
申请号：PCT/US2000/010101
申请日：2000-04-14
IPC分类号： H04J3/06 , H04L7/00 , H04L25/03
CPC分类号： H04L25/03057 , H04J3/0638 , H04L7/0008 , H04L2025/03363 , H04L2025/0349 , H04L2025/03509 , H04L2025/03617
摘要： A method for increasing bandwidth of signals between a transmitting and receiving nodes is provided. A time synchronization signal is received. Clock tuning logic (161) synchronizes the transmitting and receiving nodes using the received synchronization signal. Channel measurement logic (164) measures the capacity of the communication channel. Channel calibration logic (163) calibrates the communications channel using the capacity measurements. Precision sampling logic (165) samples the clock signal of the nodes. Phase adjustement is delivered to the nodes when a sampled clock signal exceeds a phase interval.
摘要翻译：提供了一种用于增加发送和接收节点之间的信号带宽的方法。接收时间同步信号。时钟调谐逻辑（161）使用所接收的同步信号同步发送和接收节点。信道测量逻辑（164）测量通信信道的容量。通道校准逻辑（163）使用容量测量校准通信通道。精确采样逻辑（165）对节点的时钟信号进行采样。当采样的时钟信号超过相位间隔时，相位调整被传送到节点。

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