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1. 发明申请

WO1986000768A1 DEVICE FOR TUNING A VCO TO THE CARRIER FREQUENCY OF EACH RADAR PULSE 审中-公开
标题翻译：用于调谐VCO到每个雷达脉冲的载波频率的装置
公开(公告)号：WO1986000768A1
公开(公告)日：1986-01-30
申请号：PCT/IT1985000014
申请日：1985-07-03
申请人： SELENIA, INDUSTRIE ELETTRONICHE ASSOCIATE , MASDEA, Arturo , BARTOLINI, Pietro , COLAVITO, Gianfranco , NERI, Filippo
发明人： SELENIA, INDUSTRIE ELETTRONICHE ASSOCIATE
IPC分类号： H03L07/14
CPC分类号： G01S7/28 , H03L7/087 , H03L7/14
摘要： Electronic device for rapidly tuning a voltage controlled oscillator to the radar carrier frequency of each of the individual radar pulses. A frequency discriminator (1) of the quadricorrelator type is supplied with the incoming pulses and with the output of the VCO (5) to provide the control voltage to the VCO (5) via amplifying stages (2), (4) and a sample-and-hold circuit (3) that maintains the tuned frequency for time durations greater than 100 mu sec. The operating frequency range of the device is between 6GHz - 18 GHz.
摘要翻译：用于将压控振荡器快速调谐到每个雷达脉冲的雷达载波频率的电子设备。四通道相关器类型的鉴频器（1）被提供有输入脉冲和VCO（5）的输出，以通过放大级（2），（4）和样本（5）向VCO（5）提供控制电压保持电路（3），其保持调谐频率大于100μsec的持续时间。器件的工作频率范围在6GHz至18GHz之间。

2. 发明申请

WO1997023049A1 PROCEDURE AND CIRCUIT FOR HOLDING LOCK STATE IN A DIGITAL PLL 审中-公开
标题翻译：用于在数字PLL中保持锁定状态的程序和电路
公开(公告)号：WO1997023049A1
公开(公告)日：1997-06-26
申请号：PCT/EP1996004405
申请日：1996-10-10
申请人： ITALTEL S.P.A.
发明人： ITALTEL S.P.A. , VITI, Maurizio
IPC分类号： H03L07/14
CPC分类号： H03L7/145
摘要： A procedure is described for generation of a local clock signal by means of a digital PLL allowing the PLL to hold the lock even during any microbreaks in the synchronizing signal. The circuit which implements the procedure includes a module counter N (2DIV/N) dividing the local clock frequency in a manner identical to that used for the link. A logic (FF1/2/3; 1,2) presets the beginning of count in phase with the rising fronts of the external synchronism signal (CKRIF) to create a locally synthesized synchronism signal (CKRIF.RIC). A monostable (MONOS) detects the presence of the above mentioned fronts and commands a two-input selector (SEL) to switch to the PLL the external synchronism signal or, in the absence thereof, that synthesized locally. In a variant for PCM line signals the selector is replaced by a gate OR (SOM) and the monostable is missing.
摘要翻译：描述了通过数字PLL产生本地时钟信号的过程，允许PLL即使在同步信号中的任何微爆期间也能保持锁定。实现该过程的电路包括以与用于该链路的方式相同的方式对本地时钟频率进行分割的模块计数器N（2DIV / N）。逻辑（FF1 / 2/3; 1,2）预设与外部同步信号（CKRIF）的上升沿相位的计数开始，以产生本地合成的同步信号（CKRIF.RIC）。单稳态（MONOS）检测上述前端的存在，并命令双输入选择器（SEL）将外部同步信号切换到PLL，或者在不存在的情况下，将本地合成。在PCM线路信号的变体中，选择器被门OR（SOM）取代，单稳态电路丢失。

3. 发明申请

WO1995009485A1 METHOD FOR CONTROLLING A PHASE-LOCKED LOOP, AND A PHASE-LOCKED LOOP 审中-公开
标题翻译：用于控制相位锁定环路的方法和相位锁定环路
公开(公告)号：WO1995009485A1
公开(公告)日：1995-04-06
申请号：PCT/FI1994000432
申请日：1994-09-26
申请人： NOKIA TELECOMMUNICATIONS OY , KIVIJÄRVI, Antti
发明人： NOKIA TELECOMMUNICATIONS OY
IPC分类号： H03L07/14
CPC分类号： H03L7/199 , H03L7/081 , H03L7/14 , H03L7/145
摘要： The invention relates to a method for controlling a phase-locked loop in a locking situation, and to a phase-locked loop. The loop comprises a phase detector (13), a loop filter (14) and a voltage-controlled oscillator (15) connected in succession, a feedback path being established from the output of the oscillator to a second input (12) in the phase detector. In response to a change causing a currently used input signal to become inadequate for locking, the signal connected from the loop filter (14) to the oscillator (15) is frozen to a constant value, and in response to a change causing a currently used signal to become again adequate for locking, the freezing is removed. In the method, in order that the locking would take place directly, without any sudden phase changes, (a) the output signal of the loop filter (14) is additionally maintained substantially at said constant value by means of the feedback loop (25; 45) in response to a change causing the currently used input signal to become inadequate for locking; and (b) the control provided by said feedback loop for the loop filter (14) is frozen substantially at its current value in response to a change causing the signal to become again adequate for locking.
摘要翻译：本发明涉及一种用于在锁定情况下控制锁相环的方法以及锁相环。环路包括相位检测器（13），环路滤波器（14）和压控振荡器（15），反相路径从振荡器的输出到相位的第二输入端（12）被建立探测器。响应于导致当前使用的输入信号变得不适于锁定的变化，从环路滤波器（14）连接到振荡器（15）的信号被冻结到恒定值，并且响应于导致当前使用的信号变得再次足够锁定，冻结被去除。在该方法中，为了直接进行锁定，没有任何突然的相位变化，（a）环路滤波器（14）的输出信号通过反馈回路（25; 25）被额外维持在所述恒定值。 45）响应于导致当前使用的输入信号变得不适于锁定的变化; 并且（b）由环路滤波器（14）的所述反馈回路提供的控制响应于导致信号变得再次适合于锁定的变化被大致冻结在其当前值。

4. 发明申请

WO1989012932A1 PHASE-CONTROL CIRCUIT 审中-公开
标题翻译：相控电路
公开(公告)号：WO1989012932A1
公开(公告)日：1989-12-28
申请号：PCT/EP1989000590
申请日：1989-05-26
申请人： DEUTSCHE THOMSON-BRANDT GMBH , STORZ, Dieter , BAAS, Dieter
发明人： DEUTSCHE THOMSON-BRANDT GMBH
IPC分类号： H03L07/14
CPC分类号： H03L1/00 , G11B19/28 , H03L7/087 , H03L7/10 , Y10S388/911
摘要： The speed of the disc drive of a CD-player is regulated by means of a phase-control circuit, which is set manually during production. In order to avoid tiresome manual setting during production as well as speed fluctuations, resulting in deterioration of the sound reproduction due to aging of the components and to variations in temperature, setting is performed automatically. To this end, the controller (R) of the phase-control circuit is separated from the voltage-controlled oscillator (VCO). The output of the voltage-controlled oscillator (VCO) is connected to the first input of a phase-compensation device (P2), the reference frequency (BF) being directed towards its second input. A microprocessor (MP), the input (E) of which is connected to the output of the phase-compensation device (P2) and the output (A1) of which is connected to the input of the voltage-controlled oscillator (VCO), modifies the tension at its output (A1) until the frequency at the output of the voltage-controlled oscillator (VCO) corresponds with the reference frequency (BF). The microprocessor (MP) retains said tension. The controller (R) is then reconnected to the voltage-controlled oscillator (VCO). The phase-control circuit is now set and operational. Setting of a CD-player can for example be performed every time it is switched on or another CD is being played, or during a pause between two tracks of music. Said phase-control circuit is particularly suited for a CD player.
摘要翻译： CD播放机的磁盘驱动器的速度通过在生产期间手动设置的相位控制电路来调节。为了避免在生产过程中手工设定烦琐以及速度波动，导致由于部件老化以及温度变化引起的声音再现的恶化，自动进行设定。为此，相位控制电路的控制器（R）与压控振荡器（VCO）分离。压控振荡器（VCO）的输出端连接到相位补偿装置（P2）的第一输入端，参考频率（BF）指向其第二输入端。微处理器（MP），其输入（E）连接到相位补偿装置（P2）的输出，其输出（A1）连接到压控振荡器（VCO）的输入端，修改其输出（A1）处的张力，直到压控振荡器（VCO）输出的频率与参考频率（BF）相对应。微处理器（MP）保持所述张力。控制器（R）然后被重新连接到压控振荡器（VCO）。相控电路现在可以设置和运行。 CD播放器的设置例如可以在每次打开或另一个CD播放时，或者在两首音乐轨迹之间的暂停期间执行。所述相位控制电路特别适用于CD播放机。

5. 发明申请

WO1998023036A1 A CARRIER-RECOVERY LOOP WITH STORED INITIALIZATION IN A RADIO RECEIVER 审中-公开
标题翻译：无线接收机存储初始化的载波恢复环路
公开(公告)号：WO1998023036A1
公开(公告)日：1998-05-28
申请号：PCT/US1997021367
申请日：1997-11-21
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , JANESCH, Stephen, T. , SCHNIZLEIN, Paul , BELL, Ed
IPC分类号： H03L07/14
CPC分类号： H04L27/22 , H03L7/093 , H03L7/0991 , H03L7/146 , H04L1/24 , H04L7/0334 , H04L27/2273 , H04L2027/0028 , H04L2027/0046 , H04L2027/0067 , H04L2027/0069
摘要： A carrier-recovery loop for a receiver in a communication system with features that facilitate initialization of the loop. The carrier-recovery loop is a PLL that uses a feedback signal to keep a recovery oscillator phase-locked to the carrier of a received signal. In the present invention, an initializing value of the feedback signal is stored in a memory and provided to a digitally controlled recovery oscillator (DCO). This initializing value brings the recovered signal to an initial frequency that approximates the carrier frequency. When the receivers start to acquire a phase-lock with the carrier, the carrier-recovery loop is in a condition close to the desired phase lock. Preparing the DCO in this manner imparts a significant improvement to the carrier-recovery loop. The response time for the loop to acquire a phase lock depends in part on its initial frequency offset from the carrier. In general, reducing this initial offset reduces the loop's acquisition time. By thus anticipating the frequency of the carrier, this carrier-recovery loop can have an improved acquisition time to reach phase lock. The initialization value of the feedback signal can be generated by recording a sample of the feedback signal when the carrier-recovery loop is phase-locked to a received signal or to an on-board crystal oscillator. The invention also includes a mechanism to correct drifts in the crystal oscillator's frequency.
摘要翻译：具有促进循环初始化的特征的通信系统中的接收机的载波恢复回路。载波恢复环路是使用反馈信号将恢复振荡器锁相到接收信号的载波的PLL。在本发明中，将反馈信号的初始化值存储在存储器中并提供给数字控制的恢复振荡器（DCO）。该初始化值使恢复的信号达到近似载波频率的初始频率。当接收机开始与载波获取锁相时，载波恢复环路处于接近期望相位锁的状态。以这种方式准备DCO对载体恢复循环有显着的改进。环路获取锁相的响应时间部分取决于其与载波的初始频率偏移。一般来说，减少初始偏移可以减少环路的采集时间。通过这样预期载波的频率，该载波恢复回路可以具有改善的采集时间以达到锁相。反馈信号的初始化值可以通过当载波恢复回路被锁相到接收信号时记录反馈信号的样本，或通过记录在板上的晶体振荡器来产生。本发明还包括校正晶体振荡器频率漂移的机制。

6. 发明申请

WO1997020393A1 A METHOD OF GENERATING AN OUTPUT SIGNAL IN RESPONSE TO AN EXTERNAL SIGNAL AND A FIRST REFERENCE SIGNAL, AS WELL AS A DIGITAL PHASE-LOCKED CIRCUIT HAVING A VOLTAGE-CONTROLLED OSCILLATOR 审中-公开
标题翻译：产生对外部信号和第一参考信号的响应的输出信号的方法，以及具有电压控制的振荡器的数字相位锁定电路
公开(公告)号：WO1997020393A1
公开(公告)日：1997-06-05
申请号：PCT/DK1996000481
申请日：1996-11-22
申请人： DSC COMMUNICATIONS A/S , NIELSEN, Anders, Boje
发明人： DSC COMMUNICATIONS A/S
IPC分类号： H03L07/14
CPC分类号： H03L7/143 , H03L7/181 , H04L7/0083 , H04L7/0331
摘要： A digital phase-locked circuit (10) has a voltage controlled oscillator (17) whose output is counted in a counter (13), said counter (13) being latched on the basis of the frequency of an external input signal. If the external frequency drops out, an internally generated frequency latches the counter circuit (13), and an adjustment signal from a compensation circuit adjusts the phase detector. The compensation circuit (12) consists of an 11-bit counter (26) which counts the output signal from the voltage controlled oscillator (17). The contents of the counter (26) are renewed in periods determined by the internal signal. If the external signal drops out, the counter (26) instantaneously locks to the value last locked, and a third counter (22) provides a signal which can be supplied as an input signal to the counter (13), said third counter (22) being adapted so as to apply a signal to a circuit (25) when the counted value in the third counter (22) corresponds to a quantity calculated from the counter (26).
摘要翻译：数字锁相电路（10）具有压控振荡器（17），其输出在计数器（13）中计数，所述计数器（13）根据外部输入信号的频率被锁存。如果外部频率下降，则内部产生的频率锁存计数器电路（13），来自补偿电路的调整信号调整相位检测器。补偿电路（12）由对来自压控振荡器（17）的输出信号进行计数的11位计数器（26）组成。计数器（26）的内容在由内部信号确定的周期内被更新。如果外部信号丢失，则计数器26瞬时锁定到最后被锁定的值，第三计数器22提供可作为输入信号提供给计数器（13），所述第三计数器（22）的信号），以便当第三计数器（22）中的计数值对应于从计数器（26）计算的数量时，向电路（25）施加信号。

7. 发明申请

WO1994021048A1 METHOD OF GENERATING A CLOCK SIGNAL BY MEANS OF A PHASE-LOCKED LOOP AND A PHASE-LOCKED LOOP 审中-公开
标题翻译：通过相位锁定环路和相位锁定环路产生时钟信号的方法
公开(公告)号：WO1994021048A1
公开(公告)日：1994-09-15
申请号：PCT/FI1994000077
申请日：1994-03-03
申请人： NOKIA TELECOMMUNICATIONS OY , LAAKSONEN, Esa
发明人： NOKIA TELECOMMUNICATIONS OY
IPC分类号： H03L07/14
CPC分类号： H03L7/093 , H03L7/146
摘要： The invention relates to a method of generating a clock signal (CLK) by means of a phase-locked loop, and to a phase-locked loop comprising a phase comparator (101), a loop filter (102), and a voltage-controlled oscillator (105). In the method, a synchronizing signal (MCLK) derived from a synchronisation source is applied to a first input in the phase comparator (101), and the clock signal is locked to the synchronizing signal. In order that the clock frequency could be kept unchanged even in failure situations, a control voltage sequence of the oscillator (105) is stored in a memory (111) over a predetermined period of time while the clock signal is locked to the synchronizing signal, and a sequence obtained from the memory is substituted for the control voltage obtained from the phase comparator (101) in response to a change where a currently applied synchronizing signal becomes inadequate for use in timing.
摘要翻译：本发明涉及一种通过锁相环产生时钟信号（CLK）的方法，以及一种锁相环，包括相位比较器（101），环路滤波器（102）和电压控制振荡器（105）。在该方法中，将来自同步源的同步信号（MCLK）施加到相位比较器（101）中的第一输入端，并将时钟信号锁定到同步信号。为了即使在故障情况下时钟频率也可以保持不变，在时钟信号被锁定到同步信号的情况下，振荡器（105）的控制电压序列在预定的时间段内存储在存储器（111）中，并且响应于当前施加的同步信号变得不足以用于定时的改变，从存储器获得的序列代替从相位比较器（101）获得的控制电压。

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