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1. 发明申请

WO1995009485A1 METHOD FOR CONTROLLING A PHASE-LOCKED LOOP, AND A PHASE-LOCKED LOOP 审中-公开
标题翻译：用于控制相位锁定环路的方法和相位锁定环路
公开(公告)号：WO1995009485A1
公开(公告)日：1995-04-06
申请号：PCT/FI1994000432
申请日：1994-09-26
申请人： NOKIA TELECOMMUNICATIONS OY , KIVIJÄRVI, Antti
发明人： NOKIA TELECOMMUNICATIONS OY
IPC分类号： H03L07/14
CPC分类号： H03L7/199 , H03L7/081 , H03L7/14 , H03L7/145
摘要： The invention relates to a method for controlling a phase-locked loop in a locking situation, and to a phase-locked loop. The loop comprises a phase detector (13), a loop filter (14) and a voltage-controlled oscillator (15) connected in succession, a feedback path being established from the output of the oscillator to a second input (12) in the phase detector. In response to a change causing a currently used input signal to become inadequate for locking, the signal connected from the loop filter (14) to the oscillator (15) is frozen to a constant value, and in response to a change causing a currently used signal to become again adequate for locking, the freezing is removed. In the method, in order that the locking would take place directly, without any sudden phase changes, (a) the output signal of the loop filter (14) is additionally maintained substantially at said constant value by means of the feedback loop (25; 45) in response to a change causing the currently used input signal to become inadequate for locking; and (b) the control provided by said feedback loop for the loop filter (14) is frozen substantially at its current value in response to a change causing the signal to become again adequate for locking.
摘要翻译：本发明涉及一种用于在锁定情况下控制锁相环的方法以及锁相环。环路包括相位检测器（13），环路滤波器（14）和压控振荡器（15），反相路径从振荡器的输出到相位的第二输入端（12）被建立探测器。响应于导致当前使用的输入信号变得不适于锁定的变化，从环路滤波器（14）连接到振荡器（15）的信号被冻结到恒定值，并且响应于导致当前使用的信号变得再次足够锁定，冻结被去除。在该方法中，为了直接进行锁定，没有任何突然的相位变化，（a）环路滤波器（14）的输出信号通过反馈回路（25; 25）被额外维持在所述恒定值。 45）响应于导致当前使用的输入信号变得不适于锁定的变化; 并且（b）由环路滤波器（14）的所述反馈回路提供的控制响应于导致信号变得再次适合于锁定的变化被大致冻结在其当前值。

2. 发明申请

WO1997023049A1 PROCEDURE AND CIRCUIT FOR HOLDING LOCK STATE IN A DIGITAL PLL 审中-公开
标题翻译：用于在数字PLL中保持锁定状态的程序和电路
公开(公告)号：WO1997023049A1
公开(公告)日：1997-06-26
申请号：PCT/EP1996004405
申请日：1996-10-10
申请人： ITALTEL S.P.A.
发明人： ITALTEL S.P.A. , VITI, Maurizio
IPC分类号： H03L07/14
CPC分类号： H03L7/145
摘要： A procedure is described for generation of a local clock signal by means of a digital PLL allowing the PLL to hold the lock even during any microbreaks in the synchronizing signal. The circuit which implements the procedure includes a module counter N (2DIV/N) dividing the local clock frequency in a manner identical to that used for the link. A logic (FF1/2/3; 1,2) presets the beginning of count in phase with the rising fronts of the external synchronism signal (CKRIF) to create a locally synthesized synchronism signal (CKRIF.RIC). A monostable (MONOS) detects the presence of the above mentioned fronts and commands a two-input selector (SEL) to switch to the PLL the external synchronism signal or, in the absence thereof, that synthesized locally. In a variant for PCM line signals the selector is replaced by a gate OR (SOM) and the monostable is missing.
摘要翻译：描述了通过数字PLL产生本地时钟信号的过程，允许PLL即使在同步信号中的任何微爆期间也能保持锁定。实现该过程的电路包括以与用于该链路的方式相同的方式对本地时钟频率进行分割的模块计数器N（2DIV / N）。逻辑（FF1 / 2/3; 1,2）预设与外部同步信号（CKRIF）的上升沿相位的计数开始，以产生本地合成的同步信号（CKRIF.RIC）。单稳态（MONOS）检测上述前端的存在，并命令双输入选择器（SEL）将外部同步信号切换到PLL，或者在不存在的情况下，将本地合成。在PCM线路信号的变体中，选择器被门OR（SOM）取代，单稳态电路丢失。

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