专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO1997036375A1 TRANSMIT CLOCK GENERATION SYSTEM AND METHOD 审中-公开
标题翻译：发送时钟生成系统和方法
公开(公告)号：WO1997036375A1
公开(公告)日：1997-10-02
申请号：PCT/US1997004875
申请日：1997-03-25
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , SCHNIZLEIN, Paul
IPC分类号： H03L07/099
CPC分类号： H03L7/0805 , H03L7/089 , H03L7/0992 , H04L7/0331
摘要： The communications system includes a first communications unit (2) and a second communications unit, each capable of communication with the other. The first communications unit has a first internal clock and the second communications unit has a second internal clock. The method includes the steps of receiving a receive signal (4) by the first communications unit (2) from the second communications unit, adjusting the receive signal (4) to obtain an adjusted receive clock signal (60) that tracks the receive data signal (4), accumulating the adjustments made in the adjusting step, applying the adjustments accumulated to vary the first internal clock in order to slave the first internal clock to the second internal clock of the second communications unit so as to obtain an adjusted signal (34) that is the adjusted and slaved first internal clock, and deriving a transmit clock (62) from the adjusted signal. With this method, the transmit clock (62) exhibits substantially less jitter because it is not directly derived from the jittered receive clock signal (60). The invention may in particular be applied to communication between a base set unit and handset unit of a digital cordless telephone.
摘要翻译：通信系统包括第一通信单元（2）和第二通信单元，每个通信单元能够彼此通信。第一通信单元具有第一内部时钟，第二通信单元具有第二内部时钟。该方法包括以下步骤：从第二通信单元接收第一通信单元（2）的接收信号（4），调整接收信号（4）以获得调整的接收时钟信号（60），其跟踪接收数据信号（4），累积在调整步骤中进行的调整，施加累积的调整以改变第一内部时钟，以便将第一内部时钟从第二通信单元的第二内部时钟引起，从而获得调整后的信号（34 ），其是经调整和从动的第一内部时钟，并且根据经调整的信号导出发送时钟（62）。利用这种方法，由于传输时钟（62）不直接从抖动的接收时钟信号（60）导出，所以传输时钟（62）显示出较小的抖动。本发明可以特别地应用于数字无绳电话的基站单元和手机单元之间的通信。

2. 发明申请

WO1997023047A2 DISCRETE PHASE LOCKED LOOP 审中-公开
标题翻译：分离相锁定环路
公开(公告)号：WO1997023047A2
公开(公告)日：1997-06-26
申请号：PCT/US1996019652
申请日：1996-12-13
申请人： TELEFONAKTIEBOLAGET LM ERICSSON , ERICSSON INC.
发明人： TELEFONAKTIEBOLAGET LM ERICSSON , ERICSSON INC. , JANSSON, Johan
IPC分类号： H03L07/099
CPC分类号： H03L7/0993 , H04W56/0035
摘要： A discrete phase locked loop and method for supporting global synchronization of data communications in a mobile communications system is disclosed. In order to provide for air frame synchronization, air frame data clocks and a synchronization signal must be phase locked to a global time reference signal. This is accomplished through a fully discrete phase locked loop in ASIC on software wherein a state machine is clocked by a high frequency, high accuracy, fixed frequency source already available in the radio terminal equipment. The state machine generates the required air frame data clocks and synchronization signals by completing a counter cycle. At regular intervals, this counter can skip, or double step, for one count to adjust the output phase closer to the phase of the reference signal. The interval for which this correction is maintained is settable by an interval counter. This implementation mimics an elliptic low pass filter.
摘要翻译：公开了用于支持移动通信系统中的数据通信的全局同步的离散锁相环和方法。为了提供空中帧同步，空中帧数据时钟和同步信号必须被锁相到全局时间参考信号。这通过软件中的ASIC中的完全离散的锁相环实现，其中状态机由无线电终端设备中已经可用的高频，高精度，固定频率源来计时。状态机通过完成一个反周期来生成所需的空中帧数据时钟和同步信号。定时间隔时，该计数器可以跳过或双步进行一个计数，以调整输出相位更靠近参考信号的相位。保持该校正的间隔可以通过间隔计数器来设定。该实现模拟椭圆低通滤波器。

3. 发明申请

WO1998013939A3 CONTROL OF A VOLTAGE CONTROLLED OSCILLATOR 审中-公开
公开(公告)号：WO1998013939A3
公开(公告)日：1998-04-02
申请号：PCT/FI1997000574
申请日：1997-09-24
申请人： NOKIA TELECOMMUNICATIONS OY , CARPELAN, Paulus
发明人： NOKIA TELECOMMUNICATIONS OY
IPC分类号： H03L07/099

4. 发明申请

WO1994026033A1 NUMERICALLY CONTROLLED OSCILLATOR AND DIGITAL PHASE LOCKED LOOP 审中-公开
标题翻译：数字控制振荡器和数字相位锁定环
公开(公告)号：WO1994026033A1
公开(公告)日：1994-11-10
申请号：PCT/FI1994000167
申请日：1994-04-29
申请人： NOKIA TELECOMMUNICATIONS OY , PELTOLA, Seppo
发明人： NOKIA TELECOMMUNICATIONS OY
IPC分类号： H03L07/099
CPC分类号： H03L7/0991 , H03B28/00
摘要： The invention relates to a numerically controlled oscillator comprising a first oscillator section (41) having a counter (22) acting as a frequency divider, and an external oscillator (21) supplying a clock signal (fext) connected to the counter (22) for generating an output signal (fNCO) with a divided frequency from said clock signal, the counter (22) comprising at least one phase control input (A, B) for connecting phase correction requests to the counter (22) for adjusting the phase of said output signal (fNCO) in a desired direction. In order that the gain factor of the oscillator could be diminished and the oscillator could be connected to a digital filter, a second accumulator-type oscillator section (42) known per se is connected to control the first oscillator section (41), the second oscillator section comprising an adder (31) and a register (32), to which the output of the adder is connected, the adder (31) having a first input for connecting a binary digit (x) to control said second oscillator section (42), and a second input for feeding the output signal of the register back to the adder (31). The invention also relates to a phase-locked loop utilizing a numerically controlled oscillator.
摘要翻译：本发明涉及一种数控振荡器，包括具有作为分频器的计数器（22）的第一振荡器部分（41）和提供连接到计数器（22）的时钟信号（fext）的外部振荡器（21），用于从所述时钟信号产生具有分频的输出信号（fNCO），所述计数器（22）包括用于将相位校正请求连接到所述计数器（22）的至少一个相位控制输入（A，B），用于调整所述输出信号（fNCO）。为了减小振荡器的增益因子并且振荡器可以连接到数字滤波器，本身已知的第二累加器型振荡器部分（42）被连接以控制第一振荡器部分（41），第二振荡器部分振荡器部分包括加法器（31）和寄存器（32），加法器的输出端连接到该加法器（32），加法器（31）具有用于连接二进制数位（x）的第一输入端，用于控制所述第二振荡器部分）和用于将寄存器的输出信号反馈给加法器（31）的第二输入。本发明还涉及利用数控振荡器的锁相环。

5. 发明申请

WO1996003808A2 DIGITAL PHASE LOCKED LOOP 审中-公开
标题翻译：数字相位锁定环
公开(公告)号：WO1996003808A2
公开(公告)日：1996-02-08
申请号：PCT/CA1995000432
申请日：1995-07-20
申请人： MITEL CORPORATION
发明人： MITEL CORPORATION , WIECZORKIEWICZ, Jerzy , SHETTY, Krishna , KENNEY, Terry , VAN DER VALK, Robert, L. , SPIJKER, Menno, T.
IPC分类号： H03L07/099
CPC分类号： H03L7/081
摘要： A digital phase locked loop is for recovering a stable clock signal from at least one input signal subject to jitter is disclosed. The loop comprises a digital input circuit receiving at least one input signal, a digital controlled oscillator for generating an output signal at a desired frequency and a control signal representing the time error in said output signal, a stable local oscillator for providing clock signals to the digital controlled oscillator, and a tapped delay line for receiving the output signal of the digital controlled oscillator. The tapped delay line comprises a plurality of buffers each introducing a delay of less than one clock cycle of the digital controlled oscillator. The tapped delay line produces an output signal from a tap determined by the control signal. A digital phase comparator receives at least one input signal from the input circuit and the output signal from the tapped delay line to generate a digital input signal controlling the digital controlled oscillator.
摘要翻译：数字锁相环用于从至少一个受抖动的输入信号恢复稳定的时钟信号。该环路包括接收至少一个输入信号的数字输入电路，用于产生期望频率的输出信号的数字控制振荡器和表示所述输出信号中的时间误差的控制信号，稳定的本地振荡器，用于向数字控制振荡器和用于接收数字控制振荡器的输出信号的抽头延迟线。抽头延迟线包括多个缓冲器，每个缓冲器引入小于数字控制振荡器的一个时钟周期的延迟。抽头延迟线从由控制信号确定的抽头产生输出信号。数字相位比较器接收来自输入电路的至少一个输入信号和来自抽头延迟线的输出信号，以产生控制数字控制振荡器的数字输入信号。

6. 发明申请

WO1994024767A1 AN OSCILLATOR WITH SWITCHED REACTIVE ELEMENTS 审中-公开
标题翻译：具有开关反应元件的振荡器
公开(公告)号：WO1994024767A1
公开(公告)日：1994-10-27
申请号：PCT/US1994004404
申请日：1994-04-19
申请人： RCA THOMSON LICENSING CORPORATION , SAUER, Donald, Jon , RODDA, William , CAMPBELL, Edward, Richard, III
发明人： RCA THOMSON LICENSING CORPORATION
IPC分类号： H03L07/099
CPC分类号： H03B5/24 , H03B5/20 , H03B2200/0038 , H03B2200/005 , H03B2200/0058 , H03B2201/02 , H03B2201/025 , H03B2201/0266 , H03J2200/10 , H03L7/099 , H03L7/0991 , H03L7/113 , H03L7/14 , H04N5/126 , H04N7/122
摘要： A phase-locked-loop circuit includes an oscillator having switched capacitors that are selectively coupled to a positive feedback path of the oscillator in a coarse frequency error correction mode of operation. When the frequency error is small, the circuit operates in a fine error correction mode without varying the selection of the switched reactive elements.
摘要翻译：锁相环电路包括具有开关电容器的振荡器，其以粗频率误差校正操作模式选择性地耦合到振荡器的正反馈路径。当频率误差小时，电路在精细的纠错模式下工作，而不改变切换的无功元件的选择。

7. 发明申请

WO1998018207A1 MIXED SIGNAL PHASE LOCKED LOOP 审中-公开
标题翻译：混合信号相位锁定环
公开(公告)号：WO1998018207A1
公开(公告)日：1998-04-30
申请号：PCT/US1997018861
申请日：1997-10-23
申请人： QUALITY SEMICONDUCTOR, INC.
发明人： QUALITY SEMICONDUCTOR, INC. , DICKE, Curtis, J. , WOLOSEWICZ, Jack
IPC分类号： H03L07/099
CPC分类号： H03L7/10 , H03L7/0807 , H03L7/0995 , Y10S331/02
摘要： A mixed signal phase locked loop (100), optimized for fast settling and low noise, includes a digital wide range delay line oscillator (200). When first activated, the loop (100) calibrates the digital delay line oscillator (200) to its nominal delay characteristics using a reference delay line (300). After achieving nominal delay, the oscillator (200) is locked to a desired reference frequency or a submultiple thereof. After achieving lock, the loop (100) performs synchronous data recovery by locking to an incoming data stream, instead of the reference frequency.
摘要翻译：对于快速建立和低噪声而优化的混合信号锁相环（100）包括数字宽范围延迟线振荡器（200）。当首次激活时，使用参考延迟线（300），环路（100）将数字延迟线振荡器（200）校准为其标称延迟特性。在实现标称延迟之后，振荡器（200）被锁定到期望的参考频率或其一个或多个。在实现锁定之后，循环（100）通过锁定到输入数据流来执行同步数据恢复，而不是参考频率。

8. 发明申请

WO1997037432A1 PORTABLE RADIO COMPRISING A CONNECTABLE CIRCUIT 审中-公开
标题翻译：包含连接电路的便携式无线电
公开(公告)号：WO1997037432A1
公开(公告)日：1997-10-09
申请号：PCT/IB1997000318
申请日：1997-03-28
申请人： PHILIPS ELECTRONICS N.V. , ROUSSELIN, Samuel
发明人： PHILIPS ELECTRONICS N.V.
IPC分类号： H03L07/099
CPC分类号： H03B5/04 , H03B2201/025 , H03J2200/10 , H03L7/099 , H03L7/10 , H03L7/183
摘要： The electronic device comprises an oscillation circuit (1, 2, 3, 10, 11, C1, C2, C3) included in a phase-locked loop which comprises a phase detector (17) and a variable divider (15) depending on a certain quantity. A check circuit is provided which either or not melts a fuse (25) as a function of the magnitude of the output of said phase detector (17) for each quantity of said divider indicating a bad or good locking respectively, of said loop. Application: Determination of wideband radio receiver/transmitter.
摘要翻译：电子设备包括包括在锁相环中的振荡电路（1,2,3,10,11，C1，C2，C3），该振荡电路包括相位检测器（17）和可变分频器（15），这取决于一定的数量。提供了一种检查电路，其对于每个所述分配器的数量分别指示所述回路的不良或良好的锁定，其根据所述相位检测器（17）的输出的幅度而熔化熔丝（25）。应用：宽带无线电接收机/发射机的确定。

9. 发明申请

WO1996041419A1 DIGITALLY CONTROLLED OSCILLATOR FOR A PHASE-LOCKED LOOP 审中-公开
标题翻译：数字控制振荡器，用于锁相环
公开(公告)号：WO1996041419A1
公开(公告)日：1996-12-19
申请号：PCT/US1996008533
申请日：1996-06-04
申请人： ANALOG DEVICES, INC.
发明人： ANALOG DEVICES, INC. , ADAMS, Robert, W.
IPC分类号： H03L07/099
CPC分类号： H03L7/0994 , G06F1/025
摘要： A digitally controlled oscillator in a digital phase-locked loop provides an additional output signal which indicates the time difference between clock pulses output from the digitally controlled oscillator and clock pulses of an ideal clock signal of the same average frequency. This additional signal is called a residue signal. This residue signal may then be used to extrapolate or interpolate outputs of continuously variable interpolation or decimation filters using the output clock signal of the digital phase-locked loop generated according to the digitally controlled oscillator. Because the residue signal may be used in interpolation or decimation filters, it is also applicable to analog-to-digital converters, digital-to-analog converters and sample rate converters which use such filters. The digital phase-locked loop circuit is simpler than previous circuits because a conventional overflowing accumulator may be used, which is a first order system, rather than a higher order multi-bit noise shaper. Additionally, a simpler interpolation or decimation filter may be used.
摘要翻译：数字锁相环中的数字控制振荡器提供附加的输出信号，其指示从数字控制振荡器输出的时钟脉冲与相同平均频率的理想时钟信号的时钟脉冲之间的时间差。该附加信号称为残留信号。然后可以使用该残留信号来使用根据数字控制的振荡器产生的数字锁相环的输出时钟信号来推断或内插连续可变内插或抽取滤波器的输出。由于残留信号可用于插值或抽取滤波器，因此也适用于使用这种滤波器的模数转换器，数模转换器和采样率转换器。数字锁相环电路比以前的电路简单，因为可以使用作为一阶系统的常规溢出累加器，而不是高阶多位噪声整形器。此外，可以使用更简单的内插或抽取滤波器。

10. 发明申请

WO1998025348A1 METHOD AND APPARATUS FOR GENERATING WAVEFORMS USING ADIABATIC CIRCUITRY 审中-公开
标题翻译：使用ADIAB电路产生波形的方法和装置
公开(公告)号：WO1998025348A1
公开(公告)日：1998-06-11
申请号：PCT/US1997017969
申请日：1997-10-02
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , STAMOULIS, Georgios , YE, Yibin
IPC分类号： H03L07/099
CPC分类号： H03L7/099 , H03B5/1212 , H03B5/1228 , H03B11/10 , H03B2200/0082
摘要： An ordinary LC oscillating circuit (202) generates oscillating waveforms. The waveforms are replenished with replenishing circuitry (219) which generates replenishing signals to the oscillating circuit (202) to maintain the sinusoidal oscillating waveforms in the oscillating circuit (202). The replenishing circuitry (219) includes circuitry which has been optimized to minimize any short circuit current which flows through the transistors of the replenishing circuit. The pull-up and pull-down devices of the replenishing circuit are gradually turned on and gradually turned off so as to minimize the introduction of glitches into the oscillating sinusoidal waveforms. A control circuit (217), such as a phase lock loop circuit, is included to match the frequency and phase of the oscillating waveforms to the external clock reference waveform (REFCLK). Control signals are generated by the phase lock loop circuit to control the pull-up and pull-down devices of the replenishing circuit (219) to adjust the frequency and phase of the oscillating waveforms.
摘要翻译：普通LC振荡电路（202）产生振荡波形。所述波形由补充电路（219）补充，所述补充电路产生补偿信号到振荡电路（202）以将正弦振荡波形保持在振荡电路（202）中。补充电路（219）包括已被优化以最小化流过补充电路的晶体管的任何短路电流的电路。补充电路的上拉和下拉器件逐渐导通并逐渐关闭，以便将脉冲引入振荡正弦波形中最小化。包括诸如锁相环电路的控制电路（217）以将振荡波形的频率和相位与外部时钟参考波形（REFCLK）相匹配。控制信号由锁相环电路产生，以控制补充电路（219）的上拉和下拉器件，以调整振荡波形的频率和相位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式