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1. 发明申请

WO2018208597A1 PREDICTIVE RIPPLE-CANCELLING SIGNAL INTO ERROR AMPLIFIER OF SWITCH MODE POWER SUPPLY 审中-公开
公开(公告)号：WO2018208597A1
公开(公告)日：2018-11-15
申请号：PCT/US2018/031103
申请日：2018-05-04
申请人： LINEAR TECHNOLOGY HOLDING LLC
发明人： ENGELHARDT, Michael, T. , SHTARGOT, Leonard
IPC分类号： H02M1/14 , H02M3/156 , H02M1/00
CPC分类号： H02M1/143 , H02M3/156 , H02M2001/0025 , H02M2003/1566 , H03K5/134 , H03K5/135 , H03K5/14
摘要： A predicted ripple in the feedback voltage of a switching converter is generated, based on the ripple over a certain number of recent switching cycles. The DC portion of the feedback voltage is filtered out. This predicted feedback voltage ripple is then added to a fixed reference voltage to create a compensated reference voltage. The compensated reference voltage is applied to the non-inverting input of an error amplifier, and the feedback voltage (having a DC component and ripple) is applied to the inverting input of the error amplifier. Thus, substantially the same ripple component is applied to both inputs and cancels out. Therefore, the output of the error amplifier is not affected by the ripple in the feedback voltage, and a non-rippling control voltage is generated by the error amplifier. As a result, the gain-bandwidth product of the converter can be increased for faster response to transients.

2. 发明申请

WO2017213833A1 DELAY LINE FOR ONE SHOT PRE-EMPHASIS 审中-公开
标题翻译：延迟线为一个预先强调
公开(公告)号：WO2017213833A1
公开(公告)日：2017-12-14
申请号：PCT/US2017/033853
申请日：2017-05-22
申请人： QUALCOMM INCORPORATED
发明人： PETERSON, LuVerne Ray , BRYAN, Thomas , WEE, Tin Tin
IPC分类号： G06F1/32 , H03K17/16 , H03K19/00 , H03K19/003
CPC分类号： H03K3/012 , G06F1/32 , H03K3/356113 , H03K5/134 , H03K17/161 , H03K19/0005 , H03K19/0008 , H03K19/0013 , H03K19/00361 , H03K2005/00195 , H04L25/03019
摘要： A die-to-die data transmitter is disclosed with a pull-up one-shot circuit and a pull-down one-shot circuit, each forming a delay circuit that determines a variable preemphasis period.
摘要翻译：公开了具有上拉单触发电路和下拉单触发电路的裸片至裸片数据发送器，每个都形成确定可变预加重周期的延迟电路。 / p>

3. 发明申请

WO2016039966A3 AUTOMATIC CALIBRATION CIRCUITS FOR OPERATIONAL CALIBRATION OF CRITICAL-PATH TIME DELAYS IN ADAPTIVE CLOCK DISTRIBUTION SYSTEMS, AND RELATED METHODS AND SYSTEMS 审中-公开
标题翻译：用于自适应时钟配电系统中的临界路径时延的操作校准的自动校准电路及相关的方法和系统
公开(公告)号：WO2016039966A3
公开(公告)日：2016-05-12
申请号：PCT/US2015046512
申请日：2015-08-24
申请人： QUALCOMM INC
发明人： BOWMAN KEITH ALAN , BRIDGES JEFFREY TODD , RAINA SARTHAK , KOLLA YESHWANT NAGARAJ , JEONG JIHOON , ATALLAH FRANCOIS IBRAHIM , FLEDERBACH WILLIAM ROBERT , FISCHER JEFFREY HERBERT
IPC分类号： H03K5/156 , G06F1/10 , H03K5/134
CPC分类号： H03K5/13 , G06F1/10 , H03K5/134 , H03K5/156 , H03K2005/00019
摘要： Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems, are disclosed. The adaptive clock distribution system includes a tunable-length delay circuit to delay distribution of a clock signal provided to a clocked circuit, to prevent timing margin degradation of the clocked circuit after a voltage droop occurs in a power supply supplying power to the clocked circuit. The adaptive clock distribution system also includes a dynamic variation monitor to reduce frequency of the delayed clock signal provided to the clocked circuit in response to the voltage droop in the power supply, so that the clocked circuit is not clocked beyond its performance limits during a voltage droop. An automatic calibration circuit is provided in the adaptive clock distribution system to calibrate the dynamic variation monitor during operation based on operational conditions and environmental conditions of the clocked circuit.
摘要翻译：用于自适应时钟分配系统中的关键路径时间延迟的操作校准的自动校准电路以及相关的方法和系统被公开。自适应时钟分配系统包括可调长度延迟电路，用于延迟提供给时钟电路的时钟信号的分布，以防止在向时钟电路供电的电源中发生电压下降之后时钟电路的时序裕度劣化。自适应时钟分配系统还包括动态变化监视器，以响应于电源中的电压下降而降低提供给时钟电路的延迟时钟信号的频率，使得时钟电路在电压期间不超过其性能极限下垂。在自适应时钟分配系统中提供自动校准电路，以根据时钟电路的操作条件和环境条件来校准操作期间的动态变化监测器。

4. 发明申请

WO2013095649A1 APPARATUS AND SYSTEM FOR GENERATING A SIGNAL WITH PHASE ANGLE CONFIGURATION 审中-公开
标题翻译：用于产生具有相角配置的信号的装置和系统
公开(公告)号：WO2013095649A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067231
申请日：2011-12-23
申请人： INTEL CORPORATION , SCHROM, Gerhard , RAGHURAMAN, Narayanan , PAILLET, Fabrice
发明人： SCHROM, Gerhard , RAGHURAMAN, Narayanan , PAILLET, Fabrice
IPC分类号： H03K5/13 , H03H11/26
CPC分类号： H02M1/14 , G06F1/26 , H02M2003/1586 , H03H7/325 , H03H11/265 , H03K3/0315 , H03K4/06 , H03K5/133 , H03K5/134 , H03K7/08 , H03K2005/00019 , H03K2005/00195 , H03L7/00
摘要： Described herein is an apparatus and system for generating a signal with phase angle configuration. The apparatus comprises an array of switch-resistors, each switch resistor to receive a control signal, wherein the array of switch-resistors to generate an output signal; and a circuit to configure phase angle of the output signal. The apparatus can be used for different package and inductor configurations. The apparatus provides flexibility to mitigate switching noise by adjusting phase angles, and provides the ability to enable and disable switch-resistors on the fly without ripples. The apparatus also saves power consumption by selectively turning off switch-resistors when phases are disabled. The output signal of the apparatus has smooth triangular waveforms for improving the quality of power supply generated using the output signal. Overall, the apparatus exhibits reduced sensitivity to process variations compared to traditional signal generators.
摘要翻译：这里描述了一种用于产生具有相位角配置的信号的装置和系统。该装置包括一组开关电阻器，每个开关电阻器用于接收控制信号，其中开关电阻阵列产生输出信号; 以及配置输出信号的相位角的电路。该装置可用于不同的封装和电感器配置。该设备通过调整相位角度提供了减轻开关噪声的灵活性，并提供了在无飞舞时启用和禁用开关电阻的能力。该装置还通过在禁止相位时选择性地关闭开关电阻来节省功耗。该装置的输出信号具有平滑的三角波形，用于改善使用输出信号产生的电源的质量。总体而言，与传统的信号发生器相比，该装置对工艺变化的灵敏度降低。

5. 发明申请

WO2011075540A2 TECHNIQUES FOR PROVIDING REDUCED DUTY CYCLE DISTORTION 审中-公开
标题翻译：提供减少占空比失真的技术
公开(公告)号：WO2011075540A2
公开(公告)日：2011-06-23
申请号：PCT/US2010/060597
申请日：2010-12-15
申请人： ALTERA CORPORATION , NAGARAJAN, Pradeep , CHONG, Yan , SUNG, Chiakang , HUANG, Joseph
发明人： NAGARAJAN, Pradeep , CHONG, Yan , SUNG, Chiakang , HUANG, Joseph
IPC分类号： H03L7/081 , H03K5/13
CPC分类号： H03L7/0814 , H03K5/134 , H03K5/1565 , H03K2005/00065
摘要： A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits comprises variable and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit. Each of the variable and fixed delay blocks inverts a received signal to generate an inverted signal.
摘要翻译：反馈回路电路包括相位检测器和延迟电路。相位检测器基于延迟的周期性信号生成输出信号。延迟电路耦合在延迟延迟链中，延迟延迟周期性信号。每个延迟电路包括可变延迟块和固定延迟块，其被耦合以形成用于通过延迟电路的输入信号的至少两个延迟路径以生成延迟输出信号。延迟电路中的可变延迟块的延迟根据相位检测器的输出信号而变化。每个延迟电路通过延迟路径中不同的延迟路径重新路由输入信号，以在反馈环电路的操作期间基于相位检测器的输出信号生成延迟的输出信号。每个可变延迟块和固定延迟块反转接收到的信号以生成反相信号。

6. 发明申请

WO2016022291A4 DYNAMIC MARGIN TUNING FOR CONTROLLING CUSTOM CIRCUITS AND MEMORIES 审中-公开
标题翻译：用于控制自定义电路和记忆的动态边距调节
公开(公告)号：WO2016022291A4
公开(公告)日：2016-05-12
申请号：PCT/US2015041496
申请日：2015-07-22
申请人： APPLE INC
发明人： BHATIA AJAY KUMAR
IPC分类号： H03K5/13 , G01R19/00 , G01R31/40 , G06F1/24 , G06F1/30 , G11C7/12 , G11C7/22 , H03K5/00 , H03K19/003
CPC分类号： H03K5/134 , G01R19/0084 , G01R31/40 , G06F1/08 , G06F1/24 , G06F1/26 , G06F1/305 , G11C5/14 , G11C7/1066 , G11C7/1093 , G11C7/222 , G11C2207/2281 , G11C2207/229 , H03K5/13 , H03K5/133 , H03K19/00369 , H03K2005/00019 , H03K2005/00039
摘要： Embodiments of a method that may allow for selectively tuning a delay of individual logic paths within a custom circuit or memory are disclosed. Circuitry may be configured to monitor a voltage level of a power supply coupled to the custom circuit or memory. A delay amount of a delay unit within the custom circuit or memory may be changed in response to a determination that the voltage level of the power supply has changed.
摘要翻译：公开了可以允许选择性地调节定制电路或存储器内的各个逻辑路径的延迟的方法的实施例。电路可以被配置为监测耦合到定制电路或存储器的电源的电压电平。响应于确定电源的电压电平已改变，可以改变定制电路或存储器内的延迟单元的延迟量。

7. 发明申请

WO2016039966A2 AUTOMATIC CALIBRATION CIRCUITS FOR OPERATIONAL CALIBRATION OF CRITICAL-PATH TIME DELAYS IN ADAPTIVE CLOCK DISTRIBUTION SYSTEMS, AND RELATED METHODS AND SYSTEMS 审中-公开
标题翻译：用于自适应时钟分配系统中关键时间延迟的自动校准电路及相关方法和系统
公开(公告)号：WO2016039966A2
公开(公告)日：2016-03-17
申请号：PCT/US2015/046512
申请日：2015-08-24
申请人： QUALCOMM INCORPORATED
发明人： BOWMAN, Keith, Alan , BRIDGES, Jeffrey, Todd , RAINA, Sarthak , KOLLA, Yeshwant, Nagaraj , JEONG, Jihoon , ATALLAH, Francois, Ibrahim , FLEDERBACH, William, Robert , FISCHER, Jeffrey, Herbert
IPC分类号： H03K5/156
CPC分类号： H03K5/13 , G06F1/10 , H03K5/134 , H03K5/156 , H03K2005/00019
摘要： Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems, are disclosed. The adaptive clock distribution system includes a tunable-length delay circuit to delay distribution of a clock signal provided to a clocked circuit, to prevent timing margin degradation of the clocked circuit after a voltage droop occurs in a power supply supplying power to the clocked circuit. The adaptive clock distribution system also includes a dynamic variation monitor to reduce frequency of the delayed clock signal provided to the clocked circuit in response to the voltage droop in the power supply, so that the clocked circuit is not clocked beyond its performance limits during a voltage droop. An automatic calibration circuit is provided in the adaptive clock distribution system to calibrate the dynamic variation monitor during operation based on operational conditions and environmental conditions of the clocked circuit.
摘要翻译：公开了用于自适应时钟分配系统中关键路径时间延迟的操作校准的自动校准电路以及相关方法和系统。自适应时钟分配系统包括可延长延迟电路，用于延迟提供给时钟电路的时钟信号的分布，以防止在向时钟控制电路供电的电源中发生电压下降之后时钟电路的时序裕度下降。自适应时钟分配系统还包括动态变化监视器，以响应于电源中的电压下降来减小提供给时钟电路的延迟时钟信号的频率，使得时钟控制的电路在电压期间不超过其性能限制下垂。在自适应时钟分配系统中提供自动校准电路，以在操作期间基于时钟电路的操作条件和环境条件校准动态变化监视器。

8. 发明申请

WO2015160344A1 SIGNAL DELAY CELLS 审中-公开
标题翻译：信号延迟细胞
公开(公告)号：WO2015160344A1
公开(公告)日：2015-10-22
申请号：PCT/US2014/034393
申请日：2014-04-16
申请人： WASHINGTON STATE UNIVERSITY
发明人： HEO, Deukhyoun , AGARWAL, Pawan
IPC分类号： H03L7/081 , H03K5/14
CPC分类号： H03K5/131 , H03K5/134 , H03K2005/00058 , H03K2005/00071 , H03K2005/00195 , H03L7/0992
摘要： In some examples, a circuit is described. The circuit may be included in a digital phase-locked loop (PLL) and may include a first delay cell, a second delay cell, and a delay controller. The first delay cell may include a first inverter circuit that includes first and second transistors and may be configured to receive and to delay a first signal. The delay of the first inverter circuit may be based on first and second voltages respectively provided to the first and second transistors. The second delay cell may include a second inverter circuit that includes third and fourth transistors and may be configured to receive and to delay a second signal. The delay of the second inverter circuit may be based on third and fourth voltages respectively provided to the third and fourth transistors. The delay controller may be configured to provide the first, second, third, and fourth voltages.
摘要翻译：在一些示例中，描述了电路。电路可以包括在数字锁相环（PLL）中，并且可以包括第一延迟单元，第二延迟单元和延迟控制器。第一延迟单元可以包括第一反相器电路，其包括第一和第二晶体管，并且可以被配置为接收和延迟第一信号。第一反相器电路的延迟可以基于分别提供给第一和第二晶体管的第一和第二电压。第二延迟单元可以包括第二反相器电路，其包括第三和第四晶体管，并且可以被配置为接收和延迟第二信号。第二逆变器电路的延迟可以基于分别提供给第三和第四晶体管的第三和第四电压。延迟控制器可以被配置为提供第一，第二，第三和第四电压。

9. 发明申请

WO2016188311A1 DISTRIBUTED MACH-ZEHNDER MODULATOR (MZM) DRIVER DELAY COMPENSATION 审中-公开
标题翻译：分布式MACH-ZEHNDER调制器（MZM）驱动器延迟补偿
公开(公告)号：WO2016188311A1
公开(公告)日：2016-12-01
申请号：PCT/CN2016/081150
申请日：2016-05-05
申请人： HUAWEI TECHNOLOGIES CO., LTD.
发明人： CHEN, Morgan , GU, Yifan , LEE, HungYi , GU, Liang , DANG, Yen , LEI, Gong , CAO, Yuming , SHEN, Xiao Andy , BAI, YuSheng
IPC分类号： H03K5/00
CPC分类号： G02F1/2255 , G02F2001/212 , H03K5/134
摘要： An electronic driver circuit for use with a modulator such as a segmented Mach-Zehnder Modulator (MZM) is provided. The electronic driver circuit includes a first delay buffer implemented as a first complementary metal-oxide-semiconductor (CMOS) inverter and a second delay buffer implemented as a second CMOS inverter. The second CMOS inverter follows the first CMOS inverter and has a second gate width smaller than a first gate width of the first CMOS inverter. The first CMOS inverter is configured to produce a first delayed electrical signal from a received electrical signal and the second CMOS inverter is configured to produce a second delayed electrical signal from the first delayed electrical signal produced by the first CMOS inverter.
摘要翻译：提供了一种与分段马赫 - 曾德调制器（MZM）等调制器一起使用的电子驱动电路。电子驱动电路包括实现为第一互补金属氧化物半导体（CMOS）反相器的第一延迟缓冲器和实现为第二CMOS反相器的第二延迟缓冲器。第二CMOS反相器遵循第一CMOS反相器并且具有小于第一CMOS反相器的第一栅极宽度的第二栅极宽度。第一CMOS反相器被配置为从接收到的电信号产生第一延迟电信号，并且第二CMOS反相器被配置为从由第一CMOS反相器产生的第一延迟电信号产生第二延迟电信号。

10. 发明申请

WO2015143716A1 信息转换器的供电电路、系统及供电方法审中-公开
公开(公告)号：WO2015143716A1
公开(公告)日：2015-10-01
申请号：PCT/CN2014/074301
申请日：2014-03-28
申请人：奇点新源国际技术开发(北京)有限公司
发明人：邵起明
IPC分类号： H03K17/08 , H03K5/13
CPC分类号： H03K17/163 , H03K5/134 , H03K17/284
摘要：一种信息转换器的供电电路、系统及供电方法，涉及供电电路技术领域。所述供电电路包括控制电路通断的开关管和延时启动电路，当供电电路连接的电源上电时，通过延时启动电路控制开关管控制端的电压缓慢上升，从而使开关管从截止状态缓慢开启（导通），进而使开关管输出端的输出电压缓慢上升，即信息转换器的供电电压缓慢上升。避免了开关管即时开启带来的过冲电流，降低了信息转换器的供电电路中的过电流，提高了信息转换器的供电电路安全性。

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