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1. 发明申请

WO2013071276A1 ADAPTIVE OUTPUT SWING DRIVER 审中-公开
标题翻译：自适应输出开关驱动器
公开(公告)号：WO2013071276A1
公开(公告)日：2013-05-16
申请号：PCT/US2012/064734
申请日：2012-11-12
申请人： QUALCOMM INCORPORATED
发明人： LI, Miao , AMELIFARD, Behnam , KONG, Xiaohua , DANG, Nam V.
IPC分类号： H03K19/0185 , H04L25/02
CPC分类号： H03K19/018564 , H03K19/01855 , H04L25/0264
摘要： An adjustable gain line driver (104) receives an input signal (CLK, CLK_B) and a gain control signal (104_C) and outputs a signal with a swing (106_P, 106_M), and the swing is measured (108) to generate a swing measurement signal (SWG). A target swing signal (TARGET_SWG) is generated having a target swing, and the target swing signal is measured to generate a target swing reference signal (110: VH, VL). The swing measurement signal (SWG) is compared (120) to the target swing reference control signal (TARGET_SWG) and a counter (122) generating the gain control signal (CNTL) is incremented until the measurement signal (SWG) meets the target swing reference signal (110: VH, VL). Optionally a reset signal (fig. 2: RESET) resets the counter (122), and the gain control signal (CNTL), at predetermined events.
摘要翻译：可调增益线驱动器（104）接收输入信号（CLK，CLK_B）和增益控制信号（104_C），并输出具有摆动（106_P，106_M）的信号，并且测量摆动（108）以产生摆动测量信号（SWG）。产生具有目标摆动的目标摆动信号（TARGET_SWG），并且测量目标摆动信号以产生目标摆动参考信号（110：VH，VL）。将摆动测量信号（SWG）与目标摆动参考控制信号（TARGET_SWG）进行比较（120），增加产生增益控制信号（CNTL）的计数器（122），直到测量信号（SWG）满足目标摆幅参考信号（110：VH，VL）。可选地，在预定事件下，复位信号（图2：RESET）复位计数器（122）和增益控制信号（CNTL）。

2. 发明申请

WO2008151251A1 TECHNIQUES FOR MULTI-WIRE ENCODING WITH AN EMBEDDED CLOCK 审中-公开
标题翻译：用嵌入式时钟进行多线编码的技术
公开(公告)号：WO2008151251A1
公开(公告)日：2008-12-11
申请号：PCT/US2008/065809
申请日：2008-06-04
申请人： RAMBUS, INC. , WARE, Frederick, A. , KIZER, Jade
发明人： WARE, Frederick, A. , KIZER, Jade
IPC分类号： H03K7/02
CPC分类号： H03M5/16 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03K3/356026 , H03K19/01855 , H03M5/20 , H04L25/0272 , H04L25/4906 , H04L25/4917
摘要： Techniques for multi-wire encoding with an embedded clock are disclosed. In one particular exemplary embodiment, the techniques may be realized as a transmitter component. The transmitter component may comprise at least one encoder module to generate a set of symbols, each symbol being represented by a combination of signal levels on a set of wires. The transmitter component may also comprise at least one signaling module to transmit one or more of the symbols over the set of wires according to a transmit clock. The transmitter component may additionally comprise control logic to restrict transmission of first and second subsets of the set of symbols to respective first and second portions of a clock cycle of the transmit clock, such that a signal differential among at least two of the set of wires exhibits a switching behavior that has a same frequency as the transmit clock.
摘要翻译：公开了一种具有嵌入式时钟的多线编码技术。在一个特定的示例性实施例中，这些技术可以被实现为发射器部件。发射机组件可以包括至少一个编码器模块以产生一组符号，每个符号由一组线路上的信号电平的组合表示。发射机组件还可以包括至少一个信令模块，用于根据传输时钟在一组线路上传输一个或多个符号。发射机组件可以另外包括控制逻辑，以将该组符号的第一和第二子集的发射限制到发射时钟的时钟周期的相应第一和第二部分，使得在该组线中的至少两个之间的信号差分表现出与发送时钟频率相同的开关行为。

3. 发明申请

WO0227701A3 DISPLAY DEVICES WITH DRAVING INTEGRATED CIRCUITS ARRANGED WITHIN THE DISPLAY AREA 审中-公开
标题翻译：显示设备在显示区域内安装了整合电路
公开(公告)号：WO0227701A3
公开(公告)日：2003-01-09
申请号：PCT/US0130784
申请日：2001-09-27
申请人： ALIEN TECHNOLOGY CORP
发明人： STEWART ROGER GREEN , BOLING EDWARD , JACOBSEN JEFFREY J
IPC分类号： G09G3/18 , G09G3/32 , G09G3/34 , G09G3/36 , H01L27/02 , H03K19/0185 , H03K19/094
CPC分类号： G09G3/14 , G09G3/18 , G09G3/2085 , G09G3/3208 , G09G3/34 , G09G3/36 , G09G3/3688 , G09G2300/0804 , G09G2300/0809 , G09G2310/0275 , G09G2330/021 , H01L27/0207 , H01L2224/24227 , H01L2224/95085 , H01L2924/12041 , H01L2924/12044 , H01L2924/15155 , H01L2924/15165 , H03K19/01855 , H03K19/09429 , H01L2924/15153 , H01L2924/00
摘要： Integrated circuits, assemblies with integrated circuits, display devices and electrical circuits. There are various different aspects and embodiments of these apparatuses described herein. According to one aspect, a display device includes a plurality of display drivers which includes a serial shift register, wherein the display drivers are located in the display area of the display device which is viewable. According to another aspect, an integrated circuit, which has a plurality of functionally symmetric interface pads, include an instruction decoder which decodes instructions received through at least one of the pads. In another aspect, an integrated circuit (IC) includes a position detector which detects a position of the IC relative to a receptor substrate and provides a signal which is determined by the position; this IC may be used in an assembly which includes the receptor substrate. In another aspect, an IC includes a position detector which detects a position of the IC relative to a receptor substrate and also includes a configurable pad which is configurable, depending upon the position as one of at least two of the following: an input pad, an output pad, or a no-operation pad. According to another aspect, a layout of an IC has a plurality of funtionally symmetric interface pads wherein two such pads are configurable pads. According to another aspect, an assembly includes a receptor substrate and an IC attached to the substrate, and the IC includes a first logic circuit which provides a first function, a second logic circuit which provides a second function, and a selector which selects between the two functions such that the IC performs only the selected function. Other aspects and methods are described.
摘要翻译：集成电路，集成电路组件，显示设备和电路。这里描述的这些装置有各种不同的方面和实施例。根据一个方面，显示装置包括多个显示驱动器，其包括串行移位寄存器，其中显示驱动器位于可显示的显示装置的显示区域中。根据另一方面，具有多个功能对称接口焊盘的集成电路包括解码通过至少一个焊盘接收的指令的指令解码器。在另一方面，集成电路（IC）包括位置检测器，其检测IC相对于接收器基板的位置，并提供由该位置确定的信号; 该IC可以用于包括受体底物的组件中。另一方面，IC包括位置检测器，该位置检测器检测IC相对于接收器基板的位置，并且还包括可配置的焊盘，其可配置，这取决于作为以下至少两个之一的位置的位置：输入焊盘，输出垫或无操作垫。根据另一方面，IC的布局具有多个功能对称的接口焊盘，其中两个这样的焊盘是可配置焊盘。根据另一方面，一种组件包括接收器基板和附着到基板的IC，并且IC包括提供第一功能的第一逻辑电路，提供第二功能的第二逻辑电路和选择器，两个功能使得IC仅执行所选择的功能。描述其他方面和方法。

4. 发明申请

WO02025819A1 AN APPARATUS FOR ACTIVE HIGH SPEED - LOW POWER ANALOG VOLTAGE DRIVE 审中-公开
标题翻译：用于主动高速 - 低功率模拟电压驱动的装置
公开(公告)号：WO02025819A1
公开(公告)日：2002-03-28
申请号：PCT/US2001/029299
申请日：2001-09-20
IPC分类号： H03F3/30 , H03K19/0185 , H03K19/096
CPC分类号： H03K19/018521 , H03F3/3016 , H03K19/01855
摘要： A high speed low power and active drive circuit that includes an n-channel transistor and a p-channel transistor serially connected between a positive and a negative supply voltage respectively, and having their respective gates driven by a reference voltage. A voltage drive circuit can also include a clock circuit serially connected between the n-channel transistor and the p-channel transistor and the positive and negative supply voltages.
摘要翻译：一种高速低功率和有源驱动电路，其包括分别串联连接在正电源电压和负电源电压之间的n沟道晶体管和p沟道晶体管，并且其各自的栅极由参考电压驱动。电压驱动电路还可以包括串联连接在n沟道晶体管和p沟道晶体管之间的时钟电路以及正和负电源电压。

5. 发明申请

WO2014144291A3 BIAS CIRCUIT FOR A SWITCHED CAPACITOR LEVEL SHIFTER 审中-公开
标题翻译：用于开关电容器转换器的BIAS电路
公开(公告)号：WO2014144291A3
公开(公告)日：2014-10-30
申请号：PCT/US2014028636
申请日：2014-03-14
申请人： ATIEVA INC
发明人： BISKUP RICHARD J
IPC分类号： G05F1/10 , H02J1/02 , H02M1/14 , H02M3/07
CPC分类号： H03K19/01855 , G01R19/0084 , G01R19/16542 , H03K17/162 , H03K19/018521
摘要： A noise resistant switch control circuit is provided. The circuit includes a low pass filter configured to couple to a first terminal of a switch and a first voltage clamp coupled to the low pass filter. The first voltage clamp is configured to couple to a control terminal of the switch and limit a voltage of the control terminal relative to the first terminal to within a first clamping range. The circuit includes a second voltage clamp coupled to an input terminal of the switch control circuit. The second voltage clamp is configured to couple to the control terminal of the switch. The second voltage clamp is further configured to reduce a level of a control voltage coupled to the second voltage clamp. The circuit includes a bias device configured to couple to the control terminal of the switch and to impress a biasing voltage to the control terminal.
摘要翻译：提供了一种抗噪声开关控制电路。该电路包括被配置为耦合到开关的第一端子的低通滤波器以及耦合到低通滤波器的第一电压钳位。第一电压钳被配置为耦合到开关的控制端子并且将控制端子相对于第一端子的电压限制在第一钳位范围内。该电路包括耦合到开关控制电路的输入端子的第二电压钳位。第二电压钳被配置为耦合到开关的控制端子。第二电压钳进一步被配置为降低耦合到第二电压钳的控制电压的电平。该电路包括被配置为耦合到开关的控制端子并将偏置电压施加到控制端子的偏置装置。

6. 发明申请

WO2012003254A2 MULTI-VOLTAGE LEVEL, MULTI-DYNAMIC CIRCUIT STRUCTURE DEVICE 审中-公开
标题翻译：多电平电平，多动态电路结构设备
公开(公告)号：WO2012003254A2
公开(公告)日：2012-01-05
申请号：PCT/US2011/042486
申请日：2011-06-30
申请人： QUALCOMM INCORPORATED , LIN, Jentsung, Ken
发明人： LIN, Jentsung, Ken
IPC分类号： H03K19/0185
CPC分类号： H03K19/018521 , H03K19/01855
摘要： A multi-voltage level, multi-dynamic circuit structure device and method are disclosed. In a particular embodiment, the method includes discharging a first dynamic node at a first discharge circuit of a first dynamic circuit structure in response to receiving an asserted discharge signal. The first dynamic circuit structure includes the first dynamic node at a first voltage level and a first keeper circuit that is disabled when the asserted discharge signal is received. The asserted discharge signal has a second voltage level that is different from the first voltage level. A second keeper circuit of a second dynamic circuit structure is enabled responsive to discharging the first dynamic node to maintain a second dynamic node of the second dynamic circuit structure at the first voltage level.
摘要翻译：公开了一种多电压电平，多动态电路结构装置和方法。在特定实施例中，该方法包括响应于接收到断言的放电信号而在第一动态电路结构的第一放电电路处放电第一动态节点。第一动态电路结构包括处于第一电压电平的第一动态节点和当接收到断言的放电信号时禁用的第一保持电路。所确定的放电信号具有不同于第一电压电平的第二电压电平。第二动态电路结构的第二保持器电路能够响应于对第一动态节点的放电而保持第二动态电路结构的第二动态节点处于第一电压电平。

7. 发明申请

WO2011097628A1 VOLTAGE LEVEL SHIFTER WITH DYNAMIC CIRCUIT STRUCTURE HAVING DISCHARGE DELAY TRACKING 审中-公开
标题翻译：具有放电延迟跟踪的动态电路结构的电压水平振荡器
公开(公告)号：WO2011097628A1
公开(公告)日：2011-08-11
申请号：PCT/US2011/024056
申请日：2011-02-08
申请人： QUALCOMM Incorporated , LIN, Jentsung , BASSETT, Paul Douglas
发明人： LIN, Jentsung , BASSETT, Paul Douglas
IPC分类号： H03K19/0185 , H03K19/096 , H03K19/017
CPC分类号： H03K19/018521 , H03K19/01728 , H03K19/01855 , H03K19/0963
摘要： An apparatus is disclosed. In a particular embodiment, the apparatus includes a a dynamic circuit structure that includes a dynamic node coupling a precharge circuit, a discharge circuit, and a gated keeper circuit. The gated keeper circuit is enabled by a signal from a discharge delay tracking circuit.
摘要翻译：公开了一种装置。在具体实施例中，该装置包括动态电路结构，其包括耦合预充电电路的动态节点，放电电路和门控保持器电路。门控保护器电路由来自放电延迟跟踪电路的信号使能。

8. 发明申请

WO2008027666A2 LEVEL SHIFTING CIRCUIT 审中-公开
标题翻译：水平移位电路
公开(公告)号：WO2008027666A2
公开(公告)日：2008-03-06
申请号：PCT/US2007/073826
申请日：2007-07-19
申请人： FREESCALE SEMICONDUCTOR INC. , BAJKOWSKI, Maciej , HOEKSTRA, George P. , GHASSEMI, Hamed
发明人： BAJKOWSKI, Maciej , HOEKSTRA, George P. , GHASSEMI, Hamed
IPC分类号： H03L5/00
CPC分类号： H03K19/01855 , H03K3/356121
摘要： A level shifting circuit (105) having a signal input that operates in a first voltage domain (LV DD ) and a signal output that operates in a second voltage domain (HV DD ). In some embodiments, the level shifting circuit includes a clocked level shifter. In some embodiments, the level shifting circuit includes a level shifting latch (208) that latches a translated output signal. In one example, the level shifting latch includes a latch portion and a stack of transistors (211, 213, 215, 217) with a transistor having a control electrode coupled to a clock input.
摘要翻译：电平移位电路（105）具有在第一电压域（LVAT DD）中操作的信号输入端和在第二电压域（HV DDD）中工作的信号输出端，）。在一些实施例中，电平移位电路包括时钟电平移位器。在一些实施例中，电平移位电路包括锁存转换的输出信号的电平移位锁存器（208）。在一个示例中，电平移位锁存器包括具有耦合到时钟输入的控制电极的晶体管的锁存部分和堆叠晶体管（211,213,215,217）。

9. 发明申请

WO2014144291A2 BIAS CIRCUIT FOR A SWITCHED CAPACITOR LEVEL SHIFTER 审中-公开
标题翻译：用于开关电容器电平变换器的偏置电路
公开(公告)号：WO2014144291A2
公开(公告)日：2014-09-18
申请号：PCT/US2014/028636
申请日：2014-03-14
申请人： ATIEVA, INC.
发明人： BISKUP, Richard, J.
IPC分类号： G05F1/10 , H02M3/07 , H02J1/02 , H02M1/14
CPC分类号： H03K19/01855 , G01R19/0084 , G01R19/16542 , H03K17/162 , H03K19/018521
摘要： A noise resistant switch control circuit is provided. The circuit includes a low pass filter configured to couple to a first terminal of a switch and a first voltage clamp coupled to the low pass filter. The first voltage clamp is configured to couple to a control terminal of the switch and limit a voltage of the control terminal relative to the first terminal to within a first clamping range. The circuit includes a second voltage clamp coupled to an input terminal of the switch control circuit. The second voltage clamp is configured to couple to the control terminal of the switch. The second voltage clamp is further configured to reduce a level of a control voltage coupled to the second voltage clamp. The circuit includes a bias device configured to couple to the control terminal of the switch and to impress a biasing voltage to the control terminal.
摘要翻译：提供了一种抗噪声开关控制电路。电路包括配置成耦合到开关的第一端子的低通滤波器和耦合到低通滤波器的第一电压钳位。第一电压钳被配置为耦合到开关的控制端子，并且将控制端子相对于第一端子的电压限制在第一钳位范围内。电路包括耦合到开关控制电路的输入端的第二电压钳位。第二电压钳被配置为耦合到开关的控制端。第二电压钳还被配置为降低耦合到第二电压钳的控制电压的电平。电路包括被配置为耦合到开关的控制端子并且向控制端子施加偏置电压的偏置装置。

10. 发明申请

WO2009047340A1 ASYNCHRONOUS CLOCK GATE WITH GLITCH PROTECTION 审中-公开
标题翻译：异步时钟门与保护
公开(公告)号：WO2009047340A1
公开(公告)日：2009-04-16
申请号：PCT/EP2008/063652
申请日：2008-10-10
申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH , KUHN, Ruediger
发明人： KUHN, Ruediger
IPC分类号： H03K19/00
CPC分类号： H03K19/00361 , H03K19/00315 , H03K19/01855 , H03K19/09429
摘要： Atristate buffer circuit includes a tristate buffer switchableinto a high impedance state in response to configuration signal (CS1), a delay stage (DEL) delays the an input signal (BUF-in) to the tristate buffer (TBUF) and a gating stage (GS) having inputs for the input signal (BUF-in), a delayed input signal (BUF-in-DEL) and an asynchronous tristate control signal (3st) and an output supplying the configuration signal (CS1) to the tristate buffer (TBUF). The gating stage (GS) sets the configuration signal (CS1) to the high impedance mode only whenthe tristate control signal (3st) is set and the input signal (BUF-in) and the delayed input signal (BUF-in-DEL) have logic levels indicating that no signal transition of the input signal propagates within the delay stage (DEL). Depending upon signal polarity, the input signal (BUF-in) and the delayed input signal (BUF-in-DEL) are required to have the same digital state or opposite digital states.
摘要翻译：智能缓冲电路包括响应于配置信号（CS1）可切换到高阻抗状态的三态缓冲器，延迟级（DEL）将输入信号（BUF-in）延迟到三态缓冲器（TBUF）和门控级（GS ）具有用于输入信号（BUF-in），延迟输入信号（BUF-in-DEL）和异步三态控制信号（3st）的输入和向三态缓冲器（TBUF）提供配置信号（CS1）的输出，。仅当三态控制信号（3st）被置位并且输入信号（BUF-in）和延迟输入信号（BUF-in-DEL）具有（3））时，门控级（GS）将配置信号（CS1）设置为高阻抗模式逻辑电平指示输入信号的信号转换不在延迟级（DEL）内传播。根据信号极性，输入信号（BUF-in）和延迟输入信号（BUF-in-DEL）需要具有相同的数字状态或相反的数字状态。

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