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1. 发明申请

WO2009042777A1 INDUCTOR SHARING IN RADIO FREQUENCY COMMUNICATIONS 审中-公开
标题翻译：无线电频率通信中的电感共享
公开(公告)号：WO2009042777A1
公开(公告)日：2009-04-02
申请号：PCT/US2008/077690
申请日：2008-09-25
申请人： NANOAMP SOLUTIONS, INC. (CAYMAN) , MINZHAN, Gao , SHEN, Ann, P. , HWANG, Chien-meen
发明人： MINZHAN, Gao , SHEN, Ann, P. , HWANG, Chien-meen
IPC分类号： H04B1/16 , H04B1/18
CPC分类号： H03F3/45183 , H03F1/0277 , H03F3/211 , H03F3/68 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/451 , H03F2200/492 , H03F2203/45244 , H03F2203/45332 , H03F2203/45386 , H03F2203/45396 , H03F2203/45536 , H03F2203/45638 , H03F2203/45728 , H03F2203/7206 , H03F2203/7209 , H03F2203/7221
摘要： Two or more low noise amplifiers are configured to amplify received radio frequency input signals and one or more shared load or source degeneration inductors are configured to be used for each of the two or more low noise amplifiers. Further, the one or more shared inductors can be configured to be used for processing two or more signal bands in a multi-band communication system.
摘要翻译：两个或多个低噪声放大器被配置为放大接收的射频输入信号，并且一个或多个共享负载或源极退化电感被配置为用于两个或更多个低噪声放大器中的每一个。此外，一个或多个共享电感器可以被配置为用于处理多频带通信系统中的两个或更多个信号频带。

2. 发明申请

WO2009042280A1 RADIO FREQUENCY FILTERING 审中-公开
标题翻译：无线电频率滤波
公开(公告)号：WO2009042280A1
公开(公告)日：2009-04-02
申请号：PCT/US2008/070467
申请日：2008-07-18
申请人： NANOAMP SOLUTIONS, INC. (CAYMAN) , HWANG, Chien-Meen , SHEN, Ann, P.
发明人： HWANG, Chien-Meen , SHEN, Ann, P.
IPC分类号： H01P1/20
CPC分类号： H04B1/30
摘要： Radio frequency filtering includes receiving a signal and detecting a change in the direct current (DC) offset of the signal or a change in a component that affects the DC offset of the signal. The filtering also includes setting a cut-off frequency of a high-pass filter to a first frequency value in response to the detected change and filtering the signal using the high-pass filter with the cutoff frequency set to the first frequency value. The filtering further includes adjusting the cutoff frequency of the high-pass filter from the first frequency value to a second frequency value while filtering the signal using the high-pass filter where the second frequency value is less than the first frequency value.
摘要翻译：射频滤波包括接收信号并检测信号的直流（DC）偏移的变化或影响信号的直流偏移的分量的变化。滤波还包括响应于检测到的变化将高通滤波器的截止频率设置为第一频率值，并且使用具有设置为第一频率值的截止频率的高通滤波器对信号进行滤波。滤波还包括将高通滤波器的截止频率从第一频率值调整到第二频率值，同时使用第二频率值小于第一频率值的高通滤波器对信号进行滤波。

3. 发明申请

WO2009042884A1 RADIO FREQUENCY RECEIVER ARCHITECTURE 审中-公开
标题翻译：无线电频率接收机架构
公开(公告)号：WO2009042884A1
公开(公告)日：2009-04-02
申请号：PCT/US2008/077892
申请日：2008-09-26
申请人： NANOAMP SOLUTIONS, INC. (CAYMAN) , SCHUUR, Axel , SHEN, Ann, P.
发明人： SCHUUR, Axel , SHEN, Ann, P.
IPC分类号： H04B1/16 , H04B1/18
CPC分类号： H04B1/006
摘要： A receiver includes a common-gate low noise amplifier (LNA) configured to receive an RF input signal and produce an amplified RF signal. A down-converting passive mixer is configured to mix the amplified received RF input signal with a local oscillator signal generated by a local oscillator to generate a down-converted amplified signal. An amplifier is configured to amplify the down-converted signal and has an input impedances in on the order of ohms. Only a single LNA may be required to receive RF inputs in all frequency bands of a multi-band communication standard.
摘要翻译：接收机包括配置成接收RF输入信号并产生放大的RF信号的共栅低噪声放大器（LNA）。下变频无源混频器被配置为将放大的接收RF输入信号与由本地振荡器产生的本地振荡器信号混合以产生下变频放大信号。放大器被配置为放大下变频信号并具有欧姆量级的输入阻抗。在多频段通信标准的所有频段，只需要一个LNA来接收RF输入。

4. 发明申请

WO2009042666A1 LOAD INDUCTOR SHARING 审中-公开
标题翻译：负载电感共享
公开(公告)号：WO2009042666A1
公开(公告)日：2009-04-02
申请号：PCT/US2008/077493
申请日：2008-09-24
申请人： NANOAMP SOLUTIONS, INC. (CAYMAN) , SHEN, Ann, P. , BURNHAM, James , TABATABAEI, Ali , SHEN, David, H.
发明人： SHEN, Ann, P. , BURNHAM, James , TABATABAEI, Ali , SHEN, David, H.
IPC分类号： H04B1/18 , H03F3/189
CPC分类号： H03F3/45183 , H03F3/193 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/451 , H03F2200/492 , H03F2203/45386 , H03F2203/45396 , H03F2203/45638 , H03F2203/7209
摘要： Sharing one or more load inductors comprises receiving a first input signal at a first terminal of a first amplifier and amplifying the first input signal using the first amplifier The first amplifier is coupled to one or more load inductors at a second terminal of the first amplifier and is coupled to one or more dedicated source inductors at a third terminal of the first amplifier Also, a second input signal is received at a first terminal of a second amplifier amplifying the second input signal using the second amplifier The second amplifier is coupled to the one or more load inductors at a second terminal of the second amplifier and is coupled to one or more dedicated source inductors at a third terminal of the second amplifier
摘要翻译：共享一个或多个负载电感器包括在第一放大器的第一端处接收第一输入信号并使用第一放大器放大第一输入信号。第一放大器耦合到第一放大器的第二端处的一个或多个负载电感器，以及耦合到第一放大器的第三端处的一个或多个专用源电感器。另外，第二输入信号在第二放大器的第一端处被接收，该第二放大器使用第二放大器放大第二输入信号。第二放大器耦合到一个或更多的负载电感器，并且在第二放大器的第三端处耦合到一个或多个专用源电感器

5. 发明申请

WO2009042253A1 PHASE-LOCKED LOOP START-UP TECHNIQUES 审中-公开
标题翻译：相位锁定启动技术
公开(公告)号：WO2009042253A1
公开(公告)日：2009-04-02
申请号：PCT/US2008/062048
申请日：2008-04-30
申请人： NANOAMP SOLUTIONS, INC. (Cayman) , SHEN, David, H. , SHEN, Ann, P. , SCHUUR, Axel
发明人： SHEN, David, H. , SHEN, Ann, P. , SCHUUR, Axel
IPC分类号： H03L7/08
CPC分类号： H03L7/183 , H03L7/10
摘要： Implementations feature systems and techniques for phase-locked loops (PLLs). In some aspects, implementations feature a system that has a PLL circuit including an oscillator and programmable reference frequency divider circuit or a programmable feedback frequency divider circuit. The PLL includes a control circuit to reduce a time required for a PLL settling time by programming a division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit to target the oscillator to operate outside of a system operating frequency range of the oscillator during start-up of PLL operations. The control circuit can program another division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit after stabilization of the variable oscillator.
摘要翻译：实现功能用于锁相环（PLL）的系统和技术。在一些方面，实现特征在于具有包括振荡器和可编程参考分频器电路或可编程反馈分频器电路的PLL电路的系统。 PLL包括控制电路，以通过将分频值编程到可编程参考分频器电路和/或可编程反馈分频器电路中来减少PLL建立时间所需的时间，以使振荡器在系统工作频率范围之外操作在PLL操作启动期间振荡器。在可变振荡器稳定之后，控制电路可以将另一个分频值编程到可编程参考分频器电路和/或可编程反馈分频器电路中。

6. 发明申请

WO2008156480A1 DIGITAL TUNING OF CRYSTAL OSCILLATORS 审中-公开
标题翻译：水晶振荡器的数字调谐
公开(公告)号：WO2008156480A1
公开(公告)日：2008-12-24
申请号：PCT/US2007/071493
申请日：2007-06-18
申请人： SHEN, David, H. , SHEN, Ann, P.
发明人： SHEN, David, H. , SHEN, Ann, P.
IPC分类号： H03B5/36 , H03J3/00 , H03J5/02
CPC分类号： H03B5/366 , H03B2200/005 , H03B2201/0208 , H03J2200/10
摘要： Embodiments feature techniques and systems for digitally tuning a crystal oscillator circuit. In one aspect, embodiments feature a method for tuning a digitally tuned crystal oscillator circuit. The method involves receiving a multi-bit input signal into a digital modulator, modulating the multi-bit input signal with the digital modulator by oversampling or by noiseshaping and oversampling to produce a digitally-modulated output signal having a lower number of bits than the multi-bit input signal. The method also involves coupling a tuning capacitor with the crystal oscillator circuit, and coupling the digitally-modulated output signal from the digital modulator to the crystal oscillator circuit and the tuning capacitor. In some embodiments, the digital modulator can be a delta-sigma modulator, a noiseshaping modulator, a delta modulator, a pulse width modulator, a differential modulator, or a continuous-slope delta modulator.
摘要翻译：实施例用于数字调谐晶体振荡器电路的技术和系统。在一个方面，实施例特征在于一种用于调谐数字调谐的晶体振荡器电路的方法。该方法包括将多位输入信号接收到数字调制器中，通过过采样或通过噪声整形和过采样来调制具有数字调制器的多位输入信号，以产生具有比多数位更低位数的数字调制输出信号位输入信号。该方法还涉及将调谐电容器与晶体振荡器电路耦合，并将数字调制输出信号从数字调制器耦合到晶体振荡器电路和调谐电容器。在一些实施例中，数字调制器可以是Δ-Σ调制器，噪声调制器，Δ调制器，脉冲宽度调制器，差分调制器或连续斜率增量调制器。

7. 发明申请

WO2010151270A1 EVEN-ORDER HARMONICS CALIBRATION 审中-公开
标题翻译：偶数谐波校准
公开(公告)号：WO2010151270A1
公开(公告)日：2010-12-29
申请号：PCT/US2009/049268
申请日：2009-06-30
申请人： NANOAMP MOBILE, INC. , XING, Nianwei , SHEN, David, H. , SCHUUR, Axel , SHEN, Ann, P.
发明人： XING, Nianwei , SHEN, David, H. , SCHUUR, Axel , SHEN, Ann, P.
IPC分类号： H03F1/32 , H03F3/45
CPC分类号： H03F3/45183 , H03F1/3211 , H03F2203/45342
摘要： Circuits and methods for a differential circuit involve having one of more pairs of differential transistors with back-gate terminals, where each of the back-gate terminals is biased by a tunable back-gate voltage to compensate for circuit mismatches in the differential circuit and reduce or eliminate even-order harmonics in the output signal. A compensation circuit can be configured to receive data relating to the differential output signal of the differential circuit, and to supply one or more back-gate voltages to the back-gate terminals of the differential transistors to adjust threshold voltages of the differential transistors and suppress even-order harmonics in the differential output signal of the differential circuit.
摘要翻译：用于差分电路的电路和方法涉及具有多对具有背栅极端子的差分晶体管中的一个，其中每个背栅极端子被可调谐的栅极电压偏置以补偿差分电路中的电路不匹配并且减小或消除输出信号中的偶次谐波。补偿电路可以被配置为接收与差分电路的差分输出信号相关的数据，并且向差分晶体管的背栅极端子提供一个或多个反向栅极电压，以调整差分晶体管的阈值电压并抑制差分电路的差分输出信号中的偶次谐波。

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