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1. 发明申请

WO2005041261A2 BiFET INCLUDING A FET HAVING INCREASED LINEARITY AND MANUFACTURABILITY 审中-公开
标题翻译：包括具有增加的线性和可制造性的FET的BiFET
公开(公告)号：WO2005041261A2
公开(公告)日：2005-05-06
申请号：PCT/US2004/032717
申请日：2004-10-04
申请人： SKYWORKS SOLUTIONS, INC. , ZAMPARDI, Peter, J. , PIERSON, Richard, N.
发明人： ZAMPARDI, Peter, J. , PIERSON, Richard, N.
IPC分类号： H01L
CPC分类号： H01L27/0623 , H01L27/0605 , H01L29/0817 , H01L29/7371 , H01L29/812
摘要： According to one exemplary embodiment, a BiFET situated on a substrate comprises an emitter layer segment situated over the substrate, where the emitter layer segment comprises a semiconductor of a first type. The HBT further comprises a first segment of an etch stop layer, where the first segment of the etch stop layer comprises InGaP. The BiFET further comprises a FET situated over the substrate, where the FET comprises source and drain regions, where a second segment of the etch stop layer is situated under the source and drain regions, and where the second segment of the etch stop layer comprises InGaP. The FET further comprises a semiconductor layer of a second type situated under the second segment of the etch stop layer. The etch stop layer increases linearity of the FET and does not degrade electron current flow in the HBT.
摘要翻译：根据一个示例性实施例，位于衬底上的BiFET包括位于衬底上的发射极层段，其中发射极层段包括第一类型的半导体。 HBT还包括蚀刻停止层的第一段，其中蚀刻停止层的第一段包括InGaP。 BiFET还包括位于衬底上方的FET，其中FET包括源区和漏区，其中蚀刻停止层的第二段位于源极和漏极区之下，并且其中蚀刻停止层的第二段包括InGaP 。 FET还包括位于蚀刻停止层的第二段下方的第二类型的半导体层。蚀刻停止层增加了FET的线性度，并且不会降低HBT中的电子流量。

2. 发明申请

WO2010036673A2 BIPOLAR/DUAL FET STRUCTURE INCLUDING ENHANCEMENT AND DEPLETION MODE FETS WITH ISOLATED CHANNELS 审中-公开
标题翻译：双极/双FET结构，包括具有隔离通道的增强型和分离型FET
公开(公告)号：WO2010036673A2
公开(公告)日：2010-04-01
申请号：PCT/US2009/057960
申请日：2009-09-23
申请人： SKYWORKS SOLUTIONS, INC. , ZAMPARDI, Peter, J. , SUN, Mike
发明人： ZAMPARDI, Peter, J. , SUN, Mike
IPC分类号： H01L29/73 , H01L29/737
CPC分类号： H01L21/8249 , H01L27/0605 , H01L27/0623 , H01L27/0883 , H01L29/7322 , H01L29/78
摘要： According to an exemplary embodiment, a bipolar/dual FET structure includes a bipolar transistor situated over a substrate. The bipolar/dual FET structure further includes an enhancement-mode FET and a depletion-mode FET situated over the substrate. In the bipolar/dual FET structure, the channel of the enhancement-mode FET is situated above the base of the bipolar transistor and the channel of the depletion-mode FET is situated below the base of the bipolar transistor. The channel of the enhancement- mode FET is isolated from the channel of the depletion-mode FET so as to decouple the enhancement-mode FET from the depletion mode FET.
摘要翻译：根据示例性实施例，双极/双重FET结构包括位于衬底上方的双极晶体管。双极/双FET结构还包括位于衬底上方的增强型FET和耗尽型FET。在双极/双FET结构中，增强型FET的沟道位于双极晶体管的基极之上，并且耗尽型FET的沟道位于双极晶体管的基极之下。增强型FET的通道与耗尽型FET的通道隔离，以使增强型FET与耗尽型FET分离。

3. 发明申请

WO2007106428A3 GAAS POWER TRANSISTOR 审中-公开
公开(公告)号：WO2007106428A3
公开(公告)日：2007-09-20
申请号：PCT/US2007/006186
申请日：2007-03-09
申请人： SKYWORKS SOLUTIONS, INC. , ZAMPARDI, Peter, J. , SUN, Mike
发明人： ZAMPARDI, Peter, J. , SUN, Mike
IPC分类号： H01L29/76 , H01L29/66
摘要： A GaAs power transistor unit cell is provided with one of its transistor contacts on its bottom surface, and its other two transistor contacts on its frontside surface. In one arrangement, the GaAs power transistor unit cell has a N+ GaAs substrate that cooperates with an N- GaAs material to form a transistor collector. A collector contact is on a bottom surface of the collector, and a transistor base is provided on the collector. An emitter is arranged on the base. Accordingly, the collector contact is on the bottom of the unit cell, while a base contact and emitter contact are oriented to the frontside of the unit cell. It will be understood that the emitter and collector portions may be exchanged in other constructions. In use, the GaAs transistor unit cells are interconnected to form a GaAs power transistor, with the power transistor having externally available contacts. In one specific construction, a connection pad is provided on a laminate substrate. The GaAs power transistor is adhered and secured to the contact pad. using the bottom contact, enabling a GaAs power amplifier to be easily integrated onto the laminate substrate and connected with other circuitry.

4. 发明申请

WO2011040927A1 CONTINUOUS TUNABLE LC RESONATOR USING A FET AS A VARACTOR 审中-公开
标题翻译：使用FET作为变送器的连续可调谐LC谐振器
公开(公告)号：WO2011040927A1
公开(公告)日：2011-04-07
申请号：PCT/US2009/059305
申请日：2009-10-02
申请人： SKYWORKS SOLUTIONS, INC. , LI, Bin , ZAMPARDI, Peter, J. , METZGER, Andre, G.
发明人： LI, Bin , ZAMPARDI, Peter, J. , METZGER, Andre, G.
IPC分类号： H01L29/93
CPC分类号： H01L29/93 , H01L29/10 , H01L29/107
摘要： A varactor includes a field effect transistor (FET) integrated with at least a portion of a bipolar junction transistor (BJT), in which a back gate of the FET shares an electrical connection with a base of the BJT, and in which a reverse voltage applied to the back gate of the FET creates a continuously variable capacitance in a channel of the FET.
摘要翻译：变容二极管包括与双极结型晶体管（BJT）的至少一部分集成的场效应晶体管（FET），其中FET的背栅与BJT的基极共享电连接，并且其中反向电压施加到FET的背栅极在FET的沟道中产生连续可变的电容。

5. 发明申请

WO2008002451A2 ESD AND ELECTRIC SURGE PROTECTED CIRCUIT AND METHOD OF MAKING SAME 审中-公开
标题翻译： ESD和电涌保护电路及其制造方法
公开(公告)号：WO2008002451A2
公开(公告)日：2008-01-03
申请号：PCT/US2007/014479
申请日：2007-06-21
申请人： SKYWORKS SOLUTIONS, INC. , DAI, Peter, H. , XU, Jane , ZAMPARDI, Peter, J. , RAVI, Ramanathan
发明人： DAI, Peter, H. , XU, Jane , ZAMPARDI, Peter, J. , RAVI, Ramanathan
IPC分类号： H02H9/00
CPC分类号： H02H9/046 , H01L27/0259
摘要： A circuit and process is provided for protecting a device from the detrimental effects of electro-static discharge (ESD). The circuit includes an ESD breakdown device that is used to activate a current drawdown device. When a voltage exceeding the ESD breakdown device's breakdown voltage is applied, a signal is generated that causes the current drawdown device to pump current to ground. In this way, the effects of the ESD charge are substantially reduced. In one example, the ESD breakdown device is a reverse biased diode, and the current drawdown circuit includes a Darlington circuit. When an ESD surge causes the diode to breakdown, a signal is applied to the Darlington circuit, which pumps the ESD current safely to ground.
摘要翻译：提供了一种电路和工艺来保护器件免受静电放电（ESD）的不利影响。该电路包括用于激活电流降压装置的ESD击穿装置。当施加超过ESD击穿器件的击穿电压的电压时，产生使电流降压器件将电流泵送到地的信号。以这种方式，ESD电荷的效果显着降低。在一个示例中，ESD击穿器件是反向偏置二极管，并且电流衰减电路包括达林顿电路。当ESD浪涌导致二极管击穿时，信号将施加到达林顿电路，该电路将ESD电流安全地泵送到地。

6. 发明申请

WO2012061632A2 DEVICES AND METHODOLOGIES RELATED TO STRUCTURES HAVING HBT AND FET 审中-公开
标题翻译：与具有HBT和FET的结构相关的器件和方法
公开(公告)号：WO2012061632A2
公开(公告)日：2012-05-10
申请号：PCT/US2011/059208
申请日：2011-11-03
申请人： SKYWORK SOLUTIONS, INC. , ZAMPARDI, Peter, J. , SUN, Hsiang-Chih
发明人： ZAMPARDI, Peter, J. , SUN, Hsiang-Chih
IPC分类号： H01L27/10 , H01L27/06 , H01L29/78 , H01L29/737
CPC分类号： H01L27/0605 , H01L21/8252
摘要： A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material that forms the collector layer of the HBT. In some implementations, a second FET can be provided so as to be located over the substrate and configured to include a channel formed in a semiconductor material that forms an emitter of the HBT. One or more of the foregoing features can be implemented in devices such as a die, a packaged module, and a wireless device.
摘要翻译：半导体结构包括包含位于衬底之上的集电极层的异质结双极晶体管（HBT），所述集电极层包括半导体材料以及位于所述衬底之上的场效应晶体管（FET），所述 FET具有形成在形成HBT的集电极层的半导体材料中的沟道。在一些实现中，可以提供第二FET以便位于衬底之上并且被配置成包括形成在形成HBT的发射极的半导体材料中的沟道。一个或多个前述特征可以在诸如管芯，封装模块和无线设备的器件中实现。

7. 发明申请

WO2013188694A1 PROCESS-COMPENSATED HBT POWER AMPLIFIER BIAS CIRCUITS AND METHODS 审中-公开
标题翻译：过程补偿HBT功率放大器偏置电路和方法
公开(公告)号：WO2013188694A1
公开(公告)日：2013-12-19
申请号：PCT/US2013/045720
申请日：2013-06-13
申请人： SKYWORKS SOLUTIONS, INC.
发明人： RIPLEY, David, Steven , LEHTOLA, Philip, John , ZAMPARDI, Peter, J. , SHAO, Hongxiao , KO, Tin, Myint , OZALAS, Matthew, Thomas
IPC分类号： H03F1/30 , H03F3/19
CPC分类号： H03F3/195 , H01L21/8252 , H01L23/552 , H01L23/66 , H01L25/16 , H01L27/0605 , H01L27/0658 , H01L29/20 , H01L29/7304 , H01L29/7371 , H01L29/8605 , H01L2223/6611 , H01L2223/665 , H01L2224/48091 , H01L2224/48227 , H01L2924/1305 , H01L2924/19107 , H01L2924/3025 , H03F1/302 , H03F3/191 , H03F3/21 , H03F3/211 , H03F3/213 , H03F2200/18 , H03F2200/318 , H03F2200/411 , H03F2200/555 , H04B1/3827 , H04B1/40 , H01L2924/00014 , H01L2924/00
摘要： The present disclosure relates to a system for biasing a power amplifier. The system can include a first die that includes a power amplifier circuit and a passive component having an electrical property that depends on one or more conditions of the first die. Further, the system can include a second die including a bias signal generating circuit that is configured to generate a bias signal based at least in part on measurement of the electrical property of the passive component of the first die.
摘要翻译：本公开涉及一种用于偏置功率放大器的系统。该系统可以包括第一管芯，其包括功率放大器电路和具有取决于第一管芯的一个或多个条件的电特性的无源部件。此外，该系统可以包括第二管芯，其包括偏置信号产生电路，该偏置信号产生电路被配置为至少部分地基于第一管芯的无源部件的电性能的测量来产生偏置信号。

8. 发明申请

WO2004077504A2 GALLIUM ARSENIDE HBT HAVING INCREASED PERFORMANCE AND METHOD FOR ITS FABRICATION 审中-公开
标题翻译：耐高温凝胶HBT具有增强的性能及其制造方法
公开(公告)号：WO2004077504A2
公开(公告)日：2004-09-10
申请号：PCT/US2004/003979
申请日：2004-02-10
申请人： SKYWORKS SOLUTIONS, INC.
发明人： ZAMPARDI, Peter, J. , CHOI, Kevin , RUSHING, Lance, G.
IPC分类号： H01L
CPC分类号： H01L29/66318 , H01L29/1004 , H01L29/2003 , H01L29/7371
摘要： According to one exemplary embodiment, a gallium arsenide heterojunction bipolar transistor comprises a collector layer and a first spacer layer situated over the collector layer, where the first spacer layer is a high-doped P+ layer. For example, the first spacer layer may comprise GaAs doped with carbon. The gallium arsenide heterojunction bipolar transistor further comprises a base layer situated over the first spacer layer. The base layer may comprise, for example, a concentration of indium, where the concentration of indium is linearly graded in the base layer. The base layer may comprise InGaAsN, for example. The gallium arsenide heterojunction bipolar transistor further comprises an emitter layer situated over the base layer. The emitter layer may comprise, for example, InGaP.
摘要翻译：根据一个示例性实施例，砷化镓异质结双极晶体管包括集电极层和位于集电极层之上的第一间隔层，其中第一间隔层是高掺杂P +层。例如，第一间隔层可以包括掺杂有碳的GaAs。砷化镓异质结双极晶体管还包括位于第一间隔层上方的基层。基底层可以包括例如铟的浓度，其中铟的浓度在基层中线性分级。基底层可以包括例如InGaAsN。砷化镓异质结双极晶体管还包括位于基极层之上的发射极层。发射极层可以包括例如InGaP。

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