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1. 发明申请

WO2013184959A1 A BI-MODAL POWER DELIVERY SCHEME FOR INTEGRATED CIRCUITS THAT ENABLES FINE GRAIN POWER MANAGEMENT FOR MULTIPLE FUNCTIONAL BLOCKS ON A SINGLE DIE 审中-公开
标题翻译：用于集成电路的双模式电力输送方案，用于在单个模具上实现多功能块的精细电力管理
公开(公告)号：WO2013184959A1
公开(公告)日：2013-12-12
申请号：PCT/US2013/044590
申请日：2013-06-06
申请人： QUALCOMM INCORPORATED
发明人： KOLLA, Yeshwant Nagaraj , FISCHER, Jeffrey Herbert , FLEDERBACH, Darren P.
IPC分类号： G06F1/26 , G06F1/32 , H02M3/155
CPC分类号： G06F1/26 , G06F1/32 , G06F1/3203 , Y02D10/124
摘要： Systems and methods for bi-modal and fine grained power delivery to an integrated circuit (200) comprising functional blocks (202 1 ...202 M ). A first power source (210) is coupled to a functional block (202 1 ) of the integrated circuit for supporting a first operating mode of the functional block. A second power source (204 1 ) is coupled to the functional block for supporting a second operating mode of the functional block. The first and second operating modes can be high and low frequency modes respectively. The second power source can be derived from the first power source using on-die regulators or provided independently (254). A desired average throughput of the functional block can be achieved by controlling duty cycles of the first and second power sources.
摘要翻译：用于向包括功能块（2021 ... 202M）的集成电路（200）进行双模和细粒度功率传送的系统和方法。第一电源（210）耦合到集成电路的功能块（2021），用于支持功能块的第一操作模式。第二电源（2041）耦合到功能块，用于支持功能块的第二操作模式。第一和第二种工作模式可分别为高频和低频模式。第二电源可以使用片上稳压器从第一电源得到，或独立提供（254）。可以通过控制第一和第二电源的占空比来实现功能块的期望平均吞吐量。

2. 发明申请

WO2013149040A1 A PULSE CLOCK GENERATION LOGIC WITH BUILT-IN LEVEL SHIFTER AND PROGRAMMABLE RISING EDGE AND PULSE WIDTH 审中-公开
标题翻译：具有内置电平变化的脉冲时钟发生逻辑和可编程上升沿和脉冲宽度
公开(公告)号：WO2013149040A1
公开(公告)日：2013-10-03
申请号：PCT/US2013/034414
申请日：2013-03-28
申请人： QUALCOMM INCORPORATED
发明人： GE, Shaoping , CHAI, Chiaming , LILES, Stephen Edward , NGUYEN, Lam V. , FISCHER, Jeffrey Herbert
IPC分类号： G06F1/04 , G11C7/22 , G11C11/419
CPC分类号： G06F1/04 , G11C7/222 , G11C11/417 , G11C11/418 , G11C11/419
摘要： Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit (100) includes a selective delay logic (102) to provide a programmable rising edge delay of the pulse clock (114), a selective pulse width widening logic (110) to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.
摘要翻译：用于产生具有可编程边沿和脉冲宽度的脉冲时钟的系统和方法，其配置用于不同的存储器访问操作的需求。脉冲时钟产生电路（100）包括提供脉冲时钟（114）的可编程上升沿延迟的选择延迟逻辑（102），选择脉冲宽度加宽逻辑（110），以提供脉冲时钟的可编程脉冲宽度以及用于移位脉冲时钟的电压电平的内置电平移位器。读操作的上升沿延迟被编程为对应于期望的读数组访问延迟，并且用于写操作的脉冲宽度被编程为比读操作的脉冲宽度宽。

3. 发明申请

WO2013109680A1 MIMICKING MULTI-VOLTAGE DOMAIN WORDLINE DECODING LOGIC FOR A MEMORY ARRAY 审中-公开
标题翻译：用于存储阵列的多电平域域字线解码逻辑
公开(公告)号：WO2013109680A1
公开(公告)日：2013-07-25
申请号：PCT/US2013/021824
申请日：2013-01-17
申请人： QUALCOMM INCORPORATED
发明人： GE, Shaoping , CHAI, Chiaming , LILES, Stephen E. , NGUYEN, Lam V. , FISCHER, Jeffrey Herbert
IPC分类号： G11C8/08 , G11C8/10 , G11C7/22
CPC分类号： G11C8/08 , G11C7/12 , G11C7/22 , G11C7/227 , G11C8/10
摘要： Systems and methods for adaptively mimicking word line decoding logic for multi-voltage domain memory are disclosed. In one embodiment, the multi-voltage domain memory includes a memory array implemented in a high voltage domain and a multi-voltage domain control circuit. The multi-voltage domain control circuit includes multi-voltage domain decoding logic that generates a word line select signal for the memory array and a multi-voltage domain mimic logic that mimics the multi-voltage domain decoding logic to generate a dummy wordline signal. In one embodiment, the dummy word line signal is utilized to trigger an ending edge (e.g., a falling edge) of the word line select signal once the word line is asserted. In addition or alternatively, the dummy word line signal is utilized to generate one or more control signals for the memory array such as, for example, a pre-charge control signal and/or a sense amplifier enable signal.
摘要翻译：公开了用于自适应模拟用于多电压域存储器的字线解码逻辑的系统和方法。在一个实施例中，多电压域存储器包括以高电压域实现的存储器阵列和多电压域控制电路。多电压域控制电路包括产生用于存储器阵列的字线选择信号的多电压域解码逻辑和模拟多电压域解码逻辑以产生伪字线信号的多电压域模拟逻辑。在一个实施例中，一旦该字线被断言，该虚拟字线信号用于触发字线选择信号的结束边缘（例如，下降沿）。另外或替代地，伪字线信号用于产生用于存储器阵列的一个或多个控制信号，例如预充电控制信号和/或读出放大器使能信号。

4. 发明申请

WO2007051205A1 HIGH SPEED CAM LOOKUP USING STORED ENCODED KEY 审中-公开
标题翻译：使用存储编码键的高速凸轮
公开(公告)号：WO2007051205A1
公开(公告)日：2007-05-03
申请号：PCT/US2006/060371
申请日：2006-10-30
申请人： QUALCOMM INCORPORATED , FISCHER, Jeffrey Herbert , PHAN, Michael Thaithanh , CHAI, Chiaming , DIEFFENDERFER, James Norris
发明人： FISCHER, Jeffrey Herbert , PHAN, Michael Thaithanh , CHAI, Chiaming , DIEFFENDERFER, James Norris
IPC分类号： G11C15/04
CPC分类号： G11C15/00 , G06F12/1027 , G06F2212/652 , G11C15/04
摘要： The search key and key fields of a CAM in a cache are encoded with a Hamming distance of at least two to increase the speed of the CAM by ensuring each mismatching match line is discharged by at least two transistors in parallel. Where the cache is physically tagged, the search key is a physical address. The page address portion of the physical address is encoded prior to being stored in a TLB. The page offset bits are encoded in parallel with the TLB access, and concatenated with the encoded TLB entry. If a page address addresses a large memory page size, a plurality of corresponding sub-page addresses may be generated, each addressing a smaller page size. These sub-page addresses may be encoded and stored in a micro TLB. The encoded key and key field are tolerant of single-bit soft errors.
摘要翻译：高速缓存中的CAM的搜索键和关键字段通过至少两个汉明距离进行编码，以通过确保每个不匹配的匹配线由并联的至少两个晶体管放电来增加CAM的速度。在缓存物理标记的地方，搜索关键字是物理地址。物理地址的页地址部分在被存储在TLB中之前被编码。页面偏移位与TLB访问并行编码，并与编码的TLB条目连接。如果页面地址满足大的存储器页面大小，则可以生成多个对应的子页面地址，每个地址寻址较小的页面大小。这些子页地址可以被编码并存储在微型TLB中。编码的密钥和密钥字段容忍单位软错误。

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