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1. 发明申请

WO2007103745A2 AT-SPEED MULTI-PORT MEMORY ARRAY TEST METHOD AND APPARATUS 审中-公开
标题翻译： AT速多端口存储器阵列测试方法和装置
公开(公告)号：WO2007103745A2
公开(公告)日：2007-09-13
申请号：PCT/US2007063097
申请日：2007-03-01
申请人： QUALCOMM INC , KRISHNAMURTHY ANAND , MUMFORD CLINT WAYNE , MAMILETI LAKSHMIKANT , PATEL SANJAY B
发明人： KRISHNAMURTHY ANAND , MUMFORD CLINT WAYNE , MAMILETI LAKSHMIKANT , PATEL SANJAY B
CPC分类号： G11C29/34 , G11C8/16
摘要： A multi-port memory array is tested by simultaneously writing data to the array via two or more write ports, and/or simultaneously reading data from the array via two or more read ports, at the processor operating frequency. Comparing the data read from the array to that written to the array may be performed sequentially or in parallel. Comparator circuits are effectively disabled during normal processor operations. By simultaneously writing and/or reading data via multiple ports, latent electrical marginalities may be exposed. In addition, writing test patterns using multiple write ports and reading the patterns using multiple read ports significantly reduces test time during semiconductor manufacturing tests.
摘要翻译：多端口存储器阵列通过以两个或更多个写入端口同时将数据写入阵列和/或以处理器工作频率同时经由两个或更多个读取端口从阵列读取数据来测试多端口存储器阵列。比较从阵列读取的数据和写入阵列的数据可以按顺序或并行执行。比较器电路在正常处理器操作期间被有效地禁用。通过经由多个端口同时写入和/或读取数据，可能暴露潜在的电气边界。此外，使用多个写入端口写入测试模式并使用多个读取端口读取模式可显着缩短半导体制造测试期间的测试时间。

2. 发明申请

WO2003009304A2 DUTY-CYCLE-EFFICIENT SRAM CELL TEST 审中-公开
标题翻译：周期性高效SRAM单元测试
公开(公告)号：WO2003009304A2
公开(公告)日：2003-01-30
申请号：PCT/EP2002/008472
申请日：2002-07-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , COMPAGNIE IBM FRANCE
发明人： IMBERT DE TREMIOLLES, Ghislain , TANNHOF, Pascal
IPC分类号： G11C29/00
CPC分类号： G11C29/28 , G11C29/34
摘要： A method and structure for the invention includes an integrated memory structure having a built-in test portion. The integrated memory structure has memory cells, bitlines and wordlines connected to the memory cells, wordline decoders connected to a plurality of the wordlines, bitline restore devices connected to the bitlines for charging the bitlines during read and write operations, and a clock circuit connected to the wordlines. During a test mode the wordline decoders simultaneously select multiple wordlines that the bitline restore devices maintain in an active state and the clock circuit maintains the multiple wordlines and the bitline restore devices in an active state for a period in excess of a normal read cycle. The invention also includes transistors which are connected to the memory cells. The transistors include bitline contacts which are stressed during the test mode.
摘要翻译：本发明的方法和结构包括具有内置测试部分的集成存储器结构。集成存储器结构具有连接到存储器单元的存储单元，位线和字线，连接到多个字线的字线解码器，连接到位线的位线恢复器件，用于在读和写操作期间对位线充电;以及时钟电路，字线。在测试模式期间，字线解码器同时选择位线恢复装置保持在活动状态的多个字线，并且时钟电路将多个字线和位线恢复装置维持在超过正常读周期的周期内处于活动状态。本发明还包括连接到存储单元的晶体管。晶体管包括在测试模式期间受应力的位线触点。

3. 发明申请

WO99023666A1 CIRCUIT AND METHOD FOR STRESS TESTING EEPROMS 审中-公开
标题翻译：用于应力测试的电路和方法
公开(公告)号：WO99023666A1
公开(公告)日：1999-05-14
申请号：PCT/US1998/012885
申请日：1998-06-19
IPC分类号： G11C29/20 , G11C29/34 , G11C29/00
CPC分类号： G11C29/34 , G11C29/20
摘要： A circuit and method are provided for stress-testing EEPROMS by incrementally selecting and deselecting word lines. The circuit of the invention comprises a memory cell array, a set of decoders for decoding a memory address bus and controlling word lines for the memory cell array, a control circuit, and a shift register driven by the control circuit. Each bit of the shift register has the capability of overriding a group of one or more of the decoders. When the initiation signal is received by the control circuit, a state control bit is set high and is clocked through the shift register. The high bit overrides successive groups of decoders as it is shifted through the shift register, until all word lines in the memory cell array are selected. After the stress test has been performed, the state control bit is returned to zero and is cycled through the shift register on successive clock cycles, incrementally deselecting groups of word lines until all word lines are deselected.
摘要翻译：提供电路和方法，通过逐步选择和取消选择字线来对EEPROMS进行应力测试。本发明的电路包括存储单元阵列，用于解码存储器地址总线和控制存储单元阵列的字线的解码器组，控制电路和由控制电路驱动的移位寄存器。移位寄存器的每个位具有覆盖一组或多个解码器的能力。当控制电路接收到启动信号时，状态控制位被置为高电平并通过移位寄存器计时。当它被移位通过移位寄存器时，高位将覆盖连续的解码器组，直到选择存储单元阵列中的所有字线为止。在执行了应力测试之后，状态控制位返回到零，并在连续的时钟周期循环通过移位寄存器，逐渐取消选择字线组，直到所有字线被取消选择。

4. 发明申请

WO98054729A1 METHOD AND APPARATUS FOR SELF-TESTING MULTI-PORT RAMS 审中-公开
标题翻译：自动测试多端口RAMS的方法和设备
公开(公告)号：WO98054729A1
公开(公告)日：1998-12-03
申请号：PCT/CA1998/000150
申请日：1998-02-25
IPC分类号： G11C29/34 , G11C29/00
CPC分类号： G11C29/34
摘要： It discloses novel BIST controller which detects single port faults and inter-port shorts in multi-port random access memories. The algorithm performs a conventional single-port test such as MARCH or SMARCH on one port of the memory and performs an inter-port test on all other ports. The algorithm does not impose any extra test time and requires the addition of only a few gates to a conventional single-port BIST controller, independently of the size of the memory.
摘要翻译：它公开了新颖的BIST控制器，它检测多端口随机存取存储器中的单端口故障和端口间短路。该算法在存储器的一个端口上执行常规的单端口测试，例如MARCH或SMARCH，并在所有其他端口上执行端口间测试。该算法不会施加任何额外的测试时间，并且要求仅与传统的单端口BIST控制器相加的只有几个门，而与存储器的大小无关。

5. 发明申请

WO2014120903A1 NONVOLATILE LOGIC ARRAY WITH BUILT-IN TEST RESULT SIGNAL 审中-公开
标题翻译：非线性逻辑阵列与内置测试结果信号
公开(公告)号：WO2014120903A1
公开(公告)日：2014-08-07
申请号：PCT/US2014/013811
申请日：2014-01-30
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： BARTLING, Steven, Craig , KHANNA, Sudhanshu
IPC分类号： G11C29/12 , G06F11/277 , G01R31/3193
CPC分类号： G11C29/08 , G11C11/22 , G11C11/401 , G11C14/0072 , G11C29/02 , G11C29/12 , G11C29/34 , G11C29/50 , G11C29/50016 , G11C2029/0401
摘要： A system on chip (SoC) (100) provides a nonvolatile memory array (1 10) that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines. An AND gate is coupled to the m bit lines and has an output line coupled to an input of a test controller on the SoC. An OR gate is coupled to the m bit lines and has an output line coupled to an input of the test controller.
摘要翻译：片上系统（SoC）（100）提供了被配置为n行×m位的位单元的非易失性存储器阵列（110）。每个位单元被配置为存储一位数据。存在m个位线，每个位线耦合到位单元的m列的相应一个。存在m个写入驱动器，每个写入驱动器耦合到m个位线中的相应一个位线。与门耦合到m位线，并且具有耦合到SoC上的测试控制器的输入的输出线。 OR门耦合到m位线，并且具有耦合到测试控制器的输入的输出线。

6. 发明申请

WO99043004A1 CIRCUIT AND METHOD FOR TESTING A DIGITAL SEMI-CONDUCTOR CIRCUIT 审中-公开
标题翻译：测试电路及方法测试一台数字半导体电路
公开(公告)号：WO99043004A1
公开(公告)日：1999-08-26
申请号：PCT/DE1998/002895
申请日：1998-09-30
IPC分类号： G01R31/3183 , G01R31/28 , G11C29/10 , G11C29/26 , G11C29/34 , G11C29/36 , G11C29/38 , G11C29/00
CPC分类号： G11C29/36 , G11C29/26 , G11C29/34 , G11C29/38
摘要： The present invention relates to a monolithic-integration test circuit used for checking a digital semi-conductor circuit formed on the same semi-conductor chip and comprising the following members: a plurality of elements to be checked; a checking-data model register for the intermediate storing of a checking-data model; a read- and write-circuit for writing data from the checking-data model register into the elements to be checked and for reading said data from said elements; and a comparison circuit (6) for determining whether or not a difference occurs between the written and read data in the elements to be checked. The test circuit comprises a model modification circuit (2) which can be actuated by an activation signal (3) and which modifies the checking-data model from the checking-data model register before writing the data in the elements to be checked.
摘要翻译：本发明涉及一种单片集成测试电路，用于测试形成于具有多个测试元件的同一半导体芯片的数字半导体电路装置，一个Prüfdatenmusterregister（1）用于测试数据模式，读出的中间存储和写入用于写入电路和读取Prüfdatenmusterregisters的数据在并从测试元件，并通过一个比较电路（6），其被检查测试元件的内切和读出的数据的差异。测试电路包括一个由激活信号（3）将被激活图案变化（2），该写入元件进行测试之前改变从Prüfdatenmusterregister校验数据。

7. 发明申请

WO99017298A1 METHOD FOR TESTING A SOLID STATE MEMORY 审中-公开
标题翻译：方法测试半导体STORE
公开(公告)号：WO99017298A1
公开(公告)日：1999-04-08
申请号：PCT/DE1998/002617
申请日：1998-09-04
IPC分类号： G11C29/34 , G11C29/46 , G11C29/50 , G11C29/00
CPC分类号： G11C29/50 , G11C11/401 , G11C29/34 , G11C29/46
摘要： The suggested method enables a solid state memory to be switched from the operating state to a test state and a test mode to be selected from among various options. For that purpose, only the connections specific to a regular solid state memory are used, especially the address access types and the access systems SAD and CAS. The possibility of doing without the PAD connections specific to the memory and having them switched to the test mode enables some surface of the solid state memory to be saved. The invention finds its applications mainly in the field of dynamic semiconductor memories.
摘要翻译：本发明的方法使得能够从运行状态切换的半导体存储器的测试的状态，并选择以不同的方式的测试模式。只有连接被使用的，具有半导体存储器中，通常，例如用于RAS和CAS地址输入和输入。在其特征上自己的终端（焊盘）的测试条件被省略，芯片面积得以节省。本发明的应用主要在于动态半导体存储器。

8. 发明申请

WO1995024774A2 MEMORY IDDQ-TESTABLE THROUGH CUMULATIVE WORD LINE ACTIVATION 审中-公开
标题翻译：记忆IDDQ可通过累积字线激活测试
公开(公告)号：WO1995024774A2
公开(公告)日：1995-09-14
申请号：PCT/IB1995000106
申请日：1995-02-15
申请人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB
发明人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB , SACHDEV, Manoj
IPC分类号： H04B00/00
CPC分类号： G11C29/50 , G11C8/04 , G11C8/12 , G11C11/41 , G11C29/34 , G11C2029/5006
摘要： An SRAM has a plurality of respective memory cells coupled to a respective one of a plurality of word lines and to a pair of bit lines. The SRAM comprises IDDQ test means to render the word lines active in parallel by cumulatively increasing a number of active ones among the word lines. This permits the writing of a specific logic state in all cells of a column through the tiny bit line drivers that are progressively assisted by the cells already written, thus avoiding the use of additional heavy write circuitry for IDDQ test purposes only.
摘要翻译： SRAM具有耦合到多个字线中的相应一个字线和一对位线的多个相应存储器单元。 SRAM包括IDDQ测试装置，用于通过累积增加字线中的活动字数来使字线平行活动。这允许通过由已经写入的单元逐步辅助的微小位线驱动器在列的所有单元中写入特定的逻辑状态，因此避免使用用于IDDQ测试目的的附加重写电路。

9. 发明申请

WO1981000154A1 PROGRAMMABLE READ ONLY MEMORY INTEGRATED CIRCUIT WITH BITCHECK AND DEPROGRAMMING MODES AND METHODS FOR PROGRAMMING AND TESTING SAID CIRCUIT 审中-公开
标题翻译：可编程只读存储器集成电路，具有双向转换和分频模式，并编程和测试电路的方法
公开(公告)号：WO1981000154A1
公开(公告)日：1981-01-22
申请号：PCT/US1980000828
申请日：1980-07-01
申请人： MOSTEK CORP
发明人： MOSTEK CORP , MCKENNEY V , HAMPTON J
IPC分类号： G06F11/00
CPC分类号： G11C29/50 , G06F2201/81 , G11C16/34 , G11C17/14 , G11C29/34 , G11C2029/5004
摘要： A programmable read only memory (PROM) integrated circuit is constructed with two new operating modes: a bit-check mode and a deprogramming mode. In the bitcheck mode, circuitry is provided to readily determine the apparent threshold voltage of each programmable transistor within the PROM. In the deprogramming mode, circuitry is provided to simultaneously subject all programmable transistors within the PROM to a deprogramming stress. The bitcheck mode provides a rapid programming method, and the bit-check mode and deprogramming mode are utilized in conjunction with each other to provide a rapid and thorough testing method.

10. 发明申请

WO2011007304A1 USING STORAGE CELLS TO PERFORM COMPUTATION 审中-公开
标题翻译：使用储存细胞进行计算
公开(公告)号：WO2011007304A1
公开(公告)日：2011-01-20
申请号：PCT/IB2010/053168
申请日：2010-07-11
申请人： ZIKBIT LTD. , AKERIB, Avidan , AGAM, Oren , EHRMAN, Eli , MEYASSED, Moshe
发明人： AKERIB, Avidan , AGAM, Oren , EHRMAN, Eli , MEYASSED, Moshe
IPC分类号： G06F13/00
CPC分类号： G11C29/34 , G11C15/043
摘要： An in-memory processor includes a memory array which stores data and an activation unit to activate at least two cells in a column of the memory array at generally the same time thereby to generate a Boolean function output of the data of the at least two cells. Another embodiment shows a content addressable memory (CAM) unit using memory array cells.
摘要翻译：存储器内处理器包括存储数据的存储器阵列和激活单元，用于在大致相同的时间激活存储器阵列的列中的至少两个单元，从而生成至少两个单元的数据的布尔函数输出。另一个实施例示出了使用存储器阵列单元的内容可寻址存储器（CAM）单元。

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